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256 Commits

Author SHA1 Message Date
Milczarek, Slawomir
6c8b14c918 OmitTimestampPacketDependencies to omit node dependency in timestamp packet 
Makes subcapture feature work with timestamp packet enabled.

Related-To: NEO-2747

Change-Id: Ifa45f1c066129671a02dc708b537b285f5a05d7f
Signed-off-by: Milczarek, Slawomir <slawomir.milczarek@intel.com>
 2019-05-07 16:05:00 +02:00
Mrozek, Michal
bc35cd250a Do not use max power saving mode in VA sharing scenarios. 
-This can be achieved by passing CL_QUEUE_THROTTLE_LOW_KHR as throttle hint
to command queue.
- This gives much better control about the granularity of this feature
instead of triggering this for the whole context user may still have
power saving mode queues.

Change-Id: I066729f963119ddc1f62ad2785c342af2fea588e
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
 2019-05-07 15:23:13 +02:00
Filip Hazubski
445ee08ace Fix typo 
Change-Id: I8cd853e00da7a09d20e7a43e366f1e2c45a7230c
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2019-04-25 20:22:50 +02:00
Mrozek, Michal
22c2c9b02c Change the size of aux translation transfer. 
Change-Id: I9b34babf26eee217c203d0c09d819765a45a9506
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
 2019-04-20 15:45:07 +02:00
Piotr Fusik
086ef7c461 Simplify code by introducing TimestampPacketStorage::Packet. 
Related-To: NEO-2872

Change-Id: Ifce455f1a48f2db2bf16af2dd32208ee4542204d
Signed-off-by: Piotr Fusik <piotr.fusik@intel.com>
 2019-04-18 16:14:04 +02:00
Piotr Fusik
745c20c78a Rename TimestampPacket to TimestampPacketStorage. 
Related-To: NEO-2872

Change-Id: Id1f78491912c44890ae7ead2cac12ec8eb073628
Signed-off-by: Piotr Fusik <piotr.fusik@intel.com>
 2019-04-16 15:34:28 +02:00
Maciej Plewka
da19e924f5 Add events support for cache flushes 
Related-To: NEO-2536

Change-Id: Iea9e9b08df0225ce5a126ab950621576b3880bbe
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2019-04-15 15:44:25 +02:00
Piotr Fusik
543b3d39d0 Use CPU pointers for TimestampPacket where appropriate. 
Related-To: NEO-2872

Change-Id: Ic91a1dd6252d2970e20bb32c3d867449041cbb8a
Signed-off-by: Piotr Fusik <piotr.fusik@intel.com>
 2019-04-15 10:55:12 +02:00
Mrozek, Michal
501a521120 Do 4 byte transfers for full copy kernel. 
- Also utilize mem object allocation size for aux translation.

Change-Id: I117e4d17b2c8e2acc8395381f36f3019d6987314
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
 2019-04-11 15:49:46 +02:00
Maciej Plewka
4eb48e3d06 Add function to flush caches 
Related-To: NEO-2536

Change-Id: Ifbf7e7a42514dd66eb0914f9d13407287481e123
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2019-04-05 09:48:50 +02:00
Filip Hazubski
b2e16b7897 Update allocationForCacheFlush method 
Related-To: NEO-2535

Change-Id: Ia24556814188263e2ebb54b6419feddd5d8ed707
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2019-04-03 18:07:13 +02:00
Mateusz Jablonski
f3d17008ee TransferProperties: lock resource only when transfer on CPU is requested 
Change-Id: Ic93b4fd438e75f5d54cbae9bec332c4b18c6b1ee
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2019-04-01 14:02:49 +02:00
Kamil Diedrich
0ff6358c17 Add method checkResourceCompatibility 
Change-Id: I858f54cbeac86121882ca0dec1a5f35eca034dbd
Signed-off-by: Kamil Diedrich <kamil.diedrich@intel.com>
 2019-04-01 11:12:32 +02:00
Jobczyk, Lukasz
a025dc6985 Reverse logic of creating Memory Manager - part 6 
-Remove a redundant condition from the MemoryManager constructor

Change-Id: I4b6c56f30a19e77a7a20f68c6d85516aaa52d102
Signed-off-by: Jobczyk, Lukasz <lukasz.jobczyk@intel.com>
 2019-04-01 10:27:29 +02:00
Piotr Fusik
d4a0c4852b Move EngineType to aub_stream. 
Change-Id: Ieaa75aaf4aca4487833754eb38ff709adcbf0f11
Signed-off-by: Piotr Fusik <piotr.fusik@intel.com>
 2019-03-27 10:06:29 +01:00
Maciej Plewka
9e52684f5b Change namespace from OCLRT to NEO 
Change-Id: If965c79d70392db26597aea4c2f3b7ae2820fe96
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2019-03-26 15:48:19 +01:00
Mateusz Hoppe
047f2bec87 Program correct addresses in EnqueueReadWriteBufferRect scenarios 
- SurfaceBaseAddress should be programmed with aligned address
this was not the case for certain origin and region values
- offset from aligned address added to operationParams

Change-Id: I0742b826dd0b70f0a6dedf436b850734fa015688
Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
 2019-03-26 10:37:46 +01:00
Jobczyk, Lukasz
9ecb3193af Reverse logic of creating Memory Manager - part 3 
-Move a Device::getEnabled64kbPages method's logic
 to the Memory Manager constructor

Change-Id: Ide88898000e5817a79f9a6ad5dfc9d680bec0533
Signed-off-by: Jobczyk, Lukasz <lukasz.jobczyk@intel.com>
 2019-03-25 14:42:16 +01:00
Maciej Dziuban
33c07c875f Do not insert PipeControl WA or DC Flush when not needed 
Change-Id: I71030273708f243324a566232528bce00a0361df
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
 2019-03-22 12:37:27 +01:00
Stefanowski, Adam
16aee8cc46 [2/n] Move Hardware Info to Execution Environment 
- remove hwInfo from the csr functions where it was passed as a parameter,
now csr functions have access to hwInfo by Execution Environment

Change-Id: I756ae63d9728c9c963571147bab97f9e1c15797b
Signed-off-by: Adam Stefanowski <adam.stefanowski@intel.com>
 2019-03-22 10:08:26 +01:00
Piotr Fusik
db9afd06cd Remove EngineInstanceT. 
Change-Id: I08543b5f4ef5e91e6beb8390d448e53702cd9dac
Signed-off-by: Piotr Fusik <piotr.fusik@intel.com>
 2019-03-20 10:56:22 +01:00
Venevtsev, Igor
3c1bb4a3f8 ptrOffset and ptrDiff do not truncate uint64_t to uintptr_t 
Change-Id: I0dcaf058ae3244ca0168580d972a19f9e4692e05
Signed-off-by: Venevtsev, Igor <igor.venevtsev@intel.com>
 2019-03-18 16:01:06 +01:00
Mateusz Jablonski
395e79fee8 Add support for many GMMs in Graphics Allocation 
Change-Id: I955b8dd50b502f91700c5529d0a0a291632aa157
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2019-03-13 15:44:45 +01:00
Stefanowski, Adam
341fcfc091 [1/n] Move Hardware Info to Execution Environment 
- remove gmm_environment_fixture
- remove hwInfo parameter from ExecutionEnvironment methods

Change-Id: Ieb0f9b5b89191fbbaf7676685c77644d42d69c26
Signed-off-by: Adam Stefanowski <adam.stefanowski@intel.com>
 2019-03-12 08:39:26 +01:00
Jobczyk, Lukasz
4386d10e40 Reverse logic of creating Memory Manager - part 2 
-remove MM initialization from Device::CreateEngines method

Change-Id: Iaee268b002cb0f0a4edd07907c12da6dd6076b3a
Signed-off-by: Jobczyk, Lukasz <lukasz.jobczyk@intel.com>
 2019-03-08 14:52:55 +01:00
Piotr Fusik
a2c05a241d Set allocationType in constructors. 
Change-Id: I66738be1239acdaf282f813aed46066bc5023112
Signed-off-by: Piotr Fusik <piotr.fusik@intel.com>
 2019-03-06 16:07:28 +01:00
Maciej Plewka
e53a8e8709 Add postSyncAddress to flush after walker 
Change-Id: I7fdfaf8e0acc365998cc74306ab715ea3d9c7d72
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2019-03-04 14:47:53 +01:00
Mateusz Jablonski
00184c4e2e Rename fastLeakDetectionMode -> fastLeakDetectionEnabled 
Change-Id: I5a35b2bb9a3ccea9b8e52660f3713b925fe5f607
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2019-03-04 11:51:06 +01:00
Mateusz Jablonski
6fb28dd828 Refactor GraphicsAllocation class 
move most of members to protected section
merge related members into structs

Change-Id: Ief2e092aa5e61ca6f13308f9d9b1937ea6c913b4
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2019-02-28 14:09:11 +01:00
Filip Hazubski
8b57d28116 clang-format: enable sorting includes 
Include files are now grouped and sorted in following order:
1. Header file of the class the current file implements
2. Project files
3. Third party files
4. Standard library

Change-Id: If31af05652184169f7fee1d7ad08f1b2ed602cf0
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2019-02-27 11:50:07 +01:00
Dunajski, Bartosz
4597759a65 Dont inherit TimestampPacket from Waitlist when doesnt exist 
Change-Id: I12b184353243f99ec7bacdf2dcd9da1ba09e3516
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-02-27 09:15:48 +01:00
Piotr Fusik
d79f1afdc2 GraphicsAllocation constructor accepts allocationType and memoryPool. 
Change-Id: I5044ed26ba0cb0fc9ca7077595f5ab56353ab58c
 2019-02-26 13:29:25 +01:00
Piotr Fusik
4ec5be0c99 Simplify code by removing AllocationOrigin. 
Change-Id: Ie73cefc1ae1ee846fb9a5ef1054af01cd1867a4d
 2019-02-21 16:29:05 +01:00
Maciej Dziuban
90e970cee6 Create GraphicsAllocation during dispatch when queue is blocked 
Change-Id: I8a6f9e14ff57e7ed2920260af291317805f4df13
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
 2019-02-21 15:28:17 +01:00
Piotr Fusik
3e2a2ec191 Do not truncate to size_t while aligning. 
Change-Id: If92e3b20c0ba08a6024116a44463c72ff4cfddce
 2019-02-21 14:18:34 +01:00
Piotr Fusik
f014f27370 Support the EnableLocalMemory debug variable in CSR. 
Change-Id: I902b06ab0b4a3df477d12804ba74b2727d8863f6
 2019-02-12 13:09:23 +01:00
Mrozek, Michal
2cb3181359 Remove OCLRT name space from helpers. 
Change-Id: Ia33aa7ce93a8f3ee8b2b5609de9ac3e32e206ca1
 2019-02-12 09:55:30 +01:00
Venevtsev, Igor
5e8fb19e5d Remove OCL Events concept from EnqueueOperation and dispatchWalker 
Change-Id: Iec55b0be673a2a40b9621212add224a33d4abc5d
 2019-02-12 08:46:18 +01:00
Dunajski, Bartosz
12da1b0616 Remove osContextCount parameter from GraphicsAllocation 
Change-Id: I23b650e97f107008b1122a1ecea48722fe129863
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-02-11 15:44:37 +01:00
Dunajski, Bartosz
dc181defba Use GpuAddress for TimestampPacket programming 
Change-Id: I1303605c33e2e0267a1716e12a0bfcb341fcfbd7
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-02-11 15:31:17 +01:00
Chodor, Jaroslaw
43856e88b5 Refactor around cache flush and command queue 
Change-Id: I277e27cbc60fbbb015c0024f171697408879ec0b
 2019-02-10 17:59:33 +01:00
Venevtsev, Igor
66e3f3c16c Remove OCL Events concept from command stream receiver 
Change-Id: I4d5a97b41efe601c92c2f3f33e9e24bb7d4fa3d2
 2019-02-08 15:02:40 +01:00
Kamil Diedrich
62e56d2398 Disable L3cache when resolve argument 
Change-Id: I4bb3a18d67254eef8aa4a0ce6b29401726f0b47e
 2019-02-06 15:51:31 +01:00
Chodor, Jaroslaw
048098ce66 Refactor around cache flush after walker 
Change-Id: If5c7399df91bd076b684bcab83f50b4852e53429
 2019-02-06 11:12:55 +01:00
Kamil Diedrich
e1eab521e7 use release for cl-objects instead of delete 
- fix for data race in events
- modification of the addition child event

Change-Id: I6ea3a413f13f13a91d37d20d8b9fad37d0ffafb9
 2019-02-05 14:09:32 +01:00
Hoppe, Mateusz
3c47c418a9 Refactor HardwareParse::getSurfaceState() to return CPU memory 
- if SSH indirectHeap is passed, use CPU address instead of GPU
address programed in SBA command

Change-Id: Id2c8973db0dfe2d9562ee835a27c4d3c28ea3351
 2019-02-04 17:49:00 +01:00
Hoppe, Mateusz
509ed273c4 Refactor Ults finding hardware commands 
- use CPU address for found dynamicStateHeap address in
StateBaseAddress command

Change-Id: I2d857c5a069f5a8f46169d2047cdb27efd3502b8
 2019-02-04 17:26:37 +01:00
Chodor, Jaroslaw
7d04159f76 Refactor around cache flush 
Change-Id: Iff32af0111375f4ffc804c82e6d753d57fe94e80
 2019-01-31 22:19:06 +01:00
Chodor, Jaroslaw
9a98f19a2f Adding ULT mechanism for cmdBuff validation 
Change-Id: I35f06695e27b9eb052e2aaa717862ae01db9a0ba
 2019-01-30 18:58:53 +01:00
Mateusz Jablonski
f157943610 Allocate internal allocations through preferred pool 
Change-Id: Ib17431ceefc1eb72f86625e0998f679baaa7cb0d
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2019-01-30 11:18:15 +01:00