Commit Graph

195 Commits

Author SHA1 Message Date
Szymon Morek ec04de61a7 [L0][XE_HPC]Perform memcpy on CPU for non-usm ptrs
Related-To: NEO-7237

If size is small enough, it is more efficient to
perform copy through locked ptr on CPU.
This change also introduces experimental flag to
enable this.

Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2022-09-26 13:20:40 +02:00
Compute-Runtime-Validation f5575a1370 Revert "Remove fallback path for PAT index programming"
This reverts commit faf8d51f6d.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2022-09-23 20:46:31 +02:00
Dunajski, Bartosz faf8d51f6d Remove fallback path for PAT index programming
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-09-21 10:46:43 +02:00
Zbigniew Zdanowicz f656707fc0 Use hardware support flags for state compute mode state changes
Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-08-25 18:46:37 +02:00
Dunajski, Bartosz 595cfebaef Refactor PIPE_CONTROL programming
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-08-23 13:55:25 +02:00
Dunajski, Bartosz a3903c385e Remove HW types from synchronization interface
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-07-25 13:59:26 +02:00
Kamil Kopryk 7c538b956a Correct typo
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
2022-07-14 10:13:12 +02:00
Lukasz Jobczyk 880464da77 Apply additional synchronization WA to DG2 ULLS
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2022-07-06 13:37:56 +02:00
Kamil Kopryk efa19a0b18 Simplify code - reverse helper function logic to avoid not needed negation
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
2022-06-29 09:19:33 +02:00
Bartosz Dunajski 2c853adac3 Use LogicalStateHelper to program ComputeMode
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2022-06-27 15:25:55 +02:00
Compute-Runtime-Validation 1bfe42350a Revert "Disable tlb flush WA on PVC and later"
This reverts commit e0c87435e1.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2022-06-22 20:09:28 +02:00
Lukasz Jobczyk e0c87435e1 Disable tlb flush WA on PVC and later
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2022-06-22 13:09:42 +02:00
Michal Mrozek ef7c1c22cb Rename function name to avoid confusion.
Signed-off-by: Michal Mrozek <michal.mrozek@intel.com>
2022-06-14 18:50:39 +02:00
Katarzyna Cencelewska 96e1eb7467 Move variables baseDieRev and baseDieA0Masked from xe_hpc to pvc
Pvc specific variables should be located in pvc struct

Related-To: NEO-6738
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
2022-05-17 12:19:16 +02:00
Zbigniew Zdanowicz 52a3bfcfde Unify programming of pipe control command
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-05-16 18:42:04 +02:00
Artur Harasimiuk d643c587b9 style: correct variable naming
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
2022-05-16 15:02:15 +02:00
Katarzyna Cencelewska 0b68fdbe52 Move isCooperativeEngineSupported to HwInfoConfig
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
2022-05-12 12:10:23 +02:00
Bartosz Dunajski f8ce86b116 XE_HPC: Fallback path to fix PAT_INDEX programming
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2022-05-05 15:06:21 +02:00
Dominik Dabek 8d1ad5a4f3 Refactor: use stack vector for root device indices
Stack vector will not cause dynamic allocations in most circumstances
ie. number of root device indices not more than 16

Related-To: NEO-6837

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-04-14 14:05:42 +02:00
Krystian Chmielewski ee0d183cf9 Handle legacy hasBarriers properly
Previous change regarding NEO-6785 added encoding of number of barriers
to specific value representation depending on hardware that we program for.

In patch token format encoding of number of barriers is sent via
hasBarriers field in a token.
In zebin true number of barriers is sent via barrier_count field in
zeInfo.

To remove this discrepancy, translate encoded number of barriers into
true number of barriers in legacy format.

Resolves: NEO-6785

Signed-off-by: Krystian Chmielewski <krystian.chmielewski@intel.com>
2022-04-12 09:44:10 +02:00
Bartosz Dunajski 884d729e4e Improve pat index programming on linux
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2022-04-12 08:18:20 +02:00
Krystian Chmielewski 2c1bfbb5b2 Encode number barriers
When programming number of barriers use BARRIER_SIZE enumeration.
Resolves: NEO-6785

Signed-off-by: Krystian Chmielewski <krystian.chmielewski@intel.com>
2022-04-08 10:32:23 +02:00
Filip Hazubski d2462ff8fb Add debug flag to control ISA allocation padding
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2022-04-04 15:12:30 +02:00
Bartosz Dunajski 08e3853982 Debug flag to add extra MI_MEM_FENCE for DirectSubmission
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2022-03-30 16:07:25 +02:00
Compute-Runtime-Validation 91cfd3cd1a Revert "Unify command/ring/semaphore buffers placement"
This reverts commit e035199de4.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2022-03-30 14:05:47 +02:00
Mateusz Jablonski e035199de4 Unify command/ring/semaphore buffers placement
put them all to the same memory location

Related-To: NEO-6698
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-03-29 17:55:48 +02:00
Zbigniew Zdanowicz 9858438121 Limit multiple partition count to compute command lists
Related-To: NEO-6811

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-03-29 07:29:08 +02:00
Jitendra Sharma f52f3df274 Add platform specific getter of debug surface size
For different platforms based on number of available threads
and debug surface layout, calculate max debug surface size.

Related-To: NEO-6676
Signed-off-by: Jitendra Sharma <jitendra.sharma@intel.com>
2022-03-22 12:18:40 +01:00
Filip Hazubski 80b520bc9b Change ThreadArbitrationPolicy enum type to int32_t
Change ThreadArbitrationPolicy::NotPresent value to -1
Update initial values to ThreadArbitrationPolicy::NotPresent

Related-To: NEO-6728

Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2022-03-07 20:04:24 +01:00
Aravind Gopalakrishnan 16f2fbbc37 [9/n] L0 immediate commandlist improvements
Add HwInfo utility for more fine-grained flush task enablement
Related-To: LOCI-1988

Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@intel.com>
2022-02-18 19:51:28 +01:00
Aravind Gopalakrishnan 74cdd60255 [7/n] L0 immediate commandlist improvements
Enable flushTask only for specific families for now

Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@intel.com>
2022-02-15 18:43:30 +01:00
Maciej Plewka 9d8ce7aace Command container appends BB_END on cmd buffer allocation end
When linear stream created for command container has not enough space
for command and BB_END it will program BB_END and allocate new command
buffer allocation. Pointer returned from getSpace in this case will
return storage from new command buffer allocation.

Related-To: NEO-5707

Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2022-01-31 16:15:37 +01:00
Michal Mrozek 27c43b27f3 Remove not needed method.
Signed-off-by: Michal Mrozek <michal.mrozek@intel.com>
2022-01-20 15:02:19 +01:00
Mateusz Jablonski 5cd76aef6a Refactor surface state programming, add enum value for default halign value
Related-To: NEO-6466
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-01-19 14:31:28 +01:00
Mateusz Jablonski e5a18177c5 Add unit test helper function to set pipe control hdc flush
Separate unit test helper definitions bdw_and_later / xe_hp_and_later

Related-To: NEO-6466

Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-01-17 15:45:29 +01:00
Igor Venevtsev d9aae805c7 Do not apply L0 debugger WA (Disable L3 cache) for highest DG2 steppings
Related-To: NEO-6320

Signed-off-by: Igor Venevtsev <igor.venevtsev@intel.com>
2022-01-17 13:46:40 +01:00
Filip Hazubski 5be4d89b73 Rename function
Rename MemorySynchronizationCommands::isDcFlushAllowed
to MemorySynchronizationCommands::getDcFlushEnable

Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2021-12-30 17:03:22 +01:00
Maciej Plewka 615688336f Program all fields in SCM
Related-To: NEO-6432

This change applies WA that always programs all fields in SCM for
gen12lp. Also for those platforms Force Non-Coherent is set to 0x2.

Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2021-12-28 16:30:47 +01:00
Mateusz Jablonski 896e01c1cb Require exact revision when getting binary builtin for PVC
this change also implements logic for recompilation of builtin from spv in L0
in case when binary resource is not available


Related-To: NEO-6170
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2021-12-22 19:56:54 +01:00
Filip Hazubski f4c151cce5 Refactor PipeControlArgs struct
Remove struct PipeControlArgsBase

Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2021-12-22 17:13:16 +01:00
Filip Hazubski 0fd685541d Add isDcFlushAllowed function to HwInfoConfig
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2021-12-21 18:29:43 +01:00
Filip Hazubski 6d439f88bb Explicitly set dcFlushEnable value
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2021-12-21 12:21:11 +01:00
Igor Venevtsev fe250d99b1 Disable L3 caches for debug on ATS and DG2
Resolves: NEO-6320

Signed-off-by: Igor Venevtsev <igor.venevtsev@intel.com>
2021-12-14 13:59:09 +01:00
Milczarek, Slawomir b16438de56 Add regkey to override MOCS index in surface state for scratch space
Introduce the debug regkey OverrideMocsIndexForScratchSpace
to control MOCS index in surface state for scratch space

Related-To: NEO-6509

Signed-off-by: Milczarek, Slawomir <slawomir.milczarek@intel.com>
2021-12-07 16:27:33 +01:00
Bartosz Dunajski 2b1aa8b331 Compilation fix: Add missing LrcaHelper types
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2021-12-07 13:19:36 +01:00
Bartosz Dunajski 68aea5bf62 Rename compression flags and helpers
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2021-12-03 18:09:02 +01:00
Zbigniew Zdanowicz 3e1023fa1a Unify memory layout for all multi tile post sync operations
Related-To: NEO-6262

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-12-02 18:00:40 +01:00
Bartosz Dunajski 55959d4d1d Helper method to check if allocation is compressed
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2021-12-02 16:13:53 +01:00
Lukasz Jobczyk fb376639ee Refactor isDirectSubmissionSupported
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2021-11-25 13:40:41 +01:00
Zbigniew Zdanowicz 78609cd9f5 Optimize number of calls for pipe control post syncs
Related-To: NEO-6262

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-11-10 18:36:21 +01:00