Kamil Kopryk 004e6e647f fix: align indirect data pointer to cacheline size in heapless mode ... Align indirect data pointer to cacheline size in heapless mode, restore debug_break_if if avx2 load/store operation gets unaligned pointer, remove fallback to mm256 loadu/storeu unaligned operation Related-To: NEO-7621 Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>		2024-02-14 10:00:15 +01:00
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doc	feature: enable cl_cache by default on Windows	2023-10-03 16:57:10 +02:00
extensions	fix(ocl): add support for deprecated value of CL_MEM_DEVICE_ID_INTEL	2024-01-29 17:07:26 +01:00
source	fix: align indirect data pointer to cacheline size in heapless mode	2024-02-14 10:00:15 +01:00
test	fix: correctly report support for SPIR-V 1.0 through 1.3	2024-02-14 09:21:06 +01:00
CMakeLists.txt	feature: add experimental support for cl-gl sharing on Linux	2023-03-20 12:49:52 +01:00