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https://github.com/intel/intel-graphics-compiler.git
synced 2025-10-30 08:18:26 +08:00
Rematerialization pass now supports CMP instructions
Rematerialization pass now supports CMP instructions
This commit is contained in:
Sukhov, Egor
@ -408,7 +408,7 @@ bool CloneAddressArithmetic::rematerialize(RematSet &ToProcess, unsigned int Flo
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for (auto El : ToProcess) {
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PRINT_LOG("rematerialize: ");
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PRINT_INST(El);
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PRINT_INST_NL(El);
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Value *V = El;
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llvm::SmallVector<llvm::Use *, 8> VectorOfUses;
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@ -560,9 +560,14 @@ void CloneAddressArithmetic::collectInstToProcess(RematSet &ToProcess, Function
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bool IsLoad = llvm::isa<LoadInst>(I);
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bool IsStore = llvm::isa<StoreInst>(I);
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bool IsCall = llvm::isa<CallInst>(I);
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bool IsCmp = llvm::isa<CmpInst>(I);
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if (!IsLoad && !IsStore && !IsCall)
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if (!IsLoad && !IsStore && !IsCall && !IsCmp)
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continue;
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if (IsCmp && IGC_IS_FLAG_ENABLED(RematDataAllowCMP)) {
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ToProcess.insert(static_cast<Instruction *>(&I));
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continue;
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}
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llvm::Value *V =
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IsLoad ? static_cast<LoadInst *>(&I)->getPointerOperand() : static_cast<StoreInst *>(&I)->getPointerOperand();
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143
IGC/Compiler/tests/RematAddressArithmetic/cmp-remat.ll
Normal file
143
IGC/Compiler/tests/RematAddressArithmetic/cmp-remat.ll
Normal file
@ -0,0 +1,143 @@
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;=========================== begin_copyright_notice ============================
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;
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; Copyright (C) 2025 Intel Corporation
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;
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; SPDX-License-Identifier: MIT
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;
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;============================ end_copyright_notice =============================
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; REQUIRES: regkeys
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; RUN: igc_opt --typed-pointers %s -S -o - -igc-clone-address-arithmetic --regkey=RematFlowThreshold=20 --regkey=RematRPELimit=0 --dce | FileCheck %s
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; Function Attrs: convergent nounwind null_pointer_is_valid
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define spir_kernel void @widget(half addrspace(1)* align 2 %arg, half addrspace(1)* align 2 %arg1, half addrspace(1)* align 2 %arg2, float addrspace(1)* nocapture align 4 %arg3, i8 addrspace(1)* nocapture readonly align 1 %arg4, i32 addrspace(1)* nocapture readonly align 4 %arg5, i8 addrspace(1)* nocapture readonly align 1 %arg6, i32 addrspace(1)* nocapture readonly align 4 %arg7, half addrspace(1)* align 2 %arg8, <8 x i32> %arg9, i16 %arg10) #0 {
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bb:
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%tmp = extractelement <8 x i32> %arg9, i64 1
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%tmp11 = extractelement <8 x i32> %arg9, i64 6
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%tmp12 = icmp slt i32 %tmp11, 0
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%tmp14 = add i32 %tmp11, 127
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%spec.select = select i1 %tmp12, i32 %tmp14, i32 %tmp11
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%tmp17 = ashr i32 %spec.select, 7
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%tmp18 = shl i32 %tmp17, 7
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%tmp19 = sub i32 %tmp11, %tmp18
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%tmp20 = mul i32 %tmp17, 25165824
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%tmp21 = mul nsw i32 %tmp19, 196608
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%tmp22 = add i32 %tmp20, %tmp21
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%tmp23 = shl nsw i32 %tmp19, 17
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%tmp24 = sext i32 %tmp22 to i64
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%tmp25 = ptrtoint half addrspace(1)* %arg to i64
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%tmp26 = shl nsw i64 %tmp24, 1
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%tmp27 = add i64 %tmp26, %tmp25
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%tmp28 = sext i32 %tmp21 to i64
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%tmp29 = ptrtoint half addrspace(1)* %arg1 to i64
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%tmp30 = shl nsw i64 %tmp28, 1
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%tmp31 = add i64 %tmp30, %tmp29
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%tmp32 = sext i32 %tmp23 to i64
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%tmp33 = ptrtoint half addrspace(1)* %arg2 to i64
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%tmp34 = shl nsw i64 %tmp32, 1
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%tmp35 = add i64 %tmp34, %tmp33
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%tmp36 = shl i32 %tmp, 7
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%tmp37 = zext i16 %arg10 to i32
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%tmp38 = and i32 %tmp37, 112
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%tmp39 = or i32 %tmp38, %tmp36
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%tmp40 = or i32 %tmp39, 1
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%tmp41 = or i32 %tmp39, 2
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%tmp42 = or i32 %tmp39, 4
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%tmp43 = or i32 %tmp39, 5
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%tmp44 = or i32 %tmp39, 6
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%tmp45 = or i32 %tmp39, 7
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%tmp48 = and i64 %tmp27, -64
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call void @llvm.genx.GenISA.LSC2DBlockPrefetch.isVoid(i64 %tmp48, i32 0, i32 1023, i32 383, i32 0, i32 %tmp36, i32 16, i32 32, i32 32, i32 1, i1 false, i1 false, i32 4)
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%tmp51 = and i64 %tmp31, -64
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call void @llvm.genx.GenISA.LSC2DBlockPrefetch.isVoid(i64 %tmp51, i32 0, i32 1023, i32 383, i32 0, i32 0, i32 16, i32 32, i32 32, i32 1, i1 false, i1 false, i32 4)
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call void @llvm.genx.GenISA.LSC2DBlockPrefetch.isVoid(i64 %tmp51, i32 0, i32 1023, i32 383, i32 0, i32 32, i32 16, i32 32, i32 32, i32 1, i1 false, i1 false, i32 4)
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%tmp54 = and i64 %tmp35, -64
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call void @llvm.genx.GenISA.LSC2DBlockPrefetch.isVoid(i64 %tmp54, i32 255, i32 1023, i32 255, i32 0, i32 0, i32 16, i32 32, i32 32, i32 1, i1 false, i1 false, i32 4)
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br label %bb57
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bb57: ; preds = %bb57, %bb
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call void @llvm.genx.GenISA.LSC2DBlockSetAddrPayloadField.p0i32.i32(i32* null, i32 6, i32 0, i1 false)
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%tmp58 = call <8 x i32> @llvm.genx.GenISA.LSC2DBlockReadAddrPayload.v8i32.p0i32(i32* null, i32 0, i32 0, i32 32, i32 8, i32 16, i32 1, i1 true, i1 false, i32 0)
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%tmp59 = call <8 x i32> @llvm.genx.GenISA.LSC2DBlockReadAddrPayload.v8i32.p0i32(i32* null, i32 0, i32 0, i32 32, i32 8, i32 16, i32 1, i1 true, i1 false, i32 0)
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call void @llvm.genx.GenISA.LSC2DBlockSetAddrPayloadField.p0i32.i32(i32* null, i32 5, i32 0, i1 false)
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call void @llvm.genx.GenISA.LSC2DBlockSetAddrPayloadField.p0i32.i32(i32* null, i32 6, i32 0, i1 false)
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%tmp60 = call <8 x i32> @llvm.genx.GenISA.LSC2DBlockReadAddrPayload.v8i32.p0i32(i32* null, i32 0, i32 0, i32 32, i32 8, i32 16, i32 1, i1 true, i1 false, i32 0)
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%tmp61 = call <8 x i32> @llvm.genx.GenISA.LSC2DBlockReadAddrPayload.v8i32.p0i32(i32* null, i32 0, i32 0, i32 32, i32 8, i32 16, i32 1, i1 true, i1 false, i32 0)
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call void @llvm.genx.GenISA.LSC2DBlockSetAddrPayloadField.p0i32.i32(i32* null, i32 5, i32 0, i1 false)
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call void @llvm.genx.GenISA.LSC2DBlockSetAddrPayloadField.p0i32.i32(i32* null, i32 6, i32 0, i1 false)
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%tmp62 = call <8 x i32> @llvm.genx.GenISA.LSC2DBlockReadAddrPayload.v8i32.p0i32(i32* null, i32 0, i32 0, i32 32, i32 8, i32 16, i32 1, i1 true, i1 false, i32 0)
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%tmp63 = call <8 x i32> @llvm.genx.GenISA.LSC2DBlockReadAddrPayload.v8i32.p0i32(i32* null, i32 0, i32 0, i32 32, i32 8, i32 16, i32 1, i1 true, i1 false, i32 0)
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call void @llvm.genx.GenISA.LSC2DBlockSetAddrPayloadField.p0i32.i32(i32* null, i32 5, i32 0, i1 false)
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%tmp84 = icmp slt i32 %tmp40, 0
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%tmp85 = icmp slt i32 %tmp41, 0
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%tmp87 = icmp slt i32 %tmp42, 0
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%tmp88 = icmp slt i32 %tmp43, 0
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%tmp89 = icmp slt i32 %tmp44, 0
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%tmp90 = icmp slt i32 %tmp45, 0
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; CHECK: [[REMAT_1:%remat.*]] = or i32 %tmp39, 1
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; CHECK: [[CLONED_1:%cloned_.*]] = icmp slt i32 [[REMAT_1]]
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; CHECK: = select i1 [[CLONED_1]]
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; CHECK: [[REMAT_2:%remat.*]] = or i32 %tmp39, 2
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; CHECK: [[CLONED_2:%cloned_.*]] = icmp slt i32 [[REMAT_2]]
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; CHECK: = select i1 [[CLONED_2]]
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%tmp95 = select i1 %tmp84, float 0xFFF0000000000000, float 0.000000e+00
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%tmp96 = select i1 %tmp85, float 0xFFF0000000000000, float 0.000000e+00
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%tmp98 = select i1 %tmp87, float 0xFFF0000000000000, float 0.000000e+00
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%tmp99 = select i1 %tmp88, float 0xFFF0000000000000, float 0.000000e+00
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%tmp100 = select i1 %tmp89, float 0xFFF0000000000000, float 0.000000e+00
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%tmp101 = select i1 %tmp90, float 0xFFF0000000000000, float 0.000000e+00
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%tmp103 = insertelement <8 x float> <float 0.000000e+00, float undef, float undef, float undef, float undef, float undef, float undef, float undef>, float %tmp95, i64 1
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%tmp104 = insertelement <8 x float> %tmp103, float %tmp96, i64 2
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%tmp105 = insertelement <8 x float> %tmp104, float 0.000000e+00, i64 3
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%tmp106 = insertelement <8 x float> %tmp105, float %tmp98, i64 4
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%tmp107 = insertelement <8 x float> %tmp106, float %tmp99, i64 5
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%tmp108 = insertelement <8 x float> %tmp107, float %tmp100, i64 6
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%tmp109 = insertelement <8 x float> %tmp108, float %tmp101, i64 7
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%tmp110 = call <8 x float> @llvm.maxnum.v8f32(<8 x float> zeroinitializer, <8 x float> %tmp109)
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%tmp111 = extractelement <8 x float> %tmp110, i64 0
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%tmp118 = call float @llvm.genx.GenISA.WaveAll.f32(float %tmp111, i8 12, i32 0)
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br label %bb57
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}
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; Function Attrs: convergent inaccessiblememonly nounwind
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declare float @llvm.genx.GenISA.WaveAll.f32(float, i8, i32) #1
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; Function Attrs: convergent nounwind readnone willreturn
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declare <8 x float> @llvm.genx.GenISA.sub.group.dpas.v8f32.v8f32.v8i16.v8i32(<8 x float>, <8 x i16>, <8 x i32>, i32, i32, i32, i32, i1) #2
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; Function Attrs: nounwind
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declare void @llvm.genx.GenISA.LSC2DBlockPrefetch.isVoid(i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i1, i1, i32) #3
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; Function Attrs: nocallback nofree nosync nounwind readnone speculatable willreturn
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declare i32 @llvm.umin.i32(i32, i32) #4
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; Function Attrs: nounwind readnone speculatable willreturn
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declare i32* @llvm.genx.GenISA.LSC2DBlockCreateAddrPayload.p0i32(i64, i32, i32, i32, i32, i32, i32, i32, i32) #5
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; Function Attrs: argmemonly nounwind speculatable willreturn writeonly
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declare void @llvm.genx.GenISA.LSC2DBlockSetAddrPayloadField.p0i32.i32(i32*, i32, i32, i1) #6
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; Function Attrs: nounwind willreturn
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declare <8 x i32> @llvm.genx.GenISA.LSC2DBlockReadAddrPayload.v8i32.p0i32(i32*, i32, i32, i32, i32, i32, i32, i1, i1, i32) #7
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; Function Attrs: nounwind willreturn
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declare <32 x i32> @llvm.genx.GenISA.LSC2DBlockReadAddrPayload.v32i32.p0i32(i32*, i32, i32, i32, i32, i32, i32, i1, i1, i32) #7
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; Function Attrs: nounwind willreturn
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declare <32 x i16> @llvm.genx.GenISA.LSC2DBlockReadAddrPayload.v32i16.p0i32(i32*, i32, i32, i32, i32, i32, i32, i1, i1, i32) #7
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; Function Attrs: nocallback nofree nosync nounwind readnone speculatable willreturn
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declare <8 x float> @llvm.maxnum.v8f32(<8 x float>, <8 x float>) #4
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attributes #0 = { convergent nounwind null_pointer_is_valid }
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attributes #1 = { convergent inaccessiblememonly nounwind }
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attributes #2 = { convergent nounwind readnone willreturn }
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attributes #3 = { nounwind }
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attributes #4 = { nocallback nofree nosync nounwind readnone speculatable willreturn }
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attributes #5 = { nounwind readnone speculatable willreturn }
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attributes #6 = { argmemonly nounwind speculatable willreturn writeonly }
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attributes #7 = { nounwind willreturn }
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!igc.functions = !{}
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@ -1545,6 +1545,7 @@ DECLARE_IGC_REGKEY(
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"Confine rematerialization only to variables within the same BB, we won't pull down values from predeccors", false)
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DECLARE_IGC_REGKEY(bool, RematRespectUniformity, false, "Cutoff computation chain on uniform values", false)
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DECLARE_IGC_REGKEY(bool, RematAllowExtractElement, true, "Allow Extract Element to computation chain", false)
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DECLARE_IGC_REGKEY(bool, RematDataAllowCMP, true, "Allow rematerialization of cmp instructions", true)
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DECLARE_IGC_REGKEY(bool, RematReassocBefore, false,
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"Enable short sequence of passes before clone address arithmetic pass to potentially decrese amount "
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"of operations that will be rematerialized",
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