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https://github.com/intel/intel-graphics-compiler.git
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Avoid increasing grf pressure
Vector Aliasing will increase grf pressure. This change is to limit scalar to vector aliasing to avoid increasing register pressure.
This commit is contained in:
@ -19,6 +19,7 @@ SPDX-License-Identifier: MIT
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using namespace llvm;
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using namespace IGC;
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using namespace IGC::IGCMD;
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namespace
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{
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@ -98,6 +99,7 @@ char VariableReuseAnalysis::ID = 0;
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IGC_INITIALIZE_PASS_BEGIN(VariableReuseAnalysis, "VariableReuseAnalysis",
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"VariableReuseAnalysis", false, true)
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// IGC_INITIALIZE_PASS_DEPENDENCY(RegisterEstimator)
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IGC_INITIALIZE_PASS_DEPENDENCY(MetaDataUtilsWrapper)
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IGC_INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
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IGC_INITIALIZE_PASS_DEPENDENCY(WIAnalysis)
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IGC_INITIALIZE_PASS_DEPENDENCY(LiveVarsAnalysis)
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@ -1096,55 +1098,60 @@ void VariableReuseAnalysis::InsertElementAliasing(Function* F)
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// VectorAlias=0x1: subvec aliasing for isolated values (getRootValue()=null)
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// =0x2: subvec aliasing for both isolated and non-isolated value)
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const auto control = (m_pCtx->getVectorCoalescingControl() & 0x3);
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// To avoid increasing GRF pressure, skip if F is too large.
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// To avoid increasing GRF pressure, skip if F is too large or not an entry
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const uint32_t NumBBThreshold = (int)IGC_GET_FLAG_VALUE(VectorAliasBBThreshold);
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if (control == 0 || F->size() > NumBBThreshold) {
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MetaDataUtils* pMdUtils = getAnalysis<MetaDataUtilsWrapper>().getMetaDataUtils();
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if (control == 0 || !isEntryFunc(pMdUtils, F) || F->size() > NumBBThreshold) {
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return;
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}
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for (auto II = inst_begin(F), IE = inst_end(F); II != IE; ++II)
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for (auto BI = F->begin(), BE = F->end(); BI != BE; ++BI)
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{
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Instruction* I = &*II;
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if (!m_PatternMatch->NeedInstruction(*I))
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continue;
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BasicBlock* BB = &*BI;
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setSkipScalarAliaser(BB);
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for (auto II = BB->begin(), IE = BB->end(); II != IE; ++II)
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{
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Instruction* I = &*II;
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if (!m_PatternMatch->NeedInstruction(*I))
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continue;
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InsertElementInst* IEI = dyn_cast<InsertElementInst>(I);
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if (!IEI)
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continue;
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InsertElementInst* IEI = dyn_cast<InsertElementInst>(I);
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if (!IEI)
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continue;
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// Two cases for sub-vector aliasing:
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// 1. extractFrom: sub-vector is created from a base vector.
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// For example:
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// given base: int8 b; a sub-vector s (int4) can be:
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// s = (int4)(b.s4, b.s5, b.s6, b.s7)
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// In this case, 's' becomes a part of 'b'. In LLVM IR,
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// there are a chain of extElt and insElt instructions for
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// doing so.
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// 2. insertTo: sub-vector is used to create a base vector.
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// For example:
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// given sub-vector int4 s0, s1; int8 vector b is created like:
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// b = (int8) (s0, s1)
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// In this case, both s0 and s1 become part of b.
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// Two cases for sub-vector aliasing:
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// 1. extractFrom: sub-vector is created from a base vector.
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// For example:
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// given base: int8 b; a sub-vector s (int4) can be:
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// s = (int4)(b.s4, b.s5, b.s6, b.s7)
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// In this case, 's' becomes a part of 'b'. In LLVM IR,
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// there are a chain of extElt and insElt instructions for
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// doing so.
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// 2. insertTo: sub-vector is used to create a base vector.
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// For example:
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// given sub-vector int4 s0, s1; int8 vector b is created like:
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// b = (int8) (s0, s1)
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// In this case, both s0 and s1 become part of b.
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// Start insertElement pattern from the first InsertElement (one
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// with UndefValue. Note that this's also the dessa insElt root.
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if (!isa<UndefValue>(IEI->getOperand(0)))
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continue;
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// Start insertElement pattern from the first InsertElement (one
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// with UndefValue. Note that this's also the dessa insElt root.
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if (!isa<UndefValue>(IEI->getOperand(0)))
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continue;
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// First, collect all insertElementInst and extractElementInst.
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VecInsEltInfoTy AllIEIs;
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if (!getAllInsEltsIfAvailable(IEI, AllIEIs)) {
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continue;
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}
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// First, collect all insertElementInst and extractElementInst.
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VecInsEltInfoTy AllIEIs;
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if (!getAllInsEltsIfAvailable(IEI, AllIEIs)) {
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continue;
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}
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// Check if this is an extractFrom pattern, if so, add alias.
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if (processExtractFrom(AllIEIs)) {
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continue;
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}
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// Check if this is an extractFrom pattern, if so, add alias.
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if (processExtractFrom(AllIEIs)) {
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continue;
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}
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// Check if this is an insertTo pattern, if so add alias.
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if (processInsertTo(AllIEIs)) {
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continue;
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// Check if this is an insertTo pattern, if so add alias.
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if (processInsertTo(AllIEIs)) {
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continue;
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}
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}
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}
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}
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@ -1294,6 +1301,10 @@ bool VariableReuseAnalysis::processInsertTo(VecInsEltInfoTy& AllIEIs)
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(Sub && (i - SubStartIx) != AllIEIs[i].FromVec_eltIx)) {
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isSubCandidate = false;
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}
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if (Elt && Sub == nullptr && isSkipScalarAliaser()) {
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// Skip scalar coalescing
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isSubCandidate = false;
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}
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// If Sub == nullptr or NextSub != Sub, this is the last element
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// of the current Sub (it is a scalar in case of sub == nullpr).
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@ -1561,3 +1572,11 @@ bool VariableReuseAnalysis::checkSubAlign (e_alignment& BaseAlign,
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BaseAlign = sub_align;
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return true;
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}
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void VariableReuseAnalysis::setSkipScalarAliaser(llvm::BasicBlock* BB)
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{
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if (BB->size() > 500)
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m_skipScalarAliaser = true;
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else
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m_skipScalarAliaser = false;
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}
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@ -13,6 +13,7 @@ SPDX-License-Identifier: MIT
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#include "Compiler/CISACodeGen/CoalescingEngine.hpp"
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#include "Compiler/CISACodeGen/BlockCoalescing.hpp"
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#include "common/LLVMWarningsPush.hpp"
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#include "Compiler/MetaDataUtilsWrapper.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/IR/Dominators.h"
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#include "llvm/ADT/TinyPtrVector.h"
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@ -193,6 +194,7 @@ namespace IGC {
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virtual void getAnalysisUsage(llvm::AnalysisUsage& AU) const override {
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// AU.addRequired<RegisterEstimator>();
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AU.setPreservesAll();
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AU.addRequired<MetaDataUtilsWrapper>();
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AU.addRequired<llvm::DominatorTreeWrapperPass>();
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AU.addRequired<WIAnalysis>();
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AU.addRequired<LiveVarsAnalysis>();
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@ -493,6 +495,11 @@ namespace IGC {
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// <V's root, V> into the map. This is a quick check to see if any
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// value in a dessa CC has been aliased (either aliaser or aliasee)
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Val2ValMapTy m_root2AliasMap;
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// For vector aliasing heuristic to prevent possible high-reg pressure
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bool m_skipScalarAliaser;
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void setSkipScalarAliaser(llvm::BasicBlock* BB);
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bool isSkipScalarAliaser() const { return m_skipScalarAliaser; }
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};
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llvm::FunctionPass* createVariableReuseAnalysisPass();
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