Commit Graph

18639 Commits

Author SHA1 Message Date
0547781257 Add require_assert_buffer and require_sync_buffer to zeinfo
Add require_assert_buffer and require_sync_buffer to zeinfo
2025-10-28 11:25:40 +01:00
f59fbf1a03 Unify regkey for simd16 drop for XE2 and XE3
Simplify logic by using common key, instead having seperate keys.
2025-10-28 11:15:42 +01:00
326333aec2 Minor refactor
Minor refactor
2025-10-28 10:24:16 +01:00
a575afde7b Fix a crash in EmitVISAPass
Fix a crash where we look for a previous instruction but it's not there, resulting in dyn_casting a nullptr.
2025-10-27 22:02:02 +01:00
5f4fc0e861 Disable build plugin for compilation without tests
.
2025-10-27 19:56:31 +01:00
6230f5290f Remat threshold increase
This change is to allow for bigger early rematerialization to avoid redundant spills.
2025-10-27 16:53:20 +01:00
ef5a973738 Enable more aggresive trimming for very large kernels
Enable trimming of small functions, in case kernel far exceedes
threshold even after default trimming is performed, to keep compilation
time in check.
2025-10-27 16:46:06 +01:00
66e66680f7 Fix problem in split barrier
Fixed the problem in split barrier when we are using with regular barrier.
Case:
splitbarrier.signal()
regularbarrier()
splitbarrier.wait()

was causing the hang due assigning the same ID of the barrier in the regular barrier and split barrier.
Now, the split barrier will take other ID than the regular one.
2025-10-27 12:54:22 +01:00
d7a41cf31b Rewrite TargetExtTy retyper using ValueMapTypeRemapper
This change rewrites the TargetExtTy retyper to use the
ValueMapTypeRemapper infrastructure, significantly improving the overall
design and maintainability of the code. The change also removes unused
cases added for additional safety if earlier retyping logic fails.

Two additional test cases are added, covering more complex retyping
scenarios.
2025-10-27 10:32:46 +01:00
ba8538b4e6 Skip split on spill if variable is not live-in/live-out
Split on spill pass splits live-interval of variables that are
live-in/live-out of a loop and are used inside the loop. Splitting such
a spilled variable reduces RA constraints on the split variable, making
it possible to allocate a register for that variable in the loop.

This split must be done only when the variable is live-in to the loop or
live-out of the loop and is defined in the loop. Latter condition is
because in case a variable is written in the loop, it's also spilled to
home location at loop exit.
2025-10-27 07:19:30 +01:00
1a180031e5 Changes in code. 2025-10-27 05:25:19 +01:00
5d482f7901 Disable badasm VC lit
.
2025-10-24 22:52:09 +02:00
945b3f6733 Sampler opaque ptr readiness
This change is part of the effort to support opaque pointers in next
llvm versions.
2025-10-24 17:09:00 +02:00
ecf98ed502 Refresh build scripts
Removed Ubuntu 20.04 support from build scripts.
Updated `add-apt-repository` section to current versions.
Unified buildSLT.sh to versions in buildIGC.sh.
2025-10-24 15:22:58 +02:00
06dfb54d9b Bump MINOR to 23 2025-10-24 14:51:30 +02:00
9bb52b0625 Revert "Remove usages of legacy SPIR-V Translator macros pt. 4"
Revert Revert "Remove usages of legacy SPIR-V Translator macros pt. 4"
2025-10-24 12:30:28 +02:00
fd46428741 Switch builds to LLVM 16 and update docs
Switch builds to use LLVM 16. Updated the documentation to treat LLVM 16 as default.
Refreshed parts of buildIGC.sh regarding supported versions. Fixed a bug when setting a variable in buildIGC.sh to a default value.

Force enabled exceptions for VC. This is a workaround while we're investigating why they're disabled.
2025-10-24 12:25:56 +02:00
d8e9c579df Revert: Bump MINOR to 23 2025-10-24 11:47:53 +02:00
53a472d310 optimize i64 built-in variables to i32
OpenCL represents built-in variables like `get_global_id` with generic
type `size_t`, which translates to i64. This change adds a new
optimization that simplifies built-in calculation to i32 if built-in's
use has an assumption hinting that value fits in i32 range.
2025-10-24 11:31:59 +02:00
61ac4bc1bd Fix a bug for scheduling for dpas block
The original logic may failed if two macro are build in adjacent
scheduling, the candidate instruction may depends on first block but not
second block. As a result, it cannot be added into second block.
2025-10-24 03:36:42 +02:00
b89fdf0758 Add corner case to HWConformity check
Additional checks for src alignment if dst spans more than 2GRF.
2025-10-23 21:29:58 +02:00
3287945f37 IGA: code cleanup for DpasMacroBuilder (NFC)
Removed unused code.
2025-10-23 18:26:57 +02:00
bf462ba158 Bump MINOR to 23 2025-10-23 16:27:15 +02:00
58e48ef812 Reformat SPV_INTEL_subgroup_matrix_multiply_accumulate enum
Reformat SPV_INTEL_subgroup_matrix_multiply_accumulate enum values
for easier comparison with the spec.
2025-10-23 16:10:01 +02:00
b6199548fd Changes in code. 2025-10-23 15:59:29 +02:00
2e97ce64cd Replace single iteration for loop.
Replace a for loop that only executes once with dereferencing of the
iterator returned by `begin()`.
2025-10-23 14:07:52 +02:00
5689ca664f Update IGC flag documentation.
Update IGC flag documentation.
2025-10-23 12:02:15 +02:00
e11d76fe72 Remove usages of legacy SPIR-V Translator macros pt. 4
Remove usages of legacy SPIRV Translator macros such as `SPIRV_BUILTIN`,
`SPIRV_BUILTIN_NOOP` and `SPIRV_OCL_BUILTIN`.
2025-10-23 11:59:01 +02:00
7308ad7501 handle bitcasted opaque ptrs instead of skipping them in SOALayoutChecker
When the `SOALayoutChecker::visitBitCastInst()` encountered a ptr bitcast
on opaque pointers, we just used to skip it. With this change, we checks users of
the bitcast, like it's done on typed pointers (just without ptr
type checks).

Such bitcasted ptr `%p` would be skipped without properly handling it.
```llvm
%arr = alloca [32 x float], align 4
%p = bitcast ptr %arr to ptr
```

---------------------------
2025-10-23 09:49:10 +02:00
6da778b285 Implement fine control over CloneAddressArithmetic pass
Implement fine control over CloneAddressArithmetic pass
2025-10-23 04:37:14 +02:00
7562ebc444 Enable simd16_dual8 alongside simd16
Enable simd16_dual8 alongside simd16
2025-10-23 04:22:03 +02:00
91aa64c9fd Avoid fencing BTD/TraceRayAsync calls if there are no stores prior to them.
By default, we always insert LSC fence before send.btd / send.rta calls, but it isn't necessary.
2025-10-22 23:33:35 +02:00
28b02a938e [NFC] nit on cmake comment
IST is not IGCStandalone
2025-10-22 21:37:00 +02:00
2daa009f99 [Autobackout][FunctionalRegression]Revert of change: 857fb62d05: Fix problem in split barrier
Fixed the problem in split barrier when we are using with regular barrier.
    Case:
    splitbarrier.signal()
    regularbarrier()
    splitbarrier.wait()

    was causing the hang due assigning the same ID of the barrier in the regular barrier and split barrier.
    Now, the split barrier will take other ID than the regular one.
2025-10-22 18:04:02 +02:00
0120924892 Adding hasVLA attribute
If a function contains dynamic alloca
then ModuleAllocaAnalysis pass adds 'hasVLA' attribute.
2025-10-22 18:00:29 +02:00
a9cd884f4c Emit error for functions exceeding hardware scratch space limits
Emit a compilation error when non-kernel functions exceed the hardware-supported
scratch space limit instead of silently dropping the kernel from the final
binary. This issue was observed on O0 compilation path.
2025-10-22 12:51:28 +02:00
db7015317a ADD, MUL, SUB i32 instructions added to IGCVectorizer
ADD, MUL, SUB i32 instructions added to IGCVectorizer
2025-10-22 11:53:09 +02:00
89c7117387 Prevent fast math flag propagation to __spirv_ocl_native_exp builtin implementation
This is a follow-up after 5f3b2b4c5a.
`__spirv_ocl_native_exp` has the same issue as `__spirv_ocl_exp`
2025-10-22 10:56:29 +02:00
94f2cb27d9 Fix OCL atomic benchmark regression
More investigation is needed. Currently, we don't apply atomic_iadd to
atomic_inc/dec optimization to OCL cases.
2025-10-21 21:16:48 +02:00
f8934ec463 Minor indent fix
Minor indent fix
2025-10-21 20:13:12 +02:00
bc27ff2baa Fix the bug in the destination register alignment checking
for pre-RA ACC sub

If the register is pre assgined, it's not a candidate.
2025-10-21 19:01:10 +02:00
c982af7201 GenXVectorDecomposer: Fix iterative dead code elimination
Fixes vector decomposition correctness issues where some phi
parts were being eliminated despite being necessary for proper
vector reconstruction.
2025-10-21 17:06:28 +02:00
59e367e548 Update spill threshold logic 2025-10-21 16:51:17 +02:00
857fb62d05 Fix problem in split barrier
Fixed the problem in split barrier when we are using with regular barrier.
Case:
splitbarrier.signal()
regularbarrier()
splitbarrier.wait()

was causing the hang due assigning the same ID of the barrier in the regular barrier and split barrier.
Now, the split barrier will take other ID than the regular one.
2025-10-21 15:59:22 +02:00
2a53b762fa Turn 2 asserts into warnings - try 2
Turn NumDebugCUs == 1 and llvm.dbg.declare count asserts into warnings
2025-10-21 15:57:53 +02:00
68eb7029ba Fix CodeScheduling in case of DPAS in different BB
- Fix CodeScheduling incorrect behavior in case of DPAS and load are in
different BBs
- Fix RematChainsAnalysis incorrect behavior in some cases with selects
2025-10-21 15:55:39 +02:00
2a0dedc2ba Rematerialize runtime_value intrinsics
This change is to rematerialize `runtime_value` instructions.
2025-10-21 15:51:46 +02:00
849ca205c0 Remove legacy SPIRV Translator macros usages pt. 2
Remove usages of legacy SPIRV Translator macros from ```IGC/BiFModule/Implementation/IMF/FP32```
2025-10-21 15:47:45 +02:00
aa69cad230 Remove legacy SPIRV Translator macros usages pt. 3
Remove usages of legacy SPIRV Translator macros from ```IGC/BiFModule/Implementation/IMF/FP64```
2025-10-21 15:42:47 +02:00
61b9e70ce2 Remove legacy SPIRV Translator macros pt. 1
Remove usages of legacy SPIRV Translator macros from ```IGC/BiFModule/Languages/```
2025-10-21 10:41:02 +02:00