Similar to e92b153e99 ("mediatek: introduce KERNEL_LOADADDR to Device/Default template"),
let's move the default loadaddr to Device/Default.
What's more, use 0x80200000 instead of the SDK default value 0x80088000
to avoid the following error which may overwrite TZ memory and cause crash:
[ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
[ 0.000000] OF: reserved mem: Reserved memory: failed to reserve memory for node 'atf@80000000': base 0x0000000080000000, size 2 MiB
Signed-off-by: Ziyang Huang <hzyitc@outlook.com>
[ fix spelling mistake ]
Link: https://github.com/openwrt/openwrt/pull/20470
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
This reverts commit 096739a93d.
The new fortify-headers version needs some more work to be usable in
OpenWrt. Revert this to fix the builds again.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This reverts commit 6268692bd2.
The new fortify-headers version needs some more work to be usable in
OpenWrt. Revert this to fix the builds again.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This reverts commit 61f16a6960.
The new fortify-headers version needs some more work to be usable in
OpenWrt. Revert this to fix the builds again.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Enable USB node on eMMC RFB board and disable USB2 3.0 port to make the
3rd PCIe line correctly work.
This is needed to prevent the xHCI driver to mess with PCIe by
configuring the USB2 3.0 port. Port will still be detected but won't be
configureed by the driver and won't have PHY to configure for.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The 3rd PCIe line use the USB2 serdes for PCIe operation. Correctly set
it to the DT node so that the mode can be correctly set in the PHY
driver.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Add pending patch for USB support on AN7581 SoC. This is also required
to make operational the 3rd PCIe line that use the USB2 Serdes for PCIe
operations.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Remove SerDes initialization/configuration calls from the DSA driver in
'rtl93xx_phylink_mac_config' and let our PCS driver setup the SerDes now
that the driver is able to do that.
Adjust some details in rtl93xx_phylink_mac_config to ensure the MAC is
properly disabled MAC before configuring the SerDes. This was done
within the SerDes code before.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20539
Signed-off-by: Robert Marko <robimarko@gmail.com>
This fixes the sysupgrade image generation for the LBR20 as before
updating resulted in a brick which needed to be recovered using
nmrpflash.
UART log of a bricked unit:
Loading DNI firmware for checking...
Loading firmware 1 ...
NAND read: device 0 offset 0xa600000, size 0x20000
131072 bytes read: OK
NAND read: device 0 offset 0xa600000, size 0x380000
3670016 bytes read: OK
rootfs imge header corrupted !
Loading firmware 2 ...
NAND read: device 0 offset 0xa600000, size 0x20000
131072 bytes read: OK
NAND read: device 0 offset 0xa600000, size 0x380000
3670016 bytes read: OK
rootfs imge header corrupted !
Comparing the partition contents of a bricked and a working unit showed
that on the bricked one the fake uImage header was missing. The UBI
partition also showed significant changes. Both are fixed when the
base DniImage receipt is used.
Signed-off-by: Christoph Krapp <achterin@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20558
Signed-off-by: Robert Marko <robimarko@gmail.com>
This aligns the LED behaviour with other Orbi devices. Orbi devices have
multiple RBG LEDs at the top of the device and two status LEDs at the
back next to the barrel jack.
The current behaviour of other Orbi devices is to use the multi-color
LEDs at the top for status indication and the green/red LEDs at the back
for running/panic-indication. This matches the vendor behaviour except
the color choice.
Other devices use green as running, blue on upgrade, red on failsafe and
white on bootup, so this aligns the LBR20 behaviour to the rest.
Signed-off-by: Christoph Krapp <achterin@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20558
Signed-off-by: Robert Marko <robimarko@gmail.com>
Some SoC might use the Serdes for the second USB port as a 3rd PCIe
line (with the SSTR register correctly setup).
Add the node for the 3rd PCIe card and enable for the eMMC RFB board.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Fix some warnings and compile errors generated by the new
fortify-headers when compiling some applications like strace.
Fixes: 6268692bd2 ("toolchain: fortify-headers: Update to version 2.3.3")
Link: https://github.com/openwrt/openwrt/pull/20561
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Update to recent fortify-headers version. This version also supports
_FORTIFY_SOURCE=3.
Changes: https://github.com/jvoisin/fortify-headers/compare/1.1...2.3.3
A patch similar to the removed one was applied upstream:
b40f6d8748
The root file system is getting a bit bigger.
Without this commit:
5250380 bin/targets/armsr/armv8/openwrt-armsr-armv8-generic-rootfs.tar.gz
4919997 bin/targets/malta/be/openwrt-malta-be-default-rootfs.tar.gz
With this commit:
5263407 bin/targets/armsr/armv8/openwrt-armsr-armv8-generic-rootfs.tar.gz
4930011 bin/targets/malta/be/openwrt-malta-be-default-rootfs.tar.gz
Link: https://github.com/openwrt/openwrt/pull/20313
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Fixes the following error by backporting upstream update:
```
scripts/dtc/pylibfdt/libfdt_wrap.c: In function ‘_wrap_fdt_next_node’:
scripts/dtc/pylibfdt/libfdt_wrap.c:5581:17: error: too few arguments to function ‘SWIG_Python_AppendOutput’
5581 | resultobj = SWIG_Python_AppendOutput(resultobj, val);
| ^~~~~~~~~~~~~~~~~~~~~~~~
```
This is the same fix as applied in 4e68103c4e ("uboot-rockchip: fix build with swig 4.3.0")
Link: https://github.com/openwrt/openwrt/pull/20538
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Backport a patch fixing a kernel panic on airoha_hw_init fail. This
should better handle scenario with NPU load Probe deferring.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Backport cleanup patch for Airoha Ethernet patch to permit easier
backport in the future.
Automatically refresh all affected patch.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Add pending patch to make address some workaround needed to make the
Aeonsemi AS21xxx PHY working on the Airoha AN7581/AN7583 board.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Airoha AN7581 eMMC RFB board mount 2 Aeonsemi AS21xxx PHY. One is
usually connected to GDM4 and the other is optionally connected to GDM2.
Add the relevant nodes to support the one connected to GDM4.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Pack the BL2 and BL31+U-Boot artifacts as Airoha AN7581 is currently
supported in upstream U-Boot and bootloader files can be used for
unfused boards.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
As mkits.sh only generates the relevant DTS for mkimage and is
specific for the building image, we can move it outside the locked
section as it doesn't do any operation that can be used concurrently by
others.
This won't have any real impact but clean the code making it clear what
needs to be protected and what can be executed concurrently.
Link: https://github.com/openwrt/openwrt/pull/20492
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
