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airoha: add nodes for 3rd PCIe line for AN7581

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Some SoC might use the Serdes for the second USB port as a 3rd PCIe
line (with the SSTR register correctly setup).

Add the node for the 3rd PCIe card and enable for the eMMC RFB board.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
This commit is contained in:
Christian Marangi
2025-10-27 11:08:46 +01:00
parent 3696241d3a
commit 2fae199953
2 changed files with 56 additions and 0 deletions
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13
target/linux/airoha/dts/an7581-evb-emmc.dts
View File

@ -57,6 +57,13 @@
};
};
pcie2_rst_pins: pcie2-rst-pins {
conf {
pins = "pcie_reset2";
drive-open-drain = <1>;
};
};
gswp1_led0_pins: gswp1-led0-pins {
mux {
function = "phy1_led0";
@ -156,6 +163,12 @@
status = "okay";
};
&pcie2 {
pinctrl-names = "default";
pinctrl-0 = <&pcie2_rst_pins>;
status = "okay";
};
&mdio {
as21xx_1: ethernet-phy@1d {
compatible = "ethernet-phy-ieee802.3-c45";

43
target/linux/airoha/dts/an7581.dtsi
View File

@ -718,6 +718,49 @@
};
};
pcie2: pcie@1fc40000 {
compatible = "airoha,en7581-pcie";
device_type = "pci";
linux,pci-domain = <2>;
#address-cells = <3>;
#size-cells = <2>;
reg = <0x0 0x1fc40000 0x0 0x1670>;
reg-names = "pcie-mac";
clocks = <&scuclk EN7523_CLK_PCIE>;
clock-names = "sys-ck";
phys = <&pciephy>;
phy-names = "pcie-phy";
ranges = <0x02000000 0 0x28000000 0x0 0x28000000 0 0x4000000>;
resets = <&scuclk EN7581_PCIE0_RST>,
<&scuclk EN7581_PCIE1_RST>,
<&scuclk EN7581_PCIE2_RST>;
reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
mediatek,pbus-csr = <&pbus_csr 0x10 0x14>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc2 0>,
<0 0 0 2 &pcie_intc2 1>,
<0 0 0 3 &pcie_intc2 2>,
<0 0 0 4 &pcie_intc2 3>;
status = "disabled";
pcie_intc2: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
npu: npu@1e900000 {
compatible = "airoha,en7581-npu";
reg = <0x0 0x1e900000 0x0 0x313000>;