kernel: mtd: add support for spi-nor 4B opcode
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@ -18,19 +18,12 @@
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#define SPINOR_OP_RDVCR 0x85
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/* JEDEC Standard - Serial Flash Discoverable Parmeters (SFDP) Commands */
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#define SPINOR_OP_READ_1_2_2 0xbb /* DUAL I/O READ */
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#define SPINOR_OP_READ_1_4_4 0xeb /* QUAD I/O READ */
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#define SPINOR_OP_WRITE 0x02 /* PAGE PROGRAM */
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#define SPINOR_OP_WRITE_1_1_2 0xa2 /* DUAL INPUT PROGRAM */
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#define SPINOR_OP_WRITE_1_2_2 0xd2 /* DUAL INPUT EXT PROGRAM */
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#define SPINOR_OP_WRITE_1_1_4 0x32 /* QUAD INPUT PROGRAM */
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#define SPINOR_OP_WRITE_1_4_4 0x12 /* QUAD INPUT EXT PROGRAM */
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/* READ commands with 32-bit addressing */
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#define SPINOR_OP_READ4_1_2_2 0xbc
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#define SPINOR_OP_READ4_1_4_4 0xec
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/* Configuration flags */
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#define FLASH_FLAG_SINGLE 0x000000ff
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#define FLASH_FLAG_READ_WRITE 0x00000001
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@ -507,12 +507,12 @@ static struct seq_rw_config n25q_read3_configs[] = {
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* - 'FAST' variants configured for 8 dummy cycles (see note above.)
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*/
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static struct seq_rw_config n25q_read4_configs[] = {
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{FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ4_1_4_4, 0, 4, 4, 0x00, 0, 8},
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{FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8},
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{FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ4_1_2_2, 0, 2, 2, 0x00, 0, 8},
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{FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8},
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{FLASH_FLAG_READ_FAST, SPINOR_OP_READ4_FAST, 0, 1, 1, 0x00, 0, 8},
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{FLASH_FLAG_READ_WRITE, SPINOR_OP_READ4, 0, 1, 1, 0x00, 0, 0},
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{FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B, 0, 4, 4, 0x00, 0, 8},
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{FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B, 0, 1, 4, 0x00, 0, 8},
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{FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B, 0, 2, 2, 0x00, 0, 8},
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{FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B, 0, 1, 2, 0x00, 0, 8},
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{FLASH_FLAG_READ_FAST, SPINOR_OP_READ_FAST_4B, 0, 1, 1, 0x00, 0, 8},
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{FLASH_FLAG_READ_WRITE, SPINOR_OP_READ_4B, 0, 1, 1, 0x00, 0, 0},
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{0x00, 0, 0, 0, 0, 0x00, 0, 0},
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};
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@ -553,12 +553,12 @@ static int stfsm_mx25_en_32bit_addr_seq(struct stfsm_seq *seq)
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* entering a state that is incompatible with the SPIBoot Controller.
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*/
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static struct seq_rw_config stfsm_s25fl_read4_configs[] = {
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{FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ4_1_4_4, 0, 4, 4, 0x00, 2, 4},
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{FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8},
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{FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ4_1_2_2, 0, 2, 2, 0x00, 4, 0},
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{FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8},
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{FLASH_FLAG_READ_FAST, SPINOR_OP_READ4_FAST, 0, 1, 1, 0x00, 0, 8},
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{FLASH_FLAG_READ_WRITE, SPINOR_OP_READ4, 0, 1, 1, 0x00, 0, 0},
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{FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B, 0, 4, 4, 0x00, 2, 4},
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{FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B, 0, 1, 4, 0x00, 0, 8},
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{FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B, 0, 2, 2, 0x00, 4, 0},
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{FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B, 0, 1, 2, 0x00, 0, 8},
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{FLASH_FLAG_READ_FAST, SPINOR_OP_READ_FAST_4B, 0, 1, 1, 0x00, 0, 8},
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{FLASH_FLAG_READ_WRITE, SPINOR_OP_READ_4B, 0, 1, 1, 0x00, 0, 0},
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{0x00, 0, 0, 0, 0, 0x00, 0, 0},
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};
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@ -69,6 +69,7 @@ struct flash_info {
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#define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */
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#define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */
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#define USE_FSR 0x80 /* use flag status register */
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#define SPI_NOR_4B_OPCODES 0x200
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};
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#define JEDEC_MFR(info) ((info)->id[0])
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@ -182,6 +183,77 @@ static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
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return mtd->priv;
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}
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static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
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{
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size_t i;
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for (i = 0; i < size; i++)
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if (table[i][0] == opcode)
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return table[i][1];
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/* No conversion found, keep input op code. */
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return opcode;
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}
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static inline u8 spi_nor_convert_3to4_read(u8 opcode)
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{
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static const u8 spi_nor_3to4_read[][2] = {
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{ SPINOR_OP_READ, SPINOR_OP_READ_4B },
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{ SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
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{ SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
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{ SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
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{ SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
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{ SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
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};
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return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
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ARRAY_SIZE(spi_nor_3to4_read));
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}
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static inline u8 spi_nor_convert_3to4_program(u8 opcode)
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{
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static const u8 spi_nor_3to4_program[][2] = {
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{ SPINOR_OP_PP, SPINOR_OP_PP_4B },
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{ SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
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{ SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
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};
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return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
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ARRAY_SIZE(spi_nor_3to4_program));
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}
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static inline u8 spi_nor_convert_3to4_erase(u8 opcode)
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{
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static const u8 spi_nor_3to4_erase[][2] = {
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{ SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
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{ SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
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{ SPINOR_OP_SE, SPINOR_OP_SE_4B },
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};
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return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
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ARRAY_SIZE(spi_nor_3to4_erase));
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}
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static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
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const struct flash_info *info)
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{
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/* Do some manufacturer fixups first */
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switch (JEDEC_MFR(info)) {
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case SNOR_MFR_SPANSION:
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/* No small sector erase for 4-byte command set */
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nor->erase_opcode = SPINOR_OP_SE;
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nor->mtd.erasesize = info->sector_size;
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break;
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default:
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break;
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}
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nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
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nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
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nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
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}
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/* Enable/disable 4-byte addressing mode. */
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static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
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int enable)
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@ -1312,27 +1384,10 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
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else if (mtd->size > 0x1000000) {
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/* enable 4-byte addressing if the device exceeds 16MiB */
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nor->addr_width = 4;
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if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) {
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/* Dedicated 4-byte command set */
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switch (nor->flash_read) {
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case SPI_NOR_QUAD:
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nor->read_opcode = SPINOR_OP_READ4_1_1_4;
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break;
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case SPI_NOR_DUAL:
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nor->read_opcode = SPINOR_OP_READ4_1_1_2;
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break;
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case SPI_NOR_FAST:
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nor->read_opcode = SPINOR_OP_READ4_FAST;
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break;
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case SPI_NOR_NORMAL:
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nor->read_opcode = SPINOR_OP_READ4;
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break;
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}
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nor->program_opcode = SPINOR_OP_PP_4B;
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/* No small sector erase for 4-byte command set */
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nor->erase_opcode = SPINOR_OP_SE_4B;
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mtd->erasesize = info->sector_size;
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} else
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if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
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info->flags & SPI_NOR_4B_OPCODES)
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spi_nor_set_4byte_opcodes(nor, info);
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else
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set_4byte(nor, info, 1);
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} else {
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nor->addr_width = 3;
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@ -42,9 +42,13 @@
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#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
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#define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
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#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
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#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */
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#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */
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#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
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#define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
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#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
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#define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
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#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
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#define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
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#define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
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#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
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#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
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#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
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@ -53,13 +57,21 @@
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#define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
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#define SPINOR_OP_RDCR 0x35 /* Read configuration register */
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#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
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#define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
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#define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
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/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
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#define SPINOR_OP_READ4 0x13 /* Read data bytes (low frequency) */
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#define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */
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#define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */
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#define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */
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#define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
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#define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
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#define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
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#define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
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#define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
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#define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
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#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
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#define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
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#define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
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#define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
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#define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
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#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
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/* Used for SST flashes only. */
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