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arm,arm64,mips,x86: rename PPC_getFeatureBits() to getFeatureBits()

This commit is contained in:
Nguyen Anh Quynh 2013-12-31 18:15:12 +08:00
parent ec79f401b1
commit 04ac9c3725
7 changed files with 21 additions and 16 deletions
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2
arch/AArch64/AArch64Disassembler.c
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@ -212,7 +212,7 @@ static bool Check(DecodeStatus *Out, DecodeStatus In);
#include "AArch64GenSubtargetInfo.inc" #include "AArch64GenSubtargetInfo.inc"
// Hacky: enable all features for disassembler // Hacky: enable all features for disassembler
static uint64_t AArch64_getFeatureBits(void) static uint64_t getFeatureBits(void)
{ {
// enable all features // enable all features
return -1; return -1;

2
arch/AArch64/AArch64GenDisassemblerTables.inc
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@ -14036,7 +14036,7 @@ static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst *MI,
MCRegisterInfo *MRI) MCRegisterInfo *MRI)
{ {
//uint64_t Bits = 0; //uint64_t Bits = 0;
uint64_t Bits = AArch64_getFeatureBits(); uint64_t Bits = getFeatureBits();
const uint8_t *Ptr = DecodeTable; const uint8_t *Ptr = DecodeTable;
uint32_t CurFieldValue = 0; uint32_t CurFieldValue = 0;

5
arch/ARM/ARMDisassembler.c
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@ -362,7 +362,7 @@ static DecodeStatus DecodeMRRC2(MCInst *Inst, unsigned Val,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
// Hacky: enable all features for disassembler // Hacky: enable all features for disassembler
uint64_t ARM_getFeatureBits(int mode) static uint64_t getFeatureBits(int mode)
{ {
uint64_t Bits = -1; // everything by default uint64_t Bits = -1; // everything by default
@ -442,9 +442,6 @@ static DecodeStatus _ARM_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t
ud->ITBlock.size = 0; ud->ITBlock.size = 0;
//assert(!(STI.getFeatureBits() & ARM_ModeThumb) &&
// "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
if (code_len < 4) if (code_len < 4)
return MCDisassembler_Fail; return MCDisassembler_Fail;

2
arch/ARM/ARMGenDisassemblerTables.inc
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@ -13451,7 +13451,7 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
InsnType insn, size_t Address, \ InsnType insn, size_t Address, \
int feature) \ int feature) \
{ \ { \
uint64_t Bits = ARM_getFeatureBits(feature); \ uint64_t Bits = getFeatureBits(feature); \
const uint8_t *Ptr = DecodeTable; \ const uint8_t *Ptr = DecodeTable; \
uint32_t CurFieldValue = 0; \ uint32_t CurFieldValue = 0; \
DecodeStatus S = MCDisassembler_Success; \ DecodeStatus S = MCDisassembler_Success; \

22
arch/ARM/ARMInstPrinter.c
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@ -277,11 +277,15 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
case 3: SStream_concat(O, "wfi"); break; case 3: SStream_concat(O, "wfi"); break;
case 4: SStream_concat(O, "sev"); break; case 4: SStream_concat(O, "sev"); break;
case 5: case 5:
if ((ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops)) { // FIXME: HasV80Ops becomes a mode
SStream_concat(O, "sevl"); break; //if ((ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops)) {
break; // SStream_concat(O, "sevl");
} // break;
//}
// Fallthrough for non-v8 // Fallthrough for non-v8
SStream_concat(O, "sevl");
break;
default: default:
// Anything else should just print normally. // Anything else should just print normally.
printInstruction(MI, O, MRI); printInstruction(MI, O, MRI);
@ -1121,8 +1125,10 @@ static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *
static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O) static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O)
{ {
unsigned val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); unsigned val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
SStream_concat(O, ARM_MB_MemBOptToString(val, // FIXME: HasV80Ops becomes a mode
ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops)); // SStream_concat(O, ARM_MB_MemBOptToString(val,
// ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops));
SStream_concat(O, ARM_MB_MemBOptToString(val, ARM_HasV8Ops));
} }
void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O) void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O)
@ -1269,7 +1275,9 @@ static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O)
unsigned SpecRegRBit = MCOperand_getImm(Op) >> 4; unsigned SpecRegRBit = MCOperand_getImm(Op) >> 4;
unsigned Mask = MCOperand_getImm(Op) & 0xf; unsigned Mask = MCOperand_getImm(Op) & 0xf;
if (ARM_getFeatureBits(MI->csh->mode) & ARM_FeatureMClass) { // FIXME: FeatureMClass becomes mode??
//if (ARM_getFeatureBits(MI->csh->mode) & ARM_FeatureMClass) {
if (true) {
unsigned SYSm = MCOperand_getImm(Op); unsigned SYSm = MCOperand_getImm(Op);
unsigned Opcode = MCInst_getOpcode(MI); unsigned Opcode = MCInst_getOpcode(MI);
// For reads of the special registers ignore the "mask encoding" bits // For reads of the special registers ignore the "mask encoding" bits

2
arch/Mips/MipsDisassembler.c
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@ -151,7 +151,7 @@ static DecodeStatus DecodeExtSize(MCInst *Inst,
#include "MipsGenSubtargetInfo.inc" #include "MipsGenSubtargetInfo.inc"
// Hacky: enable all features for disassembler // Hacky: enable all features for disassembler
static uint64_t Mips_getFeatureBits(int mode) static uint64_t getFeatureBits(int mode)
{ {
uint64_t Bits = -1; // include every features by default uint64_t Bits = -1; // include every features by default

2
arch/Mips/MipsGenDisassemblerTables.inc
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@ -5313,7 +5313,7 @@ static DecodeStatus decodeToMCInst(DecodeStatus S, unsigned Idx, uint32_t insn,
static DecodeStatus decodeInstruction(uint8_t DecodeTable[], MCInst *MI, static DecodeStatus decodeInstruction(uint8_t DecodeTable[], MCInst *MI,
uint32_t insn, uint64_t Address, MCRegisterInfo *MRI, int mode) uint32_t insn, uint64_t Address, MCRegisterInfo *MRI, int mode)
{ {
uint64_t Bits = Mips_getFeatureBits(mode); uint64_t Bits = getFeatureBits(mode);
uint8_t *Ptr = DecodeTable; uint8_t *Ptr = DecodeTable;
uint32_t CurFieldValue = 0; uint32_t CurFieldValue = 0;
DecodeStatus S = MCDisassembler_Success; DecodeStatus S = MCDisassembler_Success;