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Format all .(c|h) code

This commit is contained in:
billow 2023-04-20 21:55:37 +08:00
parent 2919f94530
commit 2785d31399
10 changed files with 840 additions and 658 deletions
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609
arch/TriCore/TriCoreDisassembler.c
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File diff suppressed because it is too large Load Diff

4
arch/TriCore/TriCoreDisassembler.h
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@ -15,7 +15,7 @@
void TriCore_init(MCRegisterInfo *MRI);
bool TriCore_getInstruction(csh ud, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address, void *info);
MCInst *instr, uint16_t *size, uint64_t address,
void *info);
#endif

506
arch/TriCore/TriCoreInstPrinter.c
View File

@ -35,7 +35,8 @@ static void printInstruction(MCInst *, uint64_t, SStream *);
static void printOperand(MCInst *MI, int OpNum, SStream *O);
void TriCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) {
void TriCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
{
/*
if (((cs_struct *)ud)->detail != CS_OPT_ON)
return;
@ -54,106 +55,113 @@ static inline void fill_mem(cs_tricore *tc, uint8_t base, int32_t disp);
static bool fixup_op_mem(MCInst *pInst, unsigned int reg, int32_t disp);
static inline void fill_tricore_register(MCInst *MI, uint32_t reg) {
if (!(MI->csh->detail == CS_OPT_ON && MI->flat_insn->detail)) return;
static inline void fill_tricore_register(MCInst *MI, uint32_t reg)
{
if (!(MI->csh->detail == CS_OPT_ON && MI->flat_insn->detail))
return;
cs_tricore *tricore = &MI->flat_insn->detail->tricore;
tricore->operands[tricore->op_count]
.type = TRICORE_OP_REG;
tricore->operands[tricore->op_count]
.reg = reg;
tricore->operands[tricore->op_count].type = TRICORE_OP_REG;
tricore->operands[tricore->op_count].reg = reg;
tricore->op_count++;
}
static inline void fill_tricore_imm(MCInst *MI, int32_t imm) {
if (!(MI->csh->detail == CS_OPT_ON && MI->flat_insn->detail)) return;
static inline void fill_tricore_imm(MCInst *MI, int32_t imm)
{
if (!(MI->csh->detail == CS_OPT_ON && MI->flat_insn->detail))
return;
cs_tricore *tricore = &MI->flat_insn->detail->tricore;
if (tricore->op_count >= 1 && tricore->operands[tricore->op_count - 1].type == TRICORE_OP_REG &&
fixup_op_mem(MI, tricore->operands[tricore->op_count - 1].reg, imm)) { return; }
tricore->operands[tricore->op_count]
.type = TRICORE_OP_IMM;
tricore->operands[tricore->op_count]
.imm = imm;
if (tricore->op_count >= 1 &&
tricore->operands[tricore->op_count - 1].type == TRICORE_OP_REG &&
fixup_op_mem(MI, tricore->operands[tricore->op_count - 1].reg,
imm)) {
return;
}
tricore->operands[tricore->op_count].type = TRICORE_OP_IMM;
tricore->operands[tricore->op_count].imm = imm;
tricore->op_count++;
}
static bool fixup_op_mem(MCInst *pInst, unsigned int reg, int32_t disp) {
static bool fixup_op_mem(MCInst *pInst, unsigned int reg, int32_t disp)
{
switch (TriCore_map_insn_id(pInst->csh, pInst->Opcode)) {
case TriCore_INS_LDMST:
case TriCore_INS_LDLCX:
case TriCore_INS_LD_A:
case TriCore_INS_LD_B:
case TriCore_INS_LD_BU:
case TriCore_INS_LD_H:
case TriCore_INS_LD_HU:
case TriCore_INS_LD_D:
case TriCore_INS_LD_DA:
case TriCore_INS_LD_W:
case TriCore_INS_LD_Q:
case TriCore_INS_STLCX:
case TriCore_INS_STUCX:
case TriCore_INS_ST_A:
case TriCore_INS_ST_B:
case TriCore_INS_ST_H:
case TriCore_INS_ST_D:
case TriCore_INS_ST_DA:
case TriCore_INS_ST_W:
case TriCore_INS_ST_Q:
case TriCore_INS_CACHEI_I:
case TriCore_INS_CACHEI_W:
case TriCore_INS_CACHEI_WI:
case TriCore_INS_CACHEA_I:
case TriCore_INS_CACHEA_W:
case TriCore_INS_CACHEA_WI:
case TriCore_INS_CMPSWAP_W:
case TriCore_INS_SWAP_A:
case TriCore_INS_SWAP_W:
case TriCore_INS_SWAPMSK_W:
case TriCore_INS_LEA:
case TriCore_INS_LHA: {
switch (MCInst_getOpcode(pInst)) {
case TriCore_LDMST_abs:
case TriCore_LDLCX_abs:
case TriCore_LD_A_abs:
case TriCore_LD_B_abs:
case TriCore_LD_BU_abs:
case TriCore_LD_H_abs:
case TriCore_LD_HU_abs:
case TriCore_LD_D_abs:
case TriCore_LD_DA_abs:
case TriCore_LD_W_abs:
case TriCore_LD_Q_abs:
case TriCore_STLCX_abs:
case TriCore_STUCX_abs:
case TriCore_ST_A_abs:
case TriCore_ST_B_abs:
case TriCore_ST_H_abs:
case TriCore_ST_D_abs:
case TriCore_ST_DA_abs:
case TriCore_ST_W_abs:
case TriCore_ST_Q_abs:
case TriCore_SWAP_A_abs:
case TriCore_SWAP_W_abs:
case TriCore_LEA_abs:
case TriCore_LHA_abs: {
return false;
}
}
cs_tricore *tc = &pInst->flat_insn->detail->tricore;
fill_mem(tc, reg, disp);
return true;
case TriCore_INS_LDMST:
case TriCore_INS_LDLCX:
case TriCore_INS_LD_A:
case TriCore_INS_LD_B:
case TriCore_INS_LD_BU:
case TriCore_INS_LD_H:
case TriCore_INS_LD_HU:
case TriCore_INS_LD_D:
case TriCore_INS_LD_DA:
case TriCore_INS_LD_W:
case TriCore_INS_LD_Q:
case TriCore_INS_STLCX:
case TriCore_INS_STUCX:
case TriCore_INS_ST_A:
case TriCore_INS_ST_B:
case TriCore_INS_ST_H:
case TriCore_INS_ST_D:
case TriCore_INS_ST_DA:
case TriCore_INS_ST_W:
case TriCore_INS_ST_Q:
case TriCore_INS_CACHEI_I:
case TriCore_INS_CACHEI_W:
case TriCore_INS_CACHEI_WI:
case TriCore_INS_CACHEA_I:
case TriCore_INS_CACHEA_W:
case TriCore_INS_CACHEA_WI:
case TriCore_INS_CMPSWAP_W:
case TriCore_INS_SWAP_A:
case TriCore_INS_SWAP_W:
case TriCore_INS_SWAPMSK_W:
case TriCore_INS_LEA:
case TriCore_INS_LHA: {
switch (MCInst_getOpcode(pInst)) {
case TriCore_LDMST_abs:
case TriCore_LDLCX_abs:
case TriCore_LD_A_abs:
case TriCore_LD_B_abs:
case TriCore_LD_BU_abs:
case TriCore_LD_H_abs:
case TriCore_LD_HU_abs:
case TriCore_LD_D_abs:
case TriCore_LD_DA_abs:
case TriCore_LD_W_abs:
case TriCore_LD_Q_abs:
case TriCore_STLCX_abs:
case TriCore_STUCX_abs:
case TriCore_ST_A_abs:
case TriCore_ST_B_abs:
case TriCore_ST_H_abs:
case TriCore_ST_D_abs:
case TriCore_ST_DA_abs:
case TriCore_ST_W_abs:
case TriCore_ST_Q_abs:
case TriCore_SWAP_A_abs:
case TriCore_SWAP_W_abs:
case TriCore_LEA_abs:
case TriCore_LHA_abs: {
return false;
}
}
cs_tricore *tc = &pInst->flat_insn->detail->tricore;
fill_mem(tc, reg, disp);
return true;
}
}
return false;
}
static inline void fill_mem(cs_tricore *tc, uint8_t base, int32_t disp) {
static inline void fill_mem(cs_tricore *tc, uint8_t base, int32_t disp)
{
cs_tricore_op *op = &tc->operands[tc->op_count - 1];
op->type = TRICORE_OP_MEM;
op->mem.base = base;
op->mem.disp = disp;
}
static void printOperand(MCInst *MI, int OpNum, SStream *O) {
static void printOperand(MCInst *MI, int OpNum, SStream *O)
{
MCOperand *Op;
if (OpNum >= MI->size)
return;
@ -179,34 +187,38 @@ static void printOperand(MCInst *MI, int OpNum, SStream *O) {
SStream_concat(O, "-%" PRIu64, -Imm);
}
fill_tricore_imm(MI, (int32_t) Imm);
fill_tricore_imm(MI, (int32_t)Imm);
}
}
static inline unsigned int get_msb(unsigned int value) {
static inline unsigned int get_msb(unsigned int value)
{
unsigned int msb = 0;
while (value > 0) {
value >>= 1; // Shift bits to the right
msb++; // Increment the position of the MSB
msb++; // Increment the position of the MSB
}
return msb;
}
static inline int32_t sign_ext_n(int32_t imm, unsigned n) {
static inline int32_t sign_ext_n(int32_t imm, unsigned n)
{
n = get_msb(imm) > n ? get_msb(imm) : n;
int32_t mask = 1 << (n - 1);
int32_t sign_extended = (imm ^ mask) - mask;
return sign_extended;
}
static inline void SS_print_hex(SStream *O, int32_t imm) {
static inline void SS_print_hex(SStream *O, int32_t imm)
{
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%x", imm);
else
SStream_concat(O, "%u", imm);
}
static inline void SS_print_sign_hex(SStream *O, int32_t imm) {
static inline void SS_print_sign_hex(SStream *O, int32_t imm)
{
if (imm >= 0) {
SS_print_hex(O, imm);
} else {
@ -217,10 +229,11 @@ static inline void SS_print_sign_hex(SStream *O, int32_t imm) {
}
}
static void print_sign_ext(MCInst *MI, int OpNum, SStream *O, unsigned n) {
static void print_sign_ext(MCInst *MI, int OpNum, SStream *O, unsigned n)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
if (MCOperand_isImm(MO)) {
int32_t imm = (int32_t) MCOperand_getImm(MO);
int32_t imm = (int32_t)MCOperand_getImm(MO);
imm = sign_ext_n(imm, n);
SS_print_sign_hex(O, imm);
fill_tricore_imm(MI, imm);
@ -228,30 +241,32 @@ static void print_sign_ext(MCInst *MI, int OpNum, SStream *O, unsigned n) {
printOperand(MI, OpNum, O);
}
static void off4_fixup(MCInst *MI, uint64_t *off4) {
static void off4_fixup(MCInst *MI, uint64_t *off4)
{
switch (MCInst_getOpcode(MI)) {
case TriCore_LD_A_slro:
case TriCore_LD_A_sro:
case TriCore_LD_W_slro:
case TriCore_LD_W_sro:
case TriCore_ST_A_sro:
case TriCore_ST_A_ssro:
case TriCore_ST_W_sro:
case TriCore_ST_W_ssro: {
*off4 *= 4;
break;
}
case TriCore_LD_H_sro:
case TriCore_LD_H_slro:
case TriCore_ST_H_sro:
case TriCore_ST_H_ssro: {
*off4 *= 2;
break;
}
case TriCore_LD_A_slro:
case TriCore_LD_A_sro:
case TriCore_LD_W_slro:
case TriCore_LD_W_sro:
case TriCore_ST_A_sro:
case TriCore_ST_A_ssro:
case TriCore_ST_W_sro:
case TriCore_ST_W_ssro: {
*off4 *= 4;
break;
}
case TriCore_LD_H_sro:
case TriCore_LD_H_slro:
case TriCore_ST_H_sro:
case TriCore_ST_H_ssro: {
*off4 *= 2;
break;
}
}
}
static void print_zero_ext(MCInst *MI, int OpNum, SStream *O, unsigned n) {
static void print_zero_ext(MCInst *MI, int OpNum, SStream *O, unsigned n)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
if (MCOperand_isImm(MO)) {
uint64_t imm = MCOperand_getImm(MO);
@ -278,47 +293,54 @@ static void print_zero_ext(MCInst *MI, int OpNum, SStream *O, unsigned n) {
printOperand(MI, OpNum, O);
}
static void printOff18Imm(MCInst *MI, int OpNum, SStream *O) {
static void printOff18Imm(MCInst *MI, int OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
if (MCOperand_isImm(MO)) {
uint32_t imm = (uint32_t) MCOperand_getImm(MO);
uint32_t imm = (uint32_t)MCOperand_getImm(MO);
imm = ((imm & 0x3C000) << 14) | (imm & 0x3fff);
SStream_concat(O, "0x%x", imm);
fill_tricore_imm(MI, (int32_t) imm);
fill_tricore_imm(MI, (int32_t)imm);
} else
printOperand(MI, OpNum, O);
}
static inline void fixup_tricore_disp(MCInst *MI, int OpNum, int32_t disp) {
if (MI->csh->detail != CS_OPT_ON) return;
if (OpNum <= 0) return;
static inline void fixup_tricore_disp(MCInst *MI, int OpNum, int32_t disp)
{
if (MI->csh->detail != CS_OPT_ON)
return;
if (OpNum <= 0)
return;
cs_tricore *tricore = &MI->flat_insn->detail->tricore;
if (tricore->operands[tricore->op_count - 1].type != TRICORE_OP_REG) return;
if (tricore->operands[tricore->op_count - 1].type != TRICORE_OP_REG)
return;
fill_mem(tricore, tricore->operands[tricore->op_count - 1].reg, disp);
}
static void printDisp24Imm(MCInst *MI, int OpNum, SStream *O) {
static void printDisp24Imm(MCInst *MI, int OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
if (MCOperand_isImm(MO)) {
int32_t disp = (int32_t) MCOperand_getImm(MO);
int32_t disp = (int32_t)MCOperand_getImm(MO);
switch (MCInst_getOpcode(MI)) {
case TriCore_CALL_b:
case TriCore_FCALL_b: {
disp = (int32_t) MI->address + sign_ext_n(disp * 2, 24);
break;
}
case TriCore_CALLA_b:
case TriCore_FCALLA_b:
case TriCore_JA_b:
case TriCore_JLA_b:
// = {disp24[23:20], 7’b0000000, disp24[19:0], 1’b0};
disp = ((disp & 0xf00000) << 28) | ((disp & 0xfffff) << 1);
break;
case TriCore_J_b:
case TriCore_JL_b:
disp = (int32_t) MI->address + sign_ext_n(disp, 24) * 2;
break;
case TriCore_CALL_b:
case TriCore_FCALL_b: {
disp = (int32_t)MI->address + sign_ext_n(disp * 2, 24);
break;
}
case TriCore_CALLA_b:
case TriCore_FCALLA_b:
case TriCore_JA_b:
case TriCore_JLA_b:
// = {disp24[23:20], 7’b0000000, disp24[19:0], 1’b0};
disp = ((disp & 0xf00000) << 28) |
((disp & 0xfffff) << 1);
break;
case TriCore_J_b:
case TriCore_JL_b:
disp = (int32_t)MI->address + sign_ext_n(disp, 24) * 2;
break;
}
SS_print_sign_hex(O, disp);
@ -327,42 +349,43 @@ static void printDisp24Imm(MCInst *MI, int OpNum, SStream *O) {
printOperand(MI, OpNum, O);
}
static void printDisp15Imm(MCInst *MI, int OpNum, SStream *O) {
static void printDisp15Imm(MCInst *MI, int OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
if (MCOperand_isImm(MO)) {
int32_t disp = (int32_t) MCOperand_getImm(MO);
int32_t disp = (int32_t)MCOperand_getImm(MO);
switch (MCInst_getOpcode(MI)) {
case TriCore_JEQ_brc:
case TriCore_JEQ_brr:
case TriCore_JEQ_A_brr:
case TriCore_JGE_brc:
case TriCore_JGE_brr:
case TriCore_JGE_U_brc:
case TriCore_JGE_U_brr:
case TriCore_JLT_brc:
case TriCore_JLT_brr:
case TriCore_JLT_U_brc:
case TriCore_JLT_U_brr:
case TriCore_JNE_brc:
case TriCore_JNE_brr:
case TriCore_JNE_A_brr:
case TriCore_JNED_brc:
case TriCore_JNED_brr:
case TriCore_JNEI_brc:
case TriCore_JNEI_brr:
case TriCore_JNZ_A_brr:
case TriCore_JNZ_T_brn:
case TriCore_JZ_A_brr:
case TriCore_JZ_T_brn:
disp = (int32_t) MI->address + sign_ext_n(disp, 15) * 2;
break;
case TriCore_LOOP_brr:
case TriCore_LOOPU_brr:
disp = (int32_t) MI->address + sign_ext_n(disp * 2, 15);
break;
default:
// handle other cases, if any
break;
case TriCore_JEQ_brc:
case TriCore_JEQ_brr:
case TriCore_JEQ_A_brr:
case TriCore_JGE_brc:
case TriCore_JGE_brr:
case TriCore_JGE_U_brc:
case TriCore_JGE_U_brr:
case TriCore_JLT_brc:
case TriCore_JLT_brr:
case TriCore_JLT_U_brc:
case TriCore_JLT_U_brr:
case TriCore_JNE_brc:
case TriCore_JNE_brr:
case TriCore_JNE_A_brr:
case TriCore_JNED_brc:
case TriCore_JNED_brr:
case TriCore_JNEI_brc:
case TriCore_JNEI_brr:
case TriCore_JNZ_A_brr:
case TriCore_JNZ_T_brn:
case TriCore_JZ_A_brr:
case TriCore_JZ_T_brn:
disp = (int32_t)MI->address + sign_ext_n(disp, 15) * 2;
break;
case TriCore_LOOP_brr:
case TriCore_LOOPU_brr:
disp = (int32_t)MI->address + sign_ext_n(disp * 2, 15);
break;
default:
// handle other cases, if any
break;
}
SS_print_sign_hex(O, disp);
@ -371,22 +394,23 @@ static void printDisp15Imm(MCInst *MI, int OpNum, SStream *O) {
printOperand(MI, OpNum, O);
}
static void printDisp8Imm(MCInst *MI, int OpNum, SStream *O) {
static void printDisp8Imm(MCInst *MI, int OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
if (MCOperand_isImm(MO)) {
int32_t disp = (int32_t) MCOperand_getImm(MO);
int32_t disp = (int32_t)MCOperand_getImm(MO);
switch (MCInst_getOpcode(MI)) {
case TriCore_CALL_sb:
disp = (int32_t) MI->address + sign_ext_n(2 * disp, 8);
break;
case TriCore_J_sb:
case TriCore_JNZ_sb:
case TriCore_JZ_sb:
disp = (int32_t) MI->address + sign_ext_n(disp, 8) * 2;
break;
default:
// handle other cases, if any
break;
case TriCore_CALL_sb:
disp = (int32_t)MI->address + sign_ext_n(2 * disp, 8);
break;
case TriCore_J_sb:
case TriCore_JNZ_sb:
case TriCore_JZ_sb:
disp = (int32_t)MI->address + sign_ext_n(disp, 8) * 2;
break;
default:
// handle other cases, if any
break;
}
SS_print_sign_hex(O, disp);
@ -395,40 +419,43 @@ static void printDisp8Imm(MCInst *MI, int OpNum, SStream *O) {
printOperand(MI, OpNum, O);
}
static void printDisp4Imm(MCInst *MI, int OpNum, SStream *O) {
static void printDisp4Imm(MCInst *MI, int OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
if (MCOperand_isImm(MO)) {
int32_t disp = (int32_t) MCOperand_getImm(MO);
int32_t disp = (int32_t)MCOperand_getImm(MO);
switch (MCInst_getOpcode(MI)) {
case TriCore_JEQ_sbc1:
case TriCore_JEQ_sbr1:
case TriCore_JGEZ_sbr:
case TriCore_JGTZ_sbr:
case TriCore_JLEZ_sbr:
case TriCore_JLTZ_sbr:
case TriCore_JNE_sbc1:
case TriCore_JNE_sbr1:
case TriCore_JNZ_sbr:
case TriCore_JNZ_A_sbr:
case TriCore_JNZ_T_sbrn:
case TriCore_JZ_sbr:
case TriCore_JZ_A_sbr:
case TriCore_JZ_T_sbrn:
disp = (int32_t) MI->address + disp * 2;
break;
case TriCore_JEQ_sbc2:
case TriCore_JEQ_sbr2:
case TriCore_JNE_sbc2:
case TriCore_JNE_sbr2:
disp = (int32_t) MI->address + (disp + 16) * 2;
break;
case TriCore_LOOP_sbr:
// {27b’111111111111111111111111111, disp4, 0};
disp = (int32_t) MI->address + ((0b111111111111111111111111111 << 5) | (disp << 1));
break;
default:
// handle other cases, if any
break;
case TriCore_JEQ_sbc1:
case TriCore_JEQ_sbr1:
case TriCore_JGEZ_sbr:
case TriCore_JGTZ_sbr:
case TriCore_JLEZ_sbr:
case TriCore_JLTZ_sbr:
case TriCore_JNE_sbc1:
case TriCore_JNE_sbr1:
case TriCore_JNZ_sbr:
case TriCore_JNZ_A_sbr:
case TriCore_JNZ_T_sbrn:
case TriCore_JZ_sbr:
case TriCore_JZ_A_sbr:
case TriCore_JZ_T_sbrn:
disp = (int32_t)MI->address + disp * 2;
break;
case TriCore_JEQ_sbc2:
case TriCore_JEQ_sbr2:
case TriCore_JNE_sbc2:
case TriCore_JNE_sbr2:
disp = (int32_t)MI->address + (disp + 16) * 2;
break;
case TriCore_LOOP_sbr:
// {27b’111111111111111111111111111, disp4, 0};
disp = (int32_t)MI->address +
((0b111111111111111111111111111 << 5) |
(disp << 1));
break;
default:
// handle other cases, if any
break;
}
SS_print_sign_hex(O, disp);
@ -437,42 +464,45 @@ static void printDisp4Imm(MCInst *MI, int OpNum, SStream *O) {
printOperand(MI, OpNum, O);
}
#define printSExtImm_(n) \
static void printSExtImm_ ##n(MCInst *MI, int OpNum, SStream *O) \
{ \
print_sign_ext(MI, OpNum, O, n); \
}
#define printSExtImm_(n) \
static void printSExtImm_##n(MCInst *MI, int OpNum, SStream *O) \
{ \
print_sign_ext(MI, OpNum, O, n); \
}
printSExtImm_(16)
printSExtImm_(10)
printSExtImm_(10)
printSExtImm_(9)
printSExtImm_(9)
printSExtImm_(4)
printSExtImm_(4)
#define printZExtImm_(n) \
static void printZExtImm_ ##n(MCInst *MI, int OpNum, SStream *O) \
{ \
print_zero_ext(MI, OpNum, O, n); \
}
#define printZExtImm_(n) \
static void printZExtImm_##n(MCInst *MI, int OpNum, SStream *O) \
{ \
print_zero_ext(MI, OpNum, O, n); \
}
printZExtImm_(16)
printZExtImm_(16)
printZExtImm_(9)
printZExtImm_(9)
printZExtImm_(8)
printZExtImm_(8)
printZExtImm_(4)
printZExtImm_(4)
printZExtImm_(2)
printZExtImm_(2)
static void printOExtImm_4(MCInst *MI, int OpNum, SStream *O) {
static void printOExtImm_4(
MCInst *MI,
int OpNum,
SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
if (MCOperand_isImm(MO)) {
uint32_t imm = MCOperand_getImm(MO);
// {27b’111111111111111111111111111, disp4, 0};
// {27b’111111111111111111111111111, disp4, 0};
imm = 0b11111111111111111111111111100000 | (imm << 1);
SS_print_sign_hex(O, imm);
@ -481,14 +511,14 @@ static void printOExtImm_4(MCInst *MI, int OpNum, SStream *O) {
printOperand(MI, OpNum, O);
}
/// Returned by getMnemonic() of the AsmPrinters.
typedef struct {
const char *first; // Menmonic
uint64_t second; // Bits
uint64_t second; // Bits
} MnemonicBitsInfo;
void set_mem_access(MCInst *MI, unsigned int access) {
void set_mem_access(MCInst *MI, unsigned int access)
{
// TODO: TriCore
}
@ -496,7 +526,8 @@ void set_mem_access(MCInst *MI, unsigned int access) {
#include "TriCoreGenAsmWriter.inc"
const char *TriCore_getRegisterName(csh handle, unsigned int id) {
const char *TriCore_getRegisterName(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
return getRegisterName(id);
#else
@ -504,7 +535,8 @@ const char *TriCore_getRegisterName(csh handle, unsigned int id) {
#endif
}
void TriCore_printInst(MCInst *MI, SStream *O, void *Info) {
void TriCore_printInst(MCInst *MI, SStream *O, void *Info)
{
printInstruction(MI, MI->address, O);
}

57
arch/TriCore/TriCoreMapping.c
View File

@ -15,23 +15,25 @@
#include "TriCoreGenInstrInfo.inc"
static insn_map insns[] = {
// dummy item
{0,
0,
// dummy item
{ 0,
0,
#ifndef CAPSTONE_DIET
{0},
{0},
{0},
0,
0
{ 0 },
{ 0 },
{ 0 },
0,
0
#endif
},
},
#include "TriCoreGenCSMappingInsn.inc"
};
unsigned int TriCore_map_insn_id(cs_struct *h, unsigned int id) {
unsigned short i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
unsigned int TriCore_map_insn_id(cs_struct *h, unsigned int id)
{
unsigned short i =
insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
if (i != 0) {
return insns[i].mapid;
}
@ -39,7 +41,8 @@ unsigned int TriCore_map_insn_id(cs_struct *h, unsigned int id) {
}
// given internal insn id, return public instruction info
void TriCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) {
void TriCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
{
unsigned short i;
i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
@ -51,19 +54,23 @@ void TriCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) {
memcpy(insn->detail->regs_read, insns[i].regs_use,
sizeof(insns[i].regs_use));
insn->detail->regs_read_count =
(uint8_t) count_positive(insns[i].regs_use);
(uint8_t)count_positive(insns[i].regs_use);
memcpy(insn->detail->regs_write, insns[i].regs_mod,
sizeof(insns[i].regs_mod));
insn->detail->regs_write_count =
(uint8_t) count_positive(insns[i].regs_mod);
(uint8_t)count_positive(insns[i].regs_mod);
memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
insn->detail->groups_count = (uint8_t) count_positive8(insns[i].groups);
memcpy(insn->detail->groups, insns[i].groups,
sizeof(insns[i].groups));
insn->detail->groups_count =
(uint8_t)count_positive8(insns[i].groups);
if (insns[i].branch || insns[i].indirect_branch) {
// this insn also belongs to JUMP group. add JUMP group
insn->detail->groups[insn->detail->groups_count] = TriCore_GRP_JUMP;
insn->detail
->groups[insn->detail->groups_count] =
TriCore_GRP_JUMP;
insn->detail->groups_count++;
}
#endif
@ -74,16 +81,17 @@ void TriCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) {
#ifndef CAPSTONE_DIET
static const char *insn_names[] = {
NULL,
NULL,
#include "TriCoreGenCSMappingInsnName.inc"
};
// special alias insn
static name_map alias_insn_names[] = {{0, NULL}};
static name_map alias_insn_names[] = { { 0, NULL } };
#endif
const char *TriCore_insn_name(csh handle, unsigned int id) {
const char *TriCore_insn_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
unsigned int i;
@ -104,13 +112,14 @@ const char *TriCore_insn_name(csh handle, unsigned int id) {
#ifndef CAPSTONE_DIET
static name_map group_name_maps[] = {
{TriCore_GRP_INVALID, NULL},
{TriCore_GRP_CALL, "call"},
{TriCore_GRP_JUMP, "jump"},
{ TriCore_GRP_INVALID, NULL },
{ TriCore_GRP_CALL, "call" },
{ TriCore_GRP_JUMP, "jump" },
};
#endif
const char *TriCore_group_name(csh handle, unsigned int id) {
const char *TriCore_group_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
if (id >= TriCore_GRP_ENDING)
return NULL;

1
arch/TriCore/TriCoreMapping.h
View File

@ -16,4 +16,3 @@ const char *TriCore_insn_name(csh handle, unsigned int id);
const char *TriCore_group_name(csh handle, unsigned int id);
#endif

2
arch/TriCore/TriCoreModule.c
View File

@ -32,7 +32,7 @@ cs_err TRICORE_global_init(cs_struct *ud)
cs_err TRICORE_option(cs_struct *handle, cs_opt_type type, size_t value)
{
if (type == CS_OPT_SYNTAX)
handle->syntax = (int) value;
handle->syntax = (int)value;
return CS_ERR_OK;
}

108
cstool/cstool_tricore.c
View File

@ -5,61 +5,67 @@
void print_insn_detail_tricore(csh handle, cs_insn *ins)
{
cs_tricore *tricore;
int i;
cs_regs regs_read, regs_write;
uint8_t regs_read_count, regs_write_count;
cs_tricore *tricore;
int i;
cs_regs regs_read, regs_write;
uint8_t regs_read_count, regs_write_count;
// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
if (ins->detail == NULL)
return;
// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
if (ins->detail == NULL)
return;
tricore = &(ins->detail->tricore);
tricore = &(ins->detail->tricore);
if (tricore->op_count)
printf("\top_count: %u\n", tricore->op_count);
if (tricore->op_count)
printf("\top_count: %u\n", tricore->op_count);
for (i = 0; i < tricore->op_count; i++) {
cs_tricore_op *op = &(tricore->operands[i]);
switch ((int)op->type) {
default:
break;
case TRICORE_OP_REG:
printf("\t\toperands[%u].type: REG = %s\n", i,
cs_reg_name(handle, op->reg));
break;
case TRICORE_OP_IMM:
printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm);
break;
case TRICORE_OP_MEM:
printf("\t\toperands[%u].type: MEM\n", i);
if (op->mem.base != TriCore_REG_INVALID)
printf("\t\t\toperands[%u].mem.base: REG = %s\n", i,
cs_reg_name(handle, op->mem.base));
if (op->mem.disp != 0)
printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp);
break;
}
for (i = 0; i < tricore->op_count; i++) {
cs_tricore_op *op = &(tricore->operands[i]);
switch ((int)op->type) {
default:
break;
case TRICORE_OP_REG:
printf("\t\toperands[%u].type: REG = %s\n", i,
cs_reg_name(handle, op->reg));
break;
case TRICORE_OP_IMM:
printf("\t\toperands[%u].type: IMM = 0x%x\n", i,
op->imm);
break;
case TRICORE_OP_MEM:
printf("\t\toperands[%u].type: MEM\n", i);
if (op->mem.base != TriCore_REG_INVALID)
printf("\t\t\toperands[%u].mem.base: REG = %s\n",
i, cs_reg_name(handle, op->mem.base));
if (op->mem.disp != 0)
printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i,
op->mem.disp);
break;
}
// Print out all registers accessed by this instruction (either implicit or
// explicit)
if (!cs_regs_access(handle, ins, regs_read, &regs_read_count, regs_write,
&regs_write_count)) {
if (regs_read_count) {
printf("\tRegisters read:");
for (i = 0; i < regs_read_count; i++) {
printf(" %s", cs_reg_name(handle, regs_read[i]));
// Print out all registers accessed by this instruction (either implicit or
// explicit)
if (!cs_regs_access(handle, ins, regs_read, &regs_read_count,
regs_write, &regs_write_count)) {
if (regs_read_count) {
printf("\tRegisters read:");
for (i = 0; i < regs_read_count; i++) {
printf(" %s",
cs_reg_name(handle,
regs_read[i]));
}
printf("\n");
}
if (regs_write_count) {
printf("\tRegisters modified:");
for (i = 0; i < regs_write_count; i++) {
printf(" %s",
cs_reg_name(handle,
regs_write[i]));
}
printf("\n");
}
}
}
printf("\n");
}
if (regs_write_count) {
printf("\tRegisters modified:");
for (i = 0; i < regs_write_count; i++) {
printf(" %s", cs_reg_name(handle, regs_write[i]));
}
printf("\n");
}
}
}
}

26
include/capstone/tricore.h
View File

@ -15,7 +15,7 @@ extern "C" {
#include "platform.h"
#ifdef _MSC_VER
#pragma warning(disable:4201)
#pragma warning(disable : 4201)
#endif
//> Operand type for instruction's operands
@ -29,17 +29,17 @@ typedef enum tricore_op_type {
// Instruction's operand referring to memory
// This is associated with TRICORE_OP_MEM operand type above
typedef struct tricore_op_mem {
uint8_t base; // base register
int32_t disp; // displacement/offset value
uint8_t base; // base register
int32_t disp; // displacement/offset value
} tricore_op_mem;
// Instruction operand
typedef struct cs_tricore_op {
tricore_op_type type; // operand type
tricore_op_type type; // operand type
union {
unsigned int reg; // register value for REG operand
int32_t imm; // immediate value for IMM operand
tricore_op_mem mem; // base/disp value for MEM operand
unsigned int reg; // register value for REG operand
int32_t imm; // immediate value for IMM operand
tricore_op_mem mem; // base/disp value for MEM operand
};
} cs_tricore_op;
@ -60,22 +60,22 @@ typedef enum tricore_reg {
typedef enum tricore_insn {
TriCore_INS_INVALID = 0,
#include "./inc/TriCoreGenCSInsnEnum.inc"
TriCore_INS_ENDING, // <-- mark the end of the list of instructions
TriCore_INS_ENDING, // <-- mark the end of the list of instructions
} tricore_insn;
//> Group of TriCore instructions
typedef enum tricore_insn_group {
TriCore_GRP_INVALID, ///< = CS_GRP_INVALID
TriCore_GRP_INVALID, ///< = CS_GRP_INVALID
//> Generic groups
TriCore_GRP_CALL, ///< = CS_GRP_CALL
TriCore_GRP_JUMP, ///< = CS_GRP_JUMP
TriCore_GRP_ENDING, ///< = mark the end of the list of groups
TriCore_GRP_CALL, ///< = CS_GRP_CALL
TriCore_GRP_JUMP, ///< = CS_GRP_JUMP
TriCore_GRP_ENDING, ///< = mark the end of the list of groups
} tricore_insn_group;
typedef enum tricore_feature_t {
TriCore_FEATURE_INVALID = 0,
#include "./inc/TriCoreGenCSFeatureEnum.inc"
TriCore_FEATURE_ENDING, // <-- mark the end of the list of features
TriCore_FEATURE_ENDING, // <-- mark the end of the list of features
} tricore_feature;
#ifdef __cplusplus

119
suite/cstest/src/tricore_detail.c
View File

@ -6,69 +6,76 @@
char *get_detail_tricore(csh *p_handle, cs_mode mode, cs_insn *ins)
{
cs_tricore *tricore;
int i;
cs_regs regs_read, regs_write;
uint8_t regs_read_count, regs_write_count;
cs_tricore *tricore;
int i;
cs_regs regs_read, regs_write;
uint8_t regs_read_count, regs_write_count;
char *result;
result = (char *)malloc(sizeof(char));
result[0] = '\0';
char *result;
result = (char *)malloc(sizeof(char));
result[0] = '\0';
if (ins->detail == NULL)
return result;
if (ins->detail == NULL)
return result;
csh handle = *p_handle;
csh handle = *p_handle;
tricore = &(ins->detail->tricore);
tricore = &(ins->detail->tricore);
if (tricore->op_count)
add_str(&result, "\top_count: %u\n", tricore->op_count);
if (tricore->op_count)
add_str(&result, "\top_count: %u\n", tricore->op_count);
for (i = 0; i < tricore->op_count; i++) {
cs_tricore_op *op = &(tricore->operands[i]);
switch ((int)op->type) {
default:
break;
case TRICORE_OP_REG:
add_str(&result, "\t\toperands[%u].type: REG = %s\n", i,
cs_reg_name(handle, op->reg));
break;
case TRICORE_OP_IMM:
add_str(&result, "\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm);
break;
case TRICORE_OP_MEM:
add_str(&result, "\t\toperands[%u].type: MEM\n", i);
if (op->mem.base != TriCore_REG_INVALID)
add_str(&result, "\t\t\toperands[%u].mem.base: REG = %s\n", i,
cs_reg_name(handle, op->mem.base));
if (op->mem.disp != 0)
add_str(&result, "\t\t\toperands[%u].mem.disp: 0x%x\n", i,
op->mem.disp);
break;
}
for (i = 0; i < tricore->op_count; i++) {
cs_tricore_op *op = &(tricore->operands[i]);
switch ((int)op->type) {
default:
break;
case TRICORE_OP_REG:
add_str(&result, "\t\toperands[%u].type: REG = %s\n", i,
cs_reg_name(handle, op->reg));
break;
case TRICORE_OP_IMM:
add_str(&result, "\t\toperands[%u].type: IMM = 0x%x\n",
i, op->imm);
break;
case TRICORE_OP_MEM:
add_str(&result, "\t\toperands[%u].type: MEM\n", i);
if (op->mem.base != TriCore_REG_INVALID)
add_str(&result,
"\t\t\toperands[%u].mem.base: REG = %s\n",
i, cs_reg_name(handle, op->mem.base));
if (op->mem.disp != 0)
add_str(&result,
"\t\t\toperands[%u].mem.disp: 0x%x\n",
i, op->mem.disp);
break;
}
// Print out all registers accessed by this instruction (either implicit or
// explicit)
if (!cs_regs_access(handle, ins, regs_read, &regs_read_count, regs_write,
&regs_write_count)) {
if (regs_read_count) {
add_str(&result, "\tRegisters read:");
for (i = 0; i < regs_read_count; i++) {
add_str(&result, " %s", cs_reg_name(handle, regs_read[i]));
// Print out all registers accessed by this instruction (either implicit or
// explicit)
if (!cs_regs_access(handle, ins, regs_read, &regs_read_count,
regs_write, &regs_write_count)) {
if (regs_read_count) {
add_str(&result, "\tRegisters read:");
for (i = 0; i < regs_read_count; i++) {
add_str(&result, " %s",
cs_reg_name(handle,
regs_read[i]));
}
add_str(&result, "\n");
}
if (regs_write_count) {
add_str(&result, "\tRegisters modified:");
for (i = 0; i < regs_write_count; i++) {
add_str(&result, " %s",
cs_reg_name(handle,
regs_write[i]));
}
add_str(&result, "\n");
}
}
}
add_str(&result, "\n");
}
if (regs_write_count) {
add_str(&result, "\tRegisters modified:");
for (i = 0; i < regs_write_count; i++) {
add_str(&result, " %s", cs_reg_name(handle, regs_write[i]));
}
add_str(&result, "\n");
}
}
}
return result;
return result;
}

66
tests/test_tricore.c
View File

@ -43,24 +43,27 @@ static void print_insn_detail(cs_insn *ins)
for (i = 0; i < tricore->op_count; i++) {
cs_tricore_op *op = &(tricore->operands[i]);
switch((int)op->type) {
default:
break;
case TRICORE_OP_REG:
printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
break;
case TRICORE_OP_IMM:
printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm);
break;
case TRICORE_OP_MEM:
printf("\t\toperands[%u].type: MEM\n", i);
if (op->mem.base != TriCore_REG_INVALID)
printf("\t\t\toperands[%u].mem.base: REG = %s\n",
i, cs_reg_name(handle, op->mem.base));
if (op->mem.disp != 0)
printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp);
switch ((int)op->type) {
default:
break;
case TRICORE_OP_REG:
printf("\t\toperands[%u].type: REG = %s\n", i,
cs_reg_name(handle, op->reg));
break;
case TRICORE_OP_IMM:
printf("\t\toperands[%u].type: IMM = 0x%x\n", i,
op->imm);
break;
case TRICORE_OP_MEM:
printf("\t\toperands[%u].type: MEM\n", i);
if (op->mem.base != TriCore_REG_INVALID)
printf("\t\t\toperands[%u].mem.base: REG = %s\n",
i, cs_reg_name(handle, op->mem.base));
if (op->mem.disp != 0)
printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i,
op->mem.disp);
break;
break;
}
}
@ -70,13 +73,14 @@ static void print_insn_detail(cs_insn *ins)
static void test()
{
//#define TRICORE_CODE "\x16\x01\x20\x01\x1d\x00\x02\x00\x8f\x70\x00\x11\x40\xae\x89\xee\x04\x09\x42\xf2\xe2\xf2\xc2\x11\x19\xff\xc0\x70\x19\xff\x20\x10"
#define TRICORE_CODE "\x09\xcf\xbc\xf5\x09\xf4\x01\x00\x89\xfb\x8f\x74\x89\xfe\x48\x01\x29\x00\x19\x25\x29\x03\x09\xf4\x85\xf9\x68\x0f\x16\x01"
#define TRICORE_CODE \
"\x09\xcf\xbc\xf5\x09\xf4\x01\x00\x89\xfb\x8f\x74\x89\xfe\x48\x01\x29\x00\x19\x25\x29\x03\x09\xf4\x85\xf9\x68\x0f\x16\x01"
struct platform platforms[] = {
{
CS_ARCH_TRICORE,
CS_MODE_TRICORE_162,
(unsigned char*)TRICORE_CODE,
(unsigned char *)TRICORE_CODE,
sizeof(TRICORE_CODE) - 1,
"TriCore",
},
@ -87,36 +91,44 @@ static void test()
int i;
size_t count;
for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
for (i = 0; i < sizeof(platforms) / sizeof(platforms[0]); i++) {
cs_err err =
cs_open(platforms[i].arch, platforms[i].mode, &handle);
if (err) {
printf("Failed on cs_open() with error returned: %u\n", err);
printf("Failed on cs_open() with error returned: %u\n",
err);
continue;
}
cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
count = cs_disasm(handle, platforms[i].code, platforms[i].size,
address, 0, &insn);
if (count) {
size_t j;
printf("****************\n");
printf("Platform: %s\n", platforms[i].comment);
print_string_hex("Code:", platforms[i].code, platforms[i].size);
print_string_hex("Code:", platforms[i].code,
platforms[i].size);
printf("Disasm:\n");
for (j = 0; j < count; j++) {
printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
printf("0x%" PRIx64 ":\t%s\t%s\n",
insn[j].address, insn[j].mnemonic,
insn[j].op_str);
print_insn_detail(&insn[j]);
}
printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size);
printf("0x%" PRIx64 ":\n",
insn[j - 1].address + insn[j - 1].size);
// free memory allocated by cs_disasm()
cs_free(insn, count);
} else {
printf("****************\n");
printf("Platform: %s\n", platforms[i].comment);
print_string_hex("Code:", platforms[i].code, platforms[i].size);
print_string_hex("Code:", platforms[i].code,
platforms[i].size);
printf("ERROR: Failed to disasm given code!\n");
}