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Format all .(c|h) code

This commit is contained in:
billow 2023-04-20 21:55:37 +08:00
parent 2919f94530
commit 2785d31399
10 changed files with 840 additions and 658 deletions
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415
arch/TriCore/TriCoreDisassembler.c
View File

@ -26,7 +26,9 @@
#include "../../MCDisassembler.h"
#include "../../MathExtras.h"
static bool readInstruction16(const uint8_t *code, size_t code_len, uint16_t *insn) {
static bool readInstruction16(const uint8_t *code, size_t code_len,
uint16_t *insn)
{
if (code_len < 2)
// insufficient data
return false;
@ -36,17 +38,21 @@ static bool readInstruction16(const uint8_t *code, size_t code_len, uint16_t *in
return true;
}
static bool readInstruction32(const uint8_t *code, size_t code_len, uint32_t *insn) {
static bool readInstruction32(const uint8_t *code, size_t code_len,
uint32_t *insn)
{
if (code_len < 4)
// insufficient data
return false;
// Encoded as a little-endian 32-bit word in the stream.
*insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) | (code[3] << 24);
*insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) |
(code[3] << 24);
return true;
}
static unsigned getReg(MCRegisterInfo *MRI, unsigned RC, unsigned RegNo) {
static unsigned getReg(MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
{
const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC);
return rc->RegsBegin[RegNo];
}
@ -56,8 +62,7 @@ static unsigned getReg(MCRegisterInfo *MRI, unsigned RC, unsigned RegNo) {
if (status != MCDisassembler_Success) \
return status;
#define decodeImm(x) \
MCOperand_CreateImm0(Inst, (x));
#define decodeImm(x) MCOperand_CreateImm0(Inst, (x));
static DecodeStatus DecodeSBInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder);
@ -107,59 +112,81 @@ static DecodeStatus DecodeRR2Instruction(MCInst *Inst, unsigned Insn,
static DecodeStatus DecodeRRPWInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeSLRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeSLRInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeSLROInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeSLROInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeSROInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeSROInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeSRRSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeSRRSInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeSBCInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeSBCInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeSBRNInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeSBRNInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeSSRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeSSRInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeSSROInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeSSROInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeSYSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeSYSInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeRRR2Instruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeRRR2Instruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeRRR1Instruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeRRR1Instruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeBITInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeBITInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeRR1Instruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeRR1Instruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeRCRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeRCRInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeRRRWInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeRRRWInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeRCRRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeRCRRInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeRRRRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeRRRRInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeBRRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeBRRInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeBRCInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeBRCInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeRRRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeRRRInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeABSBInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeABSBInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeRCRWInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeBRNInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeRCRWInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeBRNInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder);
#define GET_SUBTARGETINFO_ENUM
#include "TriCoreGenSubtargetInfo.inc"
bool TriCore_getFeatureBits(unsigned int mode, unsigned int feature) {
bool TriCore_getFeatureBits(unsigned int mode, unsigned int feature)
{
switch (mode) {
case CS_MODE_TRICORE_110: {
return feature == TriCore_HasV110Ops;
@ -187,7 +214,6 @@ bool TriCore_getFeatureBits(unsigned int mode, unsigned int feature) {
}
}
#include "TriCoreGenDisassemblerTables.inc"
#define GET_REGINFO_ENUM
@ -195,8 +221,10 @@ bool TriCore_getFeatureBits(unsigned int mode, unsigned int feature) {
#include "TriCoreGenRegisterInfo.inc"
static DecodeStatus
DecodeRegisterClass(MCInst *Inst, unsigned RegNo, const MCOperandInfo *MCOI, void *Decoder) {
static DecodeStatus DecodeRegisterClass(MCInst *Inst, unsigned RegNo,
const MCOperandInfo *MCOI,
void *Decoder)
{
unsigned Reg;
unsigned RegHalfNo = RegNo / 2;
@ -224,7 +252,8 @@ DecodeRegisterClass(MCInst *Inst, unsigned RegNo, const MCOperandInfo *MCOI, voi
#include "TriCoreGenInstrInfo.inc"
static DecodeStatus DecodeSBInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder) {
uint64_t Address, void *Decoder)
{
unsigned disp8 = fieldFromInstruction_2(Insn, 8, 8);
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
@ -238,7 +267,8 @@ static DecodeStatus DecodeSBInstruction(MCInst *Inst, unsigned Insn,
}
static DecodeStatus DecodeSBRInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder) {
uint64_t Address, void *Decoder)
{
DecodeStatus status;
unsigned s2 = fieldFromInstruction_2(Insn, 12, 4);
unsigned disp4 = fieldFromInstruction_2(Insn, 8, 4);
@ -259,7 +289,8 @@ static DecodeStatus DecodeSBRInstruction(MCInst *Inst, unsigned Insn,
}
static DecodeStatus DecodeSCInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder) {
uint64_t Address, void *Decoder)
{
unsigned const8 = fieldFromInstruction_2(Insn, 8, 8);
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
@ -273,7 +304,8 @@ static DecodeStatus DecodeSCInstruction(MCInst *Inst, unsigned Insn,
}
static DecodeStatus DecodeSRInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder) {
uint64_t Address, void *Decoder)
{
DecodeStatus status;
unsigned s1_d = fieldFromInstruction_2(Insn, 8, 4);
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
@ -283,13 +315,15 @@ static DecodeStatus DecodeSRInstruction(MCInst *Inst, unsigned Insn,
const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
if (desc->NumOperands > 0) {
status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0], Decoder);
status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0],
Decoder);
if (status != MCDisassembler_Success)
return status;
}
if (desc->NumOperands > 1) {
status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[1], Decoder);
status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[1],
Decoder);
if (status != MCDisassembler_Success)
return status;
}
@ -298,7 +332,8 @@ static DecodeStatus DecodeSRInstruction(MCInst *Inst, unsigned Insn,
}
static DecodeStatus DecodeSRCInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder) {
uint64_t Address, void *Decoder)
{
DecodeStatus status;
unsigned const4 = fieldFromInstruction_2(Insn, 12, 4);
unsigned s1_d = fieldFromInstruction_2(Insn, 8, 4);
@ -321,7 +356,8 @@ static DecodeStatus DecodeSRCInstruction(MCInst *Inst, unsigned Insn,
}
static DecodeStatus DecodeSRRInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder) {
uint64_t Address, void *Decoder)
{
DecodeStatus status;
unsigned s2 = fieldFromInstruction_2(Insn, 12, 4);
unsigned s1_d = fieldFromInstruction_2(Insn, 8, 4);
@ -336,7 +372,6 @@ static DecodeStatus DecodeSRRInstruction(MCInst *Inst, unsigned Insn,
if (status != MCDisassembler_Success)
return status;
// Decode s2.
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1], Decoder);
if (status != MCDisassembler_Success)
@ -346,15 +381,15 @@ static DecodeStatus DecodeSRRInstruction(MCInst *Inst, unsigned Insn,
}
static DecodeStatus DecodeABSInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder) {
uint64_t Address, void *Decoder)
{
DecodeStatus status;
unsigned off18_0 = fieldFromInstruction_4(Insn, 16, 6);
unsigned off18_1 = fieldFromInstruction_4(Insn, 28, 4);
unsigned off18_2 = fieldFromInstruction_4(Insn, 22, 4);
unsigned off18_3 = fieldFromInstruction_4(Insn, 12, 4);
unsigned off18 = (off18_0 << 0) | (off18_1 << 6) |
(off18_2 << 10) | (off18_3 << 14);
unsigned off18 = (off18_0 << 0) | (off18_1 << 6) | (off18_2 << 10) |
(off18_3 << 14);
unsigned s1_d = fieldFromInstruction_4(Insn, 8, 4);
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
@ -366,14 +401,16 @@ static DecodeStatus DecodeABSInstruction(MCInst *Inst, unsigned Insn,
if (desc->NumOperands > 1) {
if (desc->OpInfo[0].OperandType == MCOI_OPERAND_REGISTER) {
status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0], Decoder);
status = DecodeRegisterClass(Inst, s1_d,
&desc->OpInfo[0], Decoder);
if (status != MCDisassembler_Success)
return status;
MCOperand_CreateImm0(Inst, off18);
} else {
MCOperand_CreateImm0(Inst, off18);
status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0], Decoder);
status = DecodeRegisterClass(Inst, s1_d,
&desc->OpInfo[0], Decoder);
if (status != MCDisassembler_Success)
return status;
}
@ -385,7 +422,8 @@ static DecodeStatus DecodeABSInstruction(MCInst *Inst, unsigned Insn,
}
static DecodeStatus DecodeBInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder) {
uint64_t Address, void *Decoder)
{
unsigned disp24_0 = fieldFromInstruction_4(Insn, 16, 16);
unsigned disp24_1 = fieldFromInstruction_4(Insn, 8, 8);
unsigned disp24 = (disp24_0 << 0) | (disp24_1 << 16);
@ -402,7 +440,8 @@ static DecodeStatus DecodeBInstruction(MCInst *Inst, unsigned Insn,
}
static DecodeStatus DecodeBOInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder) {
uint64_t Address, void *Decoder)
{
DecodeStatus status;
unsigned off10_0 = fieldFromInstruction_4(Insn, 16, 6);
unsigned off10_1 = fieldFromInstruction_4(Insn, 28, 4);
@ -423,12 +462,14 @@ static DecodeStatus DecodeBOInstruction(MCInst *Inst, unsigned Insn,
}
if (desc->NumOperands == 2) {
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0], Decoder);
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0],
Decoder);
if (status != MCDisassembler_Success)
return status;
if (desc->OpInfo[1].OperandType == MCOI_OPERAND_REGISTER) {
return DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[1], Decoder);
return DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[1],
Decoder);
} else {
MCOperand_CreateImm0(Inst, off10);
}
@ -436,11 +477,13 @@ static DecodeStatus DecodeBOInstruction(MCInst *Inst, unsigned Insn,
}
if (desc->NumOperands > 2) {
status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0], Decoder);
status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0],
Decoder);
if (status != MCDisassembler_Success)
return status;
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1], Decoder);
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1],
Decoder);
if (status != MCDisassembler_Success)
return status;
@ -451,7 +494,8 @@ static DecodeStatus DecodeBOInstruction(MCInst *Inst, unsigned Insn,
}
static DecodeStatus DecodeBOLInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder) {
uint64_t Address, void *Decoder)
{
DecodeStatus status;
unsigned off16_0 = fieldFromInstruction_4(Insn, 16, 6);
unsigned off16_1 = fieldFromInstruction_4(Insn, 22, 6);
@ -476,12 +520,14 @@ static DecodeStatus DecodeBOLInstruction(MCInst *Inst, unsigned Insn,
case TriCore_LD_W_bol:
case TriCore_LEA_bol: {
// Decode s1_d.
status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0], Decoder);
status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0],
Decoder);
if (status != MCDisassembler_Success)
return status;
// Decode s2.
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1], Decoder);
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1],
Decoder);
if (status != MCDisassembler_Success)
return status;
break;
@ -491,12 +537,14 @@ static DecodeStatus DecodeBOLInstruction(MCInst *Inst, unsigned Insn,
case TriCore_ST_H_bol:
case TriCore_ST_W_bol: {
// Decode s2.
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0], Decoder);
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0],
Decoder);
if (status != MCDisassembler_Success)
return status;
// Decode s1_d.
status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[1], Decoder);
status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[1],
Decoder);
if (status != MCDisassembler_Success)
return status;
break;
@ -512,7 +560,8 @@ static DecodeStatus DecodeBOLInstruction(MCInst *Inst, unsigned Insn,
}
static DecodeStatus DecodeRCInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder) {
uint64_t Address, void *Decoder)
{
DecodeStatus status;
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
unsigned const9 = fieldFromInstruction_4(Insn, 12, 9);
@ -526,12 +575,14 @@ static DecodeStatus DecodeRCInstruction(MCInst *Inst, unsigned Insn,
const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
if (desc->NumOperands > 1) {
// Decode d.
status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder);
status =
DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder);
if (status != MCDisassembler_Success)
return status;
// Decode s1.
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], Decoder);
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1],
Decoder);
if (status != MCDisassembler_Success)
return status;
}
@ -543,7 +594,8 @@ static DecodeStatus DecodeRCInstruction(MCInst *Inst, unsigned Insn,
}
static DecodeStatus DecodeRCPWInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder) {
uint64_t Address, void *Decoder)
{
DecodeStatus status;
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
unsigned pos = fieldFromInstruction_4(Insn, 23, 5);
@ -580,7 +632,8 @@ static DecodeStatus DecodeRCPWInstruction(MCInst *Inst, unsigned Insn,
}
static DecodeStatus DecodeRLCInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder) {
uint64_t Address, void *Decoder)
{
DecodeStatus status;
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
unsigned const16 = fieldFromInstruction_4(Insn, 12, 16);
@ -593,11 +646,13 @@ static DecodeStatus DecodeRLCInstruction(MCInst *Inst, unsigned Insn,
const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
if (desc->NumOperands == 3) {
status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder);
status =
DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder);
if (status != MCDisassembler_Success)
return status;
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], Decoder);
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1],
Decoder);
if (status != MCDisassembler_Success)
return status;
@ -607,14 +662,16 @@ static DecodeStatus DecodeRLCInstruction(MCInst *Inst, unsigned Insn,
}
if (desc->OpInfo[0].OperandType == MCOI_OPERAND_REGISTER) {
status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder);
status =
DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder);
if (status != MCDisassembler_Success)
return status;
MCOperand_CreateImm0(Inst, const16);
} else {
MCOperand_CreateImm0(Inst, const16);
status = DecodeRegisterClass(Inst, d, &desc->OpInfo[1], Decoder);
status =
DecodeRegisterClass(Inst, d, &desc->OpInfo[1], Decoder);
if (status != MCDisassembler_Success)
return status;
}
@ -622,7 +679,8 @@ static DecodeStatus DecodeRLCInstruction(MCInst *Inst, unsigned Insn,
}
static DecodeStatus DecodeRRInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder) {
uint64_t Address, void *Decoder)
{
DecodeStatus status;
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
unsigned n = fieldFromInstruction_4(Insn, 16, 2);
@ -641,10 +699,12 @@ static DecodeStatus DecodeRRInstruction(MCInst *Inst, unsigned Insn,
if (desc->OpInfo[0].OperandType == MCOI_OPERAND_REGISTER) {
switch (MCInst_getOpcode(Inst)) {
case TriCore_CALLI_rr_v110: {
return DecodeRegisterClass(Inst, s2, &desc->OpInfo[0], Decoder);
return DecodeRegisterClass(
Inst, s2, &desc->OpInfo[0], Decoder);
}
default: {
return DecodeRegisterClass(Inst, s1, &desc->OpInfo[0], Decoder);
return DecodeRegisterClass(
Inst, s1, &desc->OpInfo[0], Decoder);
}
}
}
@ -653,30 +713,36 @@ static DecodeStatus DecodeRRInstruction(MCInst *Inst, unsigned Insn,
if (desc->NumOperands > 0) {
// Decode d.
status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder);
status =
DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder);
if (status != MCDisassembler_Success)
return status;
}
if (desc->NumOperands > 1) {
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], Decoder);
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1],
Decoder);
if (status != MCDisassembler_Success)
return status;
}
if (desc->NumOperands > 2) {
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[2], Decoder);
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[2],
Decoder);
if (status != MCDisassembler_Success)
return status;
}
if (desc->NumOperands > 3) { MCOperand_CreateImm0(Inst, n); }
if (desc->NumOperands > 3) {
MCOperand_CreateImm0(Inst, n);
}
return MCDisassembler_Success;
}
static DecodeStatus DecodeRR2Instruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder) {
uint64_t Address, void *Decoder)
{
DecodeStatus status;
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
@ -707,7 +773,8 @@ static DecodeStatus DecodeRR2Instruction(MCInst *Inst, unsigned Insn,
}
static DecodeStatus DecodeRRPWInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder) {
uint64_t Address, void *Decoder)
{
DecodeStatus status;
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
unsigned pos = fieldFromInstruction_4(Insn, 23, 5);
@ -721,16 +788,15 @@ static DecodeStatus DecodeRRPWInstruction(MCInst *Inst, unsigned Insn,
return MCDisassembler_Fail;
const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
tryDecodeReg(0, d)
tryDecodeReg(1, s1)
tryDecodeReg(2, s2)
decodeImm(pos)
decodeImm(width)
tryDecodeReg(0, d) tryDecodeReg(1, s1) tryDecodeReg(2, s2)
decodeImm(pos) decodeImm(width)
return MCDisassembler_Success;
}
static DecodeStatus DecodeSLRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) {
static DecodeStatus DecodeSLRInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder)
{
DecodeStatus status = MCDisassembler_Fail;
unsigned d = fieldFromInstruction_2(Insn, 8, 4);
unsigned s2 = fieldFromInstruction_2(Insn, 12, 4);
@ -752,7 +818,9 @@ static DecodeStatus DecodeSLRInstruction(MCInst *Inst, unsigned Insn, uint64_t A
return MCDisassembler_Success;
}
static DecodeStatus DecodeSLROInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) {
static DecodeStatus DecodeSLROInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder)
{
DecodeStatus status = MCDisassembler_Fail;
unsigned d = fieldFromInstruction_2(Insn, 8, 4);
unsigned off4 = fieldFromInstruction_2(Insn, 12, 4);
@ -772,7 +840,9 @@ static DecodeStatus DecodeSLROInstruction(MCInst *Inst, unsigned Insn, uint64_t
return MCDisassembler_Success;
}
static DecodeStatus DecodeSROInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) {
static DecodeStatus DecodeSROInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder)
{
DecodeStatus status = MCDisassembler_Fail;
unsigned off4 = fieldFromInstruction_2(Insn, 8, 4);
unsigned s2 = fieldFromInstruction_2(Insn, 12, 4);
@ -792,7 +862,9 @@ static DecodeStatus DecodeSROInstruction(MCInst *Inst, unsigned Insn, uint64_t A
return MCDisassembler_Success;
}
static DecodeStatus DecodeSRRSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) {
static DecodeStatus DecodeSRRSInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder)
{
DecodeStatus status = MCDisassembler_Fail;
unsigned n = fieldFromInstruction_2(Insn, 6, 2);
unsigned s1_d = fieldFromInstruction_2(Insn, 8, 4);
@ -819,7 +891,9 @@ static DecodeStatus DecodeSRRSInstruction(MCInst *Inst, unsigned Insn, uint64_t
return MCDisassembler_Success;
}
static DecodeStatus DecodeSBCInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) {
static DecodeStatus DecodeSBCInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder)
{
unsigned disp4 = fieldFromInstruction_2(Insn, 8, 4);
unsigned const4 = fieldFromInstruction_2(Insn, 12, 4);
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
@ -840,7 +914,9 @@ static DecodeStatus DecodeSBCInstruction(MCInst *Inst, unsigned Insn, uint64_t A
return MCDisassembler_Success;
}
static DecodeStatus DecodeSBRNInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) {
static DecodeStatus DecodeSBRNInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder)
{
unsigned disp4 = fieldFromInstruction_2(Insn, 8, 4);
unsigned n = fieldFromInstruction_2(Insn, 12, 4);
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
@ -855,7 +931,9 @@ static DecodeStatus DecodeSBRNInstruction(MCInst *Inst, unsigned Insn, uint64_t
return MCDisassembler_Success;
}
static DecodeStatus DecodeSSRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) {
static DecodeStatus DecodeSSRInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder)
{
DecodeStatus status = MCDisassembler_Fail;
unsigned s1 = fieldFromInstruction_2(Insn, 8, 4);
unsigned s2 = fieldFromInstruction_2(Insn, 12, 4);
@ -878,7 +956,9 @@ static DecodeStatus DecodeSSRInstruction(MCInst *Inst, unsigned Insn, uint64_t A
return MCDisassembler_Success;
}
static DecodeStatus DecodeSSROInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) {
static DecodeStatus DecodeSSROInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder)
{
DecodeStatus status = MCDisassembler_Fail;
unsigned s1 = fieldFromInstruction_2(Insn, 8, 4);
unsigned off4 = fieldFromInstruction_2(Insn, 12, 4);
@ -899,7 +979,9 @@ static DecodeStatus DecodeSSROInstruction(MCInst *Inst, unsigned Insn, uint64_t
/// 32-bit Opcode Format
static DecodeStatus DecodeSYSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) {
static DecodeStatus DecodeSYSInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder)
{
DecodeStatus status = MCDisassembler_Fail;
unsigned s1_d = fieldFromInstruction_4(Insn, 8, 4);
@ -909,7 +991,8 @@ static DecodeStatus DecodeSYSInstruction(MCInst *Inst, unsigned Insn, uint64_t A
const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
if (desc->NumOperands > 0) {
status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0], Decoder);
status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0],
Decoder);
if (status != MCDisassembler_Success)
return status;
}
@ -917,7 +1000,9 @@ static DecodeStatus DecodeSYSInstruction(MCInst *Inst, unsigned Insn, uint64_t A
return MCDisassembler_Success;
}
static DecodeStatus DecodeRRR2Instruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) {
static DecodeStatus DecodeRRR2Instruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder)
{
DecodeStatus status = MCDisassembler_Fail;
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
@ -951,7 +1036,9 @@ static DecodeStatus DecodeRRR2Instruction(MCInst *Inst, unsigned Insn, uint64_t
return MCDisassembler_Success;
}
static DecodeStatus DecodeRRR1Instruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) {
static DecodeStatus DecodeRRR1Instruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder)
{
DecodeStatus status = MCDisassembler_Fail;
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
@ -989,7 +1076,9 @@ static DecodeStatus DecodeRRR1Instruction(MCInst *Inst, unsigned Insn, uint64_t
return MCDisassembler_Success;
}
static DecodeStatus DecodeBITInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) {
static DecodeStatus DecodeBITInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder)
{
DecodeStatus status = MCDisassembler_Fail;
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
@ -1025,7 +1114,9 @@ static DecodeStatus DecodeBITInstruction(MCInst *Inst, unsigned Insn, uint64_t A
return MCDisassembler_Success;
}
static DecodeStatus DecodeRR1Instruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) {
static DecodeStatus DecodeRR1Instruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder)
{
DecodeStatus status = MCDisassembler_Fail;
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
@ -1057,7 +1148,9 @@ static DecodeStatus DecodeRR1Instruction(MCInst *Inst, unsigned Insn, uint64_t A
return MCDisassembler_Success;
}
static DecodeStatus DecodeRCRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) {
static DecodeStatus DecodeRCRInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder)
{
DecodeStatus status = MCDisassembler_Fail;
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
unsigned const9 = fieldFromInstruction_4(Insn, 12, 9);
@ -1089,7 +1182,9 @@ static DecodeStatus DecodeRCRInstruction(MCInst *Inst, unsigned Insn, uint64_t A
return MCDisassembler_Success;
}
static DecodeStatus DecodeRRRWInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) {
static DecodeStatus DecodeRRRWInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder)
{
DecodeStatus status = MCDisassembler_Fail;
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
@ -1127,7 +1222,9 @@ static DecodeStatus DecodeRRRWInstruction(MCInst *Inst, unsigned Insn, uint64_t
return MCDisassembler_Success;
}
static DecodeStatus DecodeRCRRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) {
static DecodeStatus DecodeRCRRInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder)
{
DecodeStatus status = MCDisassembler_Fail;
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
unsigned const4 = fieldFromInstruction_4(Insn, 12, 4);
@ -1138,7 +1235,6 @@ static DecodeStatus DecodeRCRRInstruction(MCInst *Inst, unsigned Insn, uint64_t
if (!is32Bit) // This instruction is 32-bit
return MCDisassembler_Fail;
const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder);
if (status != MCDisassembler_Success)
@ -1160,7 +1256,9 @@ static DecodeStatus DecodeRCRRInstruction(MCInst *Inst, unsigned Insn, uint64_t
return MCDisassembler_Success;
}
static DecodeStatus DecodeRRRRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) {
static DecodeStatus DecodeRRRRInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder)
{
DecodeStatus status = MCDisassembler_Fail;
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
@ -1197,7 +1295,9 @@ static DecodeStatus DecodeRRRRInstruction(MCInst *Inst, unsigned Insn, uint64_t
return MCDisassembler_Success;
}
static DecodeStatus DecodeBRRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) {
static DecodeStatus DecodeBRRInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder)
{
DecodeStatus status = MCDisassembler_Fail;
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
@ -1209,7 +1309,8 @@ static DecodeStatus DecodeBRRInstruction(MCInst *Inst, unsigned Insn, uint64_t A
const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
if (MCInst_getOpcode(Inst) == TriCore_LOOP_brr) {
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0], Decoder);
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0],
Decoder);
if (status != MCDisassembler_Success)
return status;
@ -1218,12 +1319,14 @@ static DecodeStatus DecodeBRRInstruction(MCInst *Inst, unsigned Insn, uint64_t A
}
if (desc->NumOperands >= 2) {
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[0], Decoder);
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[0],
Decoder);
if (status != MCDisassembler_Success)
return status;
if (desc->NumOperands >= 3) {
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1], Decoder);
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1],
Decoder);
if (status != MCDisassembler_Success)
return status;
}
@ -1235,7 +1338,9 @@ static DecodeStatus DecodeBRRInstruction(MCInst *Inst, unsigned Insn, uint64_t A
return MCDisassembler_Success;
}
static DecodeStatus DecodeBRCInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) {
static DecodeStatus DecodeBRCInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder)
{
DecodeStatus status = MCDisassembler_Fail;
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
unsigned const4 = fieldFromInstruction_4(Insn, 12, 4);
@ -1259,7 +1364,9 @@ static DecodeStatus DecodeBRCInstruction(MCInst *Inst, unsigned Insn, uint64_t A
return MCDisassembler_Success;
}
static DecodeStatus DecodeRRRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) {
static DecodeStatus DecodeRRRInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder)
{
DecodeStatus status = MCDisassembler_Fail;
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
@ -1294,7 +1401,9 @@ static DecodeStatus DecodeRRRInstruction(MCInst *Inst, unsigned Insn, uint64_t A
return MCDisassembler_Success;
}
static DecodeStatus DecodeABSBInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) {
static DecodeStatus DecodeABSBInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder)
{
unsigned bpos3 = fieldFromInstruction_4(Insn, 8, 3);
unsigned b = fieldFromInstruction_4(Insn, 12, 1);
@ -1309,14 +1418,14 @@ static DecodeStatus DecodeABSBInstruction(MCInst *Inst, unsigned Insn, uint64_t
if (!is32Bit) // This instruction is 32-bit
return MCDisassembler_Fail;
decodeImm(off18)
decodeImm(bpos3)
decodeImm(b)
decodeImm(off18) decodeImm(bpos3) decodeImm(b)
return MCDisassembler_Success;
}
static DecodeStatus DecodeRCRWInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) {
static DecodeStatus DecodeRCRWInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder)
{
DecodeStatus status = MCDisassembler_Fail;
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
unsigned const4 = fieldFromInstruction_4(Insn, 12, 4);
@ -1329,16 +1438,15 @@ static DecodeStatus DecodeRCRWInstruction(MCInst *Inst, unsigned Insn, uint64_t
return MCDisassembler_Fail;
const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
tryDecodeReg(0, d)
tryDecodeReg(1, s1)
tryDecodeReg(2, s3)
decodeImm(const4)
decodeImm(width)
tryDecodeReg(0, d) tryDecodeReg(1, s1) tryDecodeReg(2, s3)
decodeImm(const4) decodeImm(width)
return MCDisassembler_Success;
}
static DecodeStatus DecodeBRNInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) {
static DecodeStatus DecodeBRNInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder)
{
DecodeStatus status = MCDisassembler_Fail;
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
@ -1370,16 +1478,19 @@ static DecodeStatus DecodeBRNInstruction(MCInst *Inst, unsigned Insn, uint64_t A
#include "TriCoreGenInstrInfo.inc"
static inline bool tryGetInstruction16(const uint8_t *code, size_t code_len, MCInst *MI,
uint16_t *size, uint64_t address, void *info,
const uint8_t *decoderTable16) {
static inline bool tryGetInstruction16(const uint8_t *code, size_t code_len,
MCInst *MI, uint16_t *size,
uint64_t address, void *info,
const uint8_t *decoderTable16)
{
uint16_t insn16;
DecodeStatus Result;
if (!readInstruction16(code, code_len, &insn16)) {
return false;
}
// Calling the auto-generated decoder function.
Result = decodeInstruction_2(decoderTable16, MI, insn16, address, info, 0);
Result = decodeInstruction_2(decoderTable16, MI, insn16, address, info,
0);
if (Result != MCDisassembler_Fail) {
*size = 2;
return true;
@ -1387,16 +1498,19 @@ static inline bool tryGetInstruction16(const uint8_t *code, size_t code_len, MCI
return false;
}
static inline bool tryGetInstruction32(const uint8_t *code, size_t code_len, MCInst *MI,
uint16_t *size, uint64_t address, void *info,
const uint8_t *decoderTable32) {
static inline bool tryGetInstruction32(const uint8_t *code, size_t code_len,
MCInst *MI, uint16_t *size,
uint64_t address, void *info,
const uint8_t *decoderTable32)
{
uint32_t insn32;
DecodeStatus Result;
if (!readInstruction32(code, code_len, &insn32)) {
return false;
}
// Calling the auto-generated decoder function.
Result = decodeInstruction_4(decoderTable32, MI, insn32, address, info, 0);
Result = decodeInstruction_4(decoderTable32, MI, insn32, address, info,
0);
if (Result != MCDisassembler_Fail) {
*size = 4;
return true;
@ -1404,10 +1518,10 @@ static inline bool tryGetInstruction32(const uint8_t *code, size_t code_len, MCI
return false;
}
bool TriCore_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI,
uint16_t *size, uint64_t address, void *info) {
bool TriCore_getInstruction(csh ud, const uint8_t *code, size_t code_len,
MCInst *MI, uint16_t *size, uint64_t address,
void *info)
{
if (!ud) {
return false;
}
@ -1419,21 +1533,26 @@ bool TriCore_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst
switch (cs->mode) {
case CS_MODE_TRICORE_110: {
if (tryGetInstruction16(code, code_len, MI, size, address, info, DecoderTablev11016) ||
tryGetInstruction32(code, code_len, MI, size, address, info, DecoderTablev11032)) {
if (tryGetInstruction16(code, code_len, MI, size, address, info,
DecoderTablev11016) ||
tryGetInstruction32(code, code_len, MI, size, address, info,
DecoderTablev11032)) {
return true;
}
break;
}
case CS_MODE_TRICORE_161: {
if (tryGetInstruction32(code, code_len, MI, size, address, info, DecoderTablev16132)) {
if (tryGetInstruction32(code, code_len, MI, size, address, info,
DecoderTablev16132)) {
return true;
}
break;
}
case CS_MODE_TRICORE_162: {
if (tryGetInstruction16(code, code_len, MI, size, address, info, DecoderTablev16216) ||
tryGetInstruction32(code, code_len, MI, size, address, info, DecoderTablev16232)) {
if (tryGetInstruction16(code, code_len, MI, size, address, info,
DecoderTablev16216) ||
tryGetInstruction32(code, code_len, MI, size, address, info,
DecoderTablev16232)) {
return true;
}
break;
@ -1442,11 +1561,14 @@ bool TriCore_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst
break;
}
return tryGetInstruction16(code, code_len, MI, size, address, info, DecoderTable16) ||
tryGetInstruction32(code, code_len, MI, size, address, info, DecoderTable32);
return tryGetInstruction16(code, code_len, MI, size, address, info,
DecoderTable16) ||
tryGetInstruction32(code, code_len, MI, size, address, info,
DecoderTable32);
}
void TriCore_init(MCRegisterInfo *MRI) {
void TriCore_init(MCRegisterInfo *MRI)
{
/*
InitMCRegisterInfo(TriCoreRegDesc, 45, RA, PC,
TriCoreMCRegisterClasses, 4,
@ -1460,15 +1582,10 @@ void TriCore_init(MCRegisterInfo *MRI) {
TriCoreRegEncodingTable);
*/
MCRegisterInfo_InitMCRegisterInfo(MRI, TriCoreRegDesc, ARR_SIZE(TriCoreRegDesc),
0, 0,
TriCoreMCRegisterClasses, ARR_SIZE(TriCoreMCRegisterClasses),
0, 0,
TriCoreRegDiffLists,
0,
TriCoreSubRegIdxLists, 1,
0);
MCRegisterInfo_InitMCRegisterInfo(
MRI, TriCoreRegDesc, ARR_SIZE(TriCoreRegDesc), 0, 0,
TriCoreMCRegisterClasses, ARR_SIZE(TriCoreMCRegisterClasses), 0,
0, TriCoreRegDiffLists, 0, TriCoreSubRegIdxLists, 1, 0);
}
#endif

4
arch/TriCore/TriCoreDisassembler.h
View File

@ -15,7 +15,7 @@
void TriCore_init(MCRegisterInfo *MRI);
bool TriCore_getInstruction(csh ud, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address, void *info);
MCInst *instr, uint16_t *size, uint64_t address,
void *info);
#endif

116
arch/TriCore/TriCoreInstPrinter.c
View File

@ -35,7 +35,8 @@ static void printInstruction(MCInst *, uint64_t, SStream *);
static void printOperand(MCInst *MI, int OpNum, SStream *O);
void TriCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) {
void TriCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
{
/*
if (((cs_struct *)ud)->detail != CS_OPT_ON)
return;
@ -54,29 +55,34 @@ static inline void fill_mem(cs_tricore *tc, uint8_t base, int32_t disp);
static bool fixup_op_mem(MCInst *pInst, unsigned int reg, int32_t disp);
static inline void fill_tricore_register(MCInst *MI, uint32_t reg) {
if (!(MI->csh->detail == CS_OPT_ON && MI->flat_insn->detail)) return;
static inline void fill_tricore_register(MCInst *MI, uint32_t reg)
{
if (!(MI->csh->detail == CS_OPT_ON && MI->flat_insn->detail))
return;
cs_tricore *tricore = &MI->flat_insn->detail->tricore;
tricore->operands[tricore->op_count]
.type = TRICORE_OP_REG;
tricore->operands[tricore->op_count]
.reg = reg;
tricore->operands[tricore->op_count].type = TRICORE_OP_REG;
tricore->operands[tricore->op_count].reg = reg;
tricore->op_count++;
}
static inline void fill_tricore_imm(MCInst *MI, int32_t imm) {
if (!(MI->csh->detail == CS_OPT_ON && MI->flat_insn->detail)) return;
static inline void fill_tricore_imm(MCInst *MI, int32_t imm)
{
if (!(MI->csh->detail == CS_OPT_ON && MI->flat_insn->detail))
return;
cs_tricore *tricore = &MI->flat_insn->detail->tricore;
if (tricore->op_count >= 1 && tricore->operands[tricore->op_count - 1].type == TRICORE_OP_REG &&
fixup_op_mem(MI, tricore->operands[tricore->op_count - 1].reg, imm)) { return; }
tricore->operands[tricore->op_count]
.type = TRICORE_OP_IMM;
tricore->operands[tricore->op_count]
.imm = imm;
if (tricore->op_count >= 1 &&
tricore->operands[tricore->op_count - 1].type == TRICORE_OP_REG &&
fixup_op_mem(MI, tricore->operands[tricore->op_count - 1].reg,
imm)) {
return;
}
tricore->operands[tricore->op_count].type = TRICORE_OP_IMM;
tricore->operands[tricore->op_count].imm = imm;
tricore->op_count++;
}
static bool fixup_op_mem(MCInst *pInst, unsigned int reg, int32_t disp) {
static bool fixup_op_mem(MCInst *pInst, unsigned int reg, int32_t disp)
{
switch (TriCore_map_insn_id(pInst->csh, pInst->Opcode)) {
case TriCore_INS_LDMST:
case TriCore_INS_LDLCX:
@ -146,14 +152,16 @@ static bool fixup_op_mem(MCInst *pInst, unsigned int reg, int32_t disp) {
return false;
}
static inline void fill_mem(cs_tricore *tc, uint8_t base, int32_t disp) {
static inline void fill_mem(cs_tricore *tc, uint8_t base, int32_t disp)
{
cs_tricore_op *op = &tc->operands[tc->op_count - 1];
op->type = TRICORE_OP_MEM;
op->mem.base = base;
op->mem.disp = disp;
}
static void printOperand(MCInst *MI, int OpNum, SStream *O) {
static void printOperand(MCInst *MI, int OpNum, SStream *O)
{
MCOperand *Op;
if (OpNum >= MI->size)
return;
@ -183,7 +191,8 @@ static void printOperand(MCInst *MI, int OpNum, SStream *O) {
}
}
static inline unsigned int get_msb(unsigned int value) {
static inline unsigned int get_msb(unsigned int value)
{
unsigned int msb = 0;
while (value > 0) {
value >>= 1; // Shift bits to the right
@ -192,21 +201,24 @@ static inline unsigned int get_msb(unsigned int value) {
return msb;
}
static inline int32_t sign_ext_n(int32_t imm, unsigned n) {
static inline int32_t sign_ext_n(int32_t imm, unsigned n)
{
n = get_msb(imm) > n ? get_msb(imm) : n;
int32_t mask = 1 << (n - 1);
int32_t sign_extended = (imm ^ mask) - mask;
return sign_extended;
}
static inline void SS_print_hex(SStream *O, int32_t imm) {
static inline void SS_print_hex(SStream *O, int32_t imm)
{
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%x", imm);
else
SStream_concat(O, "%u", imm);
}
static inline void SS_print_sign_hex(SStream *O, int32_t imm) {
static inline void SS_print_sign_hex(SStream *O, int32_t imm)
{
if (imm >= 0) {
SS_print_hex(O, imm);
} else {
@ -217,7 +229,8 @@ static inline void SS_print_sign_hex(SStream *O, int32_t imm) {
}
}
static void print_sign_ext(MCInst *MI, int OpNum, SStream *O, unsigned n) {
static void print_sign_ext(MCInst *MI, int OpNum, SStream *O, unsigned n)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
if (MCOperand_isImm(MO)) {
int32_t imm = (int32_t)MCOperand_getImm(MO);
@ -228,7 +241,8 @@ static void print_sign_ext(MCInst *MI, int OpNum, SStream *O, unsigned n) {
printOperand(MI, OpNum, O);
}
static void off4_fixup(MCInst *MI, uint64_t *off4) {
static void off4_fixup(MCInst *MI, uint64_t *off4)
{
switch (MCInst_getOpcode(MI)) {
case TriCore_LD_A_slro:
case TriCore_LD_A_sro:
@ -251,7 +265,8 @@ static void off4_fixup(MCInst *MI, uint64_t *off4) {
}
}
static void print_zero_ext(MCInst *MI, int OpNum, SStream *O, unsigned n) {
static void print_zero_ext(MCInst *MI, int OpNum, SStream *O, unsigned n)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
if (MCOperand_isImm(MO)) {
uint64_t imm = MCOperand_getImm(MO);
@ -278,7 +293,8 @@ static void print_zero_ext(MCInst *MI, int OpNum, SStream *O, unsigned n) {
printOperand(MI, OpNum, O);
}
static void printOff18Imm(MCInst *MI, int OpNum, SStream *O) {
static void printOff18Imm(MCInst *MI, int OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
if (MCOperand_isImm(MO)) {
uint32_t imm = (uint32_t)MCOperand_getImm(MO);
@ -289,16 +305,21 @@ static void printOff18Imm(MCInst *MI, int OpNum, SStream *O) {
printOperand(MI, OpNum, O);
}
static inline void fixup_tricore_disp(MCInst *MI, int OpNum, int32_t disp) {
if (MI->csh->detail != CS_OPT_ON) return;
if (OpNum <= 0) return;
static inline void fixup_tricore_disp(MCInst *MI, int OpNum, int32_t disp)
{
if (MI->csh->detail != CS_OPT_ON)
return;
if (OpNum <= 0)
return;
cs_tricore *tricore = &MI->flat_insn->detail->tricore;
if (tricore->operands[tricore->op_count - 1].type != TRICORE_OP_REG) return;
if (tricore->operands[tricore->op_count - 1].type != TRICORE_OP_REG)
return;
fill_mem(tricore, tricore->operands[tricore->op_count - 1].reg, disp);
}
static void printDisp24Imm(MCInst *MI, int OpNum, SStream *O) {
static void printDisp24Imm(MCInst *MI, int OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
if (MCOperand_isImm(MO)) {
int32_t disp = (int32_t)MCOperand_getImm(MO);
@ -313,7 +334,8 @@ static void printDisp24Imm(MCInst *MI, int OpNum, SStream *O) {
case TriCore_JA_b:
case TriCore_JLA_b:
// = {disp24[23:20], 7’b0000000, disp24[19:0], 1’b0};
disp = ((disp & 0xf00000) << 28) | ((disp & 0xfffff) << 1);
disp = ((disp & 0xf00000) << 28) |
((disp & 0xfffff) << 1);
break;
case TriCore_J_b:
case TriCore_JL_b:
@ -327,7 +349,8 @@ static void printDisp24Imm(MCInst *MI, int OpNum, SStream *O) {
printOperand(MI, OpNum, O);
}
static void printDisp15Imm(MCInst *MI, int OpNum, SStream *O) {
static void printDisp15Imm(MCInst *MI, int OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
if (MCOperand_isImm(MO)) {
int32_t disp = (int32_t)MCOperand_getImm(MO);
@ -371,7 +394,8 @@ static void printDisp15Imm(MCInst *MI, int OpNum, SStream *O) {
printOperand(MI, OpNum, O);
}
static void printDisp8Imm(MCInst *MI, int OpNum, SStream *O) {
static void printDisp8Imm(MCInst *MI, int OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
if (MCOperand_isImm(MO)) {
int32_t disp = (int32_t)MCOperand_getImm(MO);
@ -395,7 +419,8 @@ static void printDisp8Imm(MCInst *MI, int OpNum, SStream *O) {
printOperand(MI, OpNum, O);
}
static void printDisp4Imm(MCInst *MI, int OpNum, SStream *O) {
static void printDisp4Imm(MCInst *MI, int OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
if (MCOperand_isImm(MO)) {
int32_t disp = (int32_t)MCOperand_getImm(MO);
@ -424,7 +449,9 @@ static void printDisp4Imm(MCInst *MI, int OpNum, SStream *O) {
break;
case TriCore_LOOP_sbr:
// {27b’111111111111111111111111111, disp4, 0};
disp = (int32_t) MI->address + ((0b111111111111111111111111111 << 5) | (disp << 1));
disp = (int32_t)MI->address +
((0b111111111111111111111111111 << 5) |
(disp << 1));
break;
default:
// handle other cases, if any
@ -443,7 +470,6 @@ static void printDisp4Imm(MCInst *MI, int OpNum, SStream *O) {
print_sign_ext(MI, OpNum, O, n); \
}
printSExtImm_(16)
printSExtImm_(10)
@ -468,7 +494,11 @@ printZExtImm_(4)
printZExtImm_(2)
static void printOExtImm_4(MCInst *MI, int OpNum, SStream *O) {
static void printOExtImm_4(
MCInst *MI,
int OpNum,
SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
if (MCOperand_isImm(MO)) {
uint32_t imm = MCOperand_getImm(MO);
@ -481,14 +511,14 @@ static void printOExtImm_4(MCInst *MI, int OpNum, SStream *O) {
printOperand(MI, OpNum, O);
}
/// Returned by getMnemonic() of the AsmPrinters.
typedef struct {
const char *first; // Menmonic
uint64_t second; // Bits
} MnemonicBitsInfo;
void set_mem_access(MCInst *MI, unsigned int access) {
void set_mem_access(MCInst *MI, unsigned int access)
{
// TODO: TriCore
}
@ -496,7 +526,8 @@ void set_mem_access(MCInst *MI, unsigned int access) {
#include "TriCoreGenAsmWriter.inc"
const char *TriCore_getRegisterName(csh handle, unsigned int id) {
const char *TriCore_getRegisterName(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
return getRegisterName(id);
#else
@ -504,7 +535,8 @@ const char *TriCore_getRegisterName(csh handle, unsigned int id) {
#endif
}
void TriCore_printInst(MCInst *MI, SStream *O, void *Info) {
void TriCore_printInst(MCInst *MI, SStream *O, void *Info)
{
printInstruction(MI, MI->address, O);
}

25
arch/TriCore/TriCoreMapping.c
View File

@ -30,8 +30,10 @@ static insn_map insns[] = {
#include "TriCoreGenCSMappingInsn.inc"
};
unsigned int TriCore_map_insn_id(cs_struct *h, unsigned int id) {
unsigned short i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
unsigned int TriCore_map_insn_id(cs_struct *h, unsigned int id)
{
unsigned short i =
insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
if (i != 0) {
return insns[i].mapid;
}
@ -39,7 +41,8 @@ unsigned int TriCore_map_insn_id(cs_struct *h, unsigned int id) {
}
// given internal insn id, return public instruction info
void TriCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) {
void TriCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
{
unsigned short i;
i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
@ -58,12 +61,16 @@ void TriCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) {
insn->detail->regs_write_count =
(uint8_t)count_positive(insns[i].regs_mod);
memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
insn->detail->groups_count = (uint8_t) count_positive8(insns[i].groups);
memcpy(insn->detail->groups, insns[i].groups,
sizeof(insns[i].groups));
insn->detail->groups_count =
(uint8_t)count_positive8(insns[i].groups);
if (insns[i].branch || insns[i].indirect_branch) {
// this insn also belongs to JUMP group. add JUMP group
insn->detail->groups[insn->detail->groups_count] = TriCore_GRP_JUMP;
insn->detail
->groups[insn->detail->groups_count] =
TriCore_GRP_JUMP;
insn->detail->groups_count++;
}
#endif
@ -83,7 +90,8 @@ static const char *insn_names[] = {
static name_map alias_insn_names[] = { { 0, NULL } };
#endif
const char *TriCore_insn_name(csh handle, unsigned int id) {
const char *TriCore_insn_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
unsigned int i;
@ -110,7 +118,8 @@ static name_map group_name_maps[] = {
};
#endif
const char *TriCore_group_name(csh handle, unsigned int id) {
const char *TriCore_group_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
if (id >= TriCore_GRP_ENDING)
return NULL;

1
arch/TriCore/TriCoreMapping.h
View File

@ -16,4 +16,3 @@ const char *TriCore_insn_name(csh handle, unsigned int id);
const char *TriCore_group_name(csh handle, unsigned int id);
#endif

22
cstool/cstool_tricore.c
View File

@ -29,26 +29,30 @@ void print_insn_detail_tricore(csh handle, cs_insn *ins)
cs_reg_name(handle, op->reg));
break;
case TRICORE_OP_IMM:
printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm);
printf("\t\toperands[%u].type: IMM = 0x%x\n", i,
op->imm);
break;
case TRICORE_OP_MEM:
printf("\t\toperands[%u].type: MEM\n", i);
if (op->mem.base != TriCore_REG_INVALID)
printf("\t\t\toperands[%u].mem.base: REG = %s\n", i,
cs_reg_name(handle, op->mem.base));
printf("\t\t\toperands[%u].mem.base: REG = %s\n",
i, cs_reg_name(handle, op->mem.base));
if (op->mem.disp != 0)
printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp);
printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i,
op->mem.disp);
break;
}
// Print out all registers accessed by this instruction (either implicit or
// explicit)
if (!cs_regs_access(handle, ins, regs_read, &regs_read_count, regs_write,
&regs_write_count)) {
if (!cs_regs_access(handle, ins, regs_read, &regs_read_count,
regs_write, &regs_write_count)) {
if (regs_read_count) {
printf("\tRegisters read:");
for (i = 0; i < regs_read_count; i++) {
printf(" %s", cs_reg_name(handle, regs_read[i]));
printf(" %s",
cs_reg_name(handle,
regs_read[i]));
}
printf("\n");
}
@ -56,7 +60,9 @@ void print_insn_detail_tricore(csh handle, cs_insn *ins)
if (regs_write_count) {
printf("\tRegisters modified:");
for (i = 0; i < regs_write_count; i++) {
printf(" %s", cs_reg_name(handle, regs_write[i]));
printf(" %s",
cs_reg_name(handle,
regs_write[i]));
}
printf("\n");
}

25
suite/cstest/src/tricore_detail.c
View File

@ -35,27 +35,32 @@ char *get_detail_tricore(csh *p_handle, cs_mode mode, cs_insn *ins)
cs_reg_name(handle, op->reg));
break;
case TRICORE_OP_IMM:
add_str(&result, "\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm);
add_str(&result, "\t\toperands[%u].type: IMM = 0x%x\n",
i, op->imm);
break;
case TRICORE_OP_MEM:
add_str(&result, "\t\toperands[%u].type: MEM\n", i);
if (op->mem.base != TriCore_REG_INVALID)
add_str(&result, "\t\t\toperands[%u].mem.base: REG = %s\n", i,
cs_reg_name(handle, op->mem.base));
add_str(&result,
"\t\t\toperands[%u].mem.base: REG = %s\n",
i, cs_reg_name(handle, op->mem.base));
if (op->mem.disp != 0)
add_str(&result, "\t\t\toperands[%u].mem.disp: 0x%x\n", i,
op->mem.disp);
add_str(&result,
"\t\t\toperands[%u].mem.disp: 0x%x\n",
i, op->mem.disp);
break;
}
// Print out all registers accessed by this instruction (either implicit or
// explicit)
if (!cs_regs_access(handle, ins, regs_read, &regs_read_count, regs_write,
&regs_write_count)) {
if (!cs_regs_access(handle, ins, regs_read, &regs_read_count,
regs_write, &regs_write_count)) {
if (regs_read_count) {
add_str(&result, "\tRegisters read:");
for (i = 0; i < regs_read_count; i++) {
add_str(&result, " %s", cs_reg_name(handle, regs_read[i]));
add_str(&result, " %s",
cs_reg_name(handle,
regs_read[i]));
}
add_str(&result, "\n");
}
@ -63,7 +68,9 @@ char *get_detail_tricore(csh *p_handle, cs_mode mode, cs_insn *ins)
if (regs_write_count) {
add_str(&result, "\tRegisters modified:");
for (i = 0; i < regs_write_count; i++) {
add_str(&result, " %s", cs_reg_name(handle, regs_write[i]));
add_str(&result, " %s",
cs_reg_name(handle,
regs_write[i]));
}
add_str(&result, "\n");
}

34
tests/test_tricore.c
View File

@ -47,10 +47,12 @@ static void print_insn_detail(cs_insn *ins)
default:
break;
case TRICORE_OP_REG:
printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
printf("\t\toperands[%u].type: REG = %s\n", i,
cs_reg_name(handle, op->reg));
break;
case TRICORE_OP_IMM:
printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm);
printf("\t\toperands[%u].type: IMM = 0x%x\n", i,
op->imm);
break;
case TRICORE_OP_MEM:
printf("\t\toperands[%u].type: MEM\n", i);
@ -58,7 +60,8 @@ static void print_insn_detail(cs_insn *ins)
printf("\t\t\toperands[%u].mem.base: REG = %s\n",
i, cs_reg_name(handle, op->mem.base));
if (op->mem.disp != 0)
printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp);
printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i,
op->mem.disp);
break;
}
@ -70,7 +73,8 @@ static void print_insn_detail(cs_insn *ins)
static void test()
{
//#define TRICORE_CODE "\x16\x01\x20\x01\x1d\x00\x02\x00\x8f\x70\x00\x11\x40\xae\x89\xee\x04\x09\x42\xf2\xe2\xf2\xc2\x11\x19\xff\xc0\x70\x19\xff\x20\x10"
#define TRICORE_CODE "\x09\xcf\xbc\xf5\x09\xf4\x01\x00\x89\xfb\x8f\x74\x89\xfe\x48\x01\x29\x00\x19\x25\x29\x03\x09\xf4\x85\xf9\x68\x0f\x16\x01"
#define TRICORE_CODE \
"\x09\xcf\xbc\xf5\x09\xf4\x01\x00\x89\xfb\x8f\x74\x89\xfe\x48\x01\x29\x00\x19\x25\x29\x03\x09\xf4\x85\xf9\x68\x0f\x16\x01"
struct platform platforms[] = {
{
@ -88,35 +92,43 @@ static void test()
size_t count;
for (i = 0; i < sizeof(platforms) / sizeof(platforms[0]); i++) {
cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
cs_err err =
cs_open(platforms[i].arch, platforms[i].mode, &handle);
if (err) {
printf("Failed on cs_open() with error returned: %u\n", err);
printf("Failed on cs_open() with error returned: %u\n",
err);
continue;
}
cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
count = cs_disasm(handle, platforms[i].code, platforms[i].size,
address, 0, &insn);
if (count) {
size_t j;
printf("****************\n");
printf("Platform: %s\n", platforms[i].comment);
print_string_hex("Code:", platforms[i].code, platforms[i].size);
print_string_hex("Code:", platforms[i].code,
platforms[i].size);
printf("Disasm:\n");
for (j = 0; j < count; j++) {
printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
printf("0x%" PRIx64 ":\t%s\t%s\n",
insn[j].address, insn[j].mnemonic,
insn[j].op_str);
print_insn_detail(&insn[j]);
}
printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size);
printf("0x%" PRIx64 ":\n",
insn[j - 1].address + insn[j - 1].size);
// free memory allocated by cs_disasm()
cs_free(insn, count);
} else {
printf("****************\n");
printf("Platform: %s\n", platforms[i].comment);
print_string_hex("Code:", platforms[i].code, platforms[i].size);
print_string_hex("Code:", platforms[i].code,
platforms[i].size);
printf("ERROR: Failed to disasm given code!\n");
}