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x86: handle 0x82 opcode for CAPSTONE_X86_REDUCE setup

This commit is contained in:
Nguyen Anh Quynh 2014-12-30 15:43:19 +08:00
parent 3410b63a4e
commit 3c27827a25
7 changed files with 6113 additions and 5965 deletions
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4
arch/X86/X86Disassembler.c
View File

@ -211,6 +211,7 @@ static void translateImmediate(MCInst *mcInst, uint64_t immediate,
break;
}
} else if (type == TYPE_IMM3) {
#ifndef CAPSTONE_X86_REDUCE
// Check for immediates that printSSECC can't handle.
if (immediate >= 8) {
unsigned NewOpc = 0;
@ -229,7 +230,9 @@ static void translateImmediate(MCInst *mcInst, uint64_t immediate,
// Switch opcode to the one that doesn't get special printing.
MCInst_setOpcode(mcInst, NewOpc);
}
#endif
} else if (type == TYPE_IMM5) {
#ifndef CAPSTONE_X86_REDUCE
// Check for immediates that printAVXCC can't handle.
if (immediate >= 32) {
unsigned NewOpc = 0;
@ -260,6 +263,7 @@ static void translateImmediate(MCInst *mcInst, uint64_t immediate,
// Switch opcode to the one that doesn't get special printing.
MCInst_setOpcode(mcInst, NewOpc);
}
#endif
}
switch (type) {

6
arch/X86/X86DisassemblerDecoder.c
View File

@ -951,10 +951,8 @@ static int readOpcode(struct InternalInstruction *insn)
}
// Hacky for FEMMS
#ifndef CAPSTONE_X86_REDUCE
#define GET_INSTRINFO_ENUM
#ifdef CAPSTONE_X86_REDUCE
#include "X86GenInstrInfo_reduce.inc"
#else
#include "X86GenInstrInfo.inc"
#endif
@ -978,11 +976,13 @@ static int getIDWithAttrMask(uint16_t *instructionID,
InstructionContext instructionClass;
#ifndef CAPSTONE_X86_REDUCE
// HACK for femms. to be handled properly in next version 3.x
if (insn->opcode == 0x0e && insn->opcodeType == T3DNOW_MAP) {
*instructionID = X86_FEMMS;
return 0;
}
#endif
if (insn->opcodeType == T3DNOW_MAP)
instructionClass = IC_OF;

23
arch/X86/X86GenAsmWriter1_reduce.inc
View File

@ -69,8 +69,10 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
8532099U, // ADC64rm
2240643U, // ADC64rr
2232451U, // ADC64rr_REV
2240643U, // ADC82_8ri8
5384U, // ADC8i8
155779U, // ADC8mi
155779U, // ADC8mi8
155779U, // ADC8mr
2240643U, // ADC8ri
10629251U, // ADC8rm
@ -116,11 +118,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
2240699U, // ADD64rr
0U, // ADD64rr_DB
2232507U, // ADD64rr_REV
155835U, // ADD82_8mi8
2240699U, // ADD82_8ri8
5393U, // ADD8i8
155835U, // ADD8mi
155835U, // ADD8mr
2240699U, // ADD8ri
2240699U, // ADD8ri8
10629307U, // ADD8rm
2240699U, // ADD8rr
2232507U, // ADD8rr_REV
@ -159,11 +162,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
8532204U, // AND64rm
2240748U, // AND64rr
2232556U, // AND64rr_REV
155884U, // AND82_8mi8
2240748U, // AND82_8ri8
5402U, // AND8i8
155884U, // AND8mi
155884U, // AND8mr
2240748U, // AND8ri
2240748U, // AND8ri8
10629356U, // AND8rm
2240748U, // AND8rr
2232556U, // AND8rr_REV
@ -448,8 +452,10 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
16913109U, // CMP64rm
14815957U, // CMP64rr
14815957U, // CMP64rr_REV
14815957U, // CMP82_8ri8
5419U, // CMP8i8
156373U, // CMP8mi
156373U, // CMP8mi8
156373U, // CMP8mr
14815957U, // CMP8ri
21107413U, // CMP8rm
@ -993,11 +999,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
8532834U, // OR64rm
2241378U, // OR64rr
2233186U, // OR64rr_REV
156514U, // OR82_8mi8
2241378U, // OR82_8ri8
5429U, // OR8i8
156514U, // OR8mi
156514U, // OR8mr
2241378U, // OR8ri
2241378U, // OR8ri8
10629986U, // OR8rm
2241378U, // OR8rr
2233186U, // OR8rr_REV
@ -1302,8 +1309,10 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
8532045U, // SBB64rm
2240589U, // SBB64rr
2232397U, // SBB64rr_REV
2240589U, // SBB82_8ri8
5344U, // SBB8i8
155725U, // SBB8mi
155725U, // SBB8mi8
155725U, // SBB8mr
2240589U, // SBB8ri
10629197U, // SBB8rm
@ -1495,11 +1504,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
8532087U, // SUB64rm
2240631U, // SUB64rr
2232439U, // SUB64rr_REV
155767U, // SUB82_8mi8
2240631U, // SUB82_8ri8
5375U, // SUB8i8
155767U, // SUB8mi
155767U, // SUB8mr
2240631U, // SUB8ri
2240631U, // SUB8ri8
10629239U, // SUB8rm
2240631U, // SUB8rr
2232439U, // SUB8rr_REV
@ -1667,11 +1677,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
8532846U, // XOR64rm
2241390U, // XOR64rr
2233198U, // XOR64rr_REV
156526U, // XOR82_8mi8
2241390U, // XOR82_8ri8
5428U, // XOR8i8
156526U, // XOR8mi
156526U, // XOR8mr
2241390U, // XOR8ri
2241390U, // XOR8ri8
10629998U, // XOR8rm
2241390U, // XOR8rr
2233198U, // XOR8rr_REV
@ -2146,7 +2157,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
printi64mem(MI, 0, O);
break;
case 6:
// ADC8mi, ADC8mr, ADD8mi, ADD8mr, AND8mi, AND8mr, CMP8mi, CMP8mr, CMPXCH...
// ADC8mi, ADC8mi8, ADC8mr, ADD82_8mi8, ADD8mi, ADD8mr, AND82_8mi8, AND8m...
printi8mem(MI, 0, O);
break;
case 7:

24
arch/X86/X86GenAsmWriter_reduce.inc
View File

@ -69,8 +69,10 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
1623380U, // ADC64rm
1598804U, // ADC64rr
2123092U, // ADC64rr_REV
1597486U, // ADC82_8ri8
4726830U, // ADC8i8
5259310U, // ADC8mi
5259310U, // ADC8mi8
5259310U, // ADC8mr
1597486U, // ADC8ri
57390U, // ADC8rm
@ -116,11 +118,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
1598838U, // ADD64rr
0U, // ADD64rr_DB
2123126U, // ADD64rr_REV
5259329U, // ADD82_8mi8
1597505U, // ADD82_8ri8
4726849U, // ADD8i8
5259329U, // ADD8mi
5259329U, // ADD8mr
1597505U, // ADD8ri
1597505U, // ADD8ri8
57409U, // ADD8rm
1597505U, // ADD8rr
2121793U, // ADD8rr_REV
@ -159,11 +162,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
1623439U, // AND64rm
1598863U, // AND64rr
2123151U, // AND64rr_REV
5259335U, // AND82_8mi8
1597511U, // AND82_8ri8
4726855U, // AND8i8
5259335U, // AND8mi
5259335U, // AND8mr
1597511U, // AND8ri
1597511U, // AND8ri8
57415U, // AND8rm
1597511U, // AND8rr
2121799U, // AND8rr_REV
@ -448,8 +452,10 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
83630U, // CMP64rm
22619822U, // CMP64rr
22619822U, // CMP64rr_REV
22618245U, // CMP82_8ri8
4726917U, // CMP8i8
5259397U, // CMP8mi
5259397U, // CMP8mi8
5259397U, // CMP8mr
22618245U, // CMP8ri
139397U, // CMP8rm
@ -993,11 +999,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
1623780U, // OR64rm
1599204U, // OR64rr
2123492U, // OR64rr_REV
5259422U, // OR82_8mi8
1597598U, // OR82_8ri8
4726942U, // OR8i8
5259422U, // OR8mi
5259422U, // OR8mr
1597598U, // OR8ri
1597598U, // OR8ri8
57502U, // OR8rm
1597598U, // OR8rr
2121886U, // OR8rr_REV
@ -1302,8 +1309,10 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
1623344U, // SBB64rm
1598768U, // SBB64rr
2123056U, // SBB64rr_REV
1597474U, // SBB82_8ri8
4726818U, // SBB8i8
5259298U, // SBB8mi
5259298U, // SBB8mi8
5259298U, // SBB8mr
1597474U, // SBB8ri
57378U, // SBB8rm
@ -1495,11 +1504,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
1623358U, // SUB64rm
1598782U, // SUB64rr
2123070U, // SUB64rr_REV
5259304U, // SUB82_8mi8
1597480U, // SUB82_8ri8
4726824U, // SUB8i8
5259304U, // SUB8mi
5259304U, // SUB8mr
1597480U, // SUB8ri
1597480U, // SUB8ri8
57384U, // SUB8rm
1597480U, // SUB8rr
2121768U, // SUB8rr_REV
@ -1667,11 +1677,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
1623794U, // XOR64rm
1599218U, // XOR64rr
2123506U, // XOR64rr_REV
5259427U, // XOR82_8mi8
1597603U, // XOR82_8ri8
4726947U, // XOR8i8
5259427U, // XOR8mi
5259427U, // XOR8mr
1597603U, // XOR8ri
1597603U, // XOR8ri8
57507U, // XOR8rm
1597603U, // XOR8rr
2121891U, // XOR8rr_REV
@ -2615,7 +2626,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
return;
break;
case 10:
// ADC8mi, ADC8mr, ADD8mi, ADD8mr, AND8mi, AND8mr, CMP8mi, CMP8mr, CMPXCH...
// ADC8mi, ADC8mi8, ADC8mr, ADD82_8mi8, ADD8mi, ADD8mr, AND82_8mi8, AND8m...
printi8mem(MI, 0, O);
break;
case 11:
@ -3064,7 +3075,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
const char *AsmString;
char *tmp, *AsmMnem, *AsmOps, *c;
int OpIdx, PrintMethodIdx;
MCRegisterInfo *MRI = (MCRegisterInfo *)info;
switch (MCInst_getOpcode(MI)) {
default: return NULL;
case X86_AAD8i8:

7273
arch/X86/X86GenDisassemblerTables_reduce.inc
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File diff suppressed because it is too large Load Diff

4622
arch/X86/X86GenInstrInfo_reduce.inc
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File diff suppressed because it is too large Load Diff

126
arch/X86/X86Mapping.c
View File

@ -38159,6 +38159,12 @@ static insn_map insns[] = { // reduce x86 instructions
X86_ADC64rr_REV, X86_INS_ADC,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
#endif
},
{
X86_ADC82_8ri8, X86_INS_ADC,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},
{
@ -38171,6 +38177,12 @@ static insn_map insns[] = { // reduce x86 instructions
X86_ADC8mi, X86_INS_ADC,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
#endif
},
{
X86_ADC8mi8, X86_INS_ADC,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},
{
@ -38387,6 +38399,18 @@ static insn_map insns[] = { // reduce x86 instructions
X86_ADD64rr_REV, X86_INS_ADD,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
#endif
},
{
X86_ADD82_8mi8, X86_INS_ADD,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},
{
X86_ADD82_8ri8, X86_INS_ADD,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},
{
@ -38411,12 +38435,6 @@ static insn_map insns[] = { // reduce x86 instructions
X86_ADD8ri, X86_INS_ADD,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
#endif
},
{
X86_ADD8ri8, X86_INS_ADD,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},
{
@ -38621,6 +38639,18 @@ static insn_map insns[] = { // reduce x86 instructions
X86_AND64rr_REV, X86_INS_AND,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
#endif
},
{
X86_AND82_8mi8, X86_INS_AND,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},
{
X86_AND82_8ri8, X86_INS_AND,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},
{
@ -38645,12 +38675,6 @@ static insn_map insns[] = { // reduce x86 instructions
X86_AND8ri, X86_INS_AND,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
#endif
},
{
X86_AND8ri8, X86_INS_AND,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},
{
@ -40253,6 +40277,12 @@ static insn_map insns[] = { // reduce x86 instructions
X86_CMP64rr_REV, X86_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
#endif
},
{
X86_CMP82_8ri8, X86_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},
{
@ -40265,6 +40295,12 @@ static insn_map insns[] = { // reduce x86 instructions
X86_CMP8mi, X86_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
#endif
},
{
X86_CMP8mi8, X86_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},
{
@ -43445,6 +43481,18 @@ static insn_map insns[] = { // reduce x86 instructions
X86_OR64rr_REV, X86_INS_OR,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
#endif
},
{
X86_OR82_8mi8, X86_INS_OR,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},
{
X86_OR82_8ri8, X86_INS_OR,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},
{
@ -43469,12 +43517,6 @@ static insn_map insns[] = { // reduce x86 instructions
X86_OR8ri, X86_INS_OR,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
#endif
},
{
X86_OR8ri8, X86_INS_OR,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},
{
@ -45269,6 +45311,12 @@ static insn_map insns[] = { // reduce x86 instructions
X86_SBB64rr_REV, X86_INS_SBB,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
#endif
},
{
X86_SBB82_8ri8, X86_INS_SBB,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},
{
@ -45281,6 +45329,12 @@ static insn_map insns[] = { // reduce x86 instructions
X86_SBB8mi, X86_INS_SBB,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
#endif
},
{
X86_SBB8mi8, X86_INS_SBB,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},
{
@ -46343,6 +46397,18 @@ static insn_map insns[] = { // reduce x86 instructions
X86_SUB64rr_REV, X86_INS_SUB,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
#endif
},
{
X86_SUB82_8mi8, X86_INS_SUB,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},
{
X86_SUB82_8ri8, X86_INS_SUB,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},
{
@ -46367,12 +46433,6 @@ static insn_map insns[] = { // reduce x86 instructions
X86_SUB8ri, X86_INS_SUB,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
#endif
},
{
X86_SUB8ri8, X86_INS_SUB,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},
{
@ -47225,6 +47285,18 @@ static insn_map insns[] = { // reduce x86 instructions
X86_XOR64rr_REV, X86_INS_XOR,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
#endif
},
{
X86_XOR82_8mi8, X86_INS_XOR,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},
{
X86_XOR82_8ri8, X86_INS_XOR,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},
{
@ -47249,12 +47321,6 @@ static insn_map insns[] = { // reduce x86 instructions
X86_XOR8ri, X86_INS_XOR,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
#endif
},
{
X86_XOR8ri8, X86_INS_XOR,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},
{