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arm: use lowercase for special registers
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@ -1378,7 +1378,7 @@ static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O)
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// As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
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// APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
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if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
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SStream_concat0(O, "APSR_");
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SStream_concat0(O, "apsr_");
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switch (Mask) {
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default: // llvm_unreachable("Unexpected mask value!");
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case 4: SStream_concat0(O, "g"); ARM_addSysReg(MI, ARM_SYSREG_APSR_G); return;
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@ -1389,7 +1389,7 @@ static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O)
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reg = 0;
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if (SpecRegRBit) {
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SStream_concat0(O, "SPSR");
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SStream_concat0(O, "spsr");
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if (Mask) {
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SStream_concat0(O, "_");
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if (Mask & 8) {
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@ -1414,7 +1414,7 @@ static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O)
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ARM_addSysReg(MI, reg);
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}
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} else {
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SStream_concat0(O, "CPSR");
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SStream_concat0(O, "cpsr");
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if (Mask) {
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SStream_concat0(O, "_");
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if (Mask & 8) {
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