Virtualization
/
capstone
mirror of https://gitlab.com/qemu-project/capstone.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

fix xtensa DecodeMR23RegisterClass and add tests for MAC16 instru… (#2551) 

* fix xtensa `DecodeMR23RegisterClass` and add tests for `MAC16` instructions

* revert
This commit is contained in:
billow 2024-11-24 22:21:05 +08:00 committed by GitHub
parent 7d01d7e7a9
commit fc59da4d1c
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
2 changed files with 99 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/Xtensa/XtensaDisassembler.c
View File

@ -225,10 +225,10 @@ static DecodeStatus DecodeMR23RegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder)
{
if ((RegNo < 2) || (RegNo > 3))
if (RegNo >= ARR_SIZE(MR23DecoderTable))
return MCDisassembler_Fail;
unsigned Reg = MR23DecoderTable[RegNo - 2];
unsigned Reg = MR23DecoderTable[RegNo];
MCOperand_CreateReg0(Inst, (Reg));
return MCDisassembler_Success;
}

97
tests/MC/Xtensa/mac16.s.yaml Normal file
View File

@ -0,0 +1,97 @@
test_cases:
- input:
bytes: [ 0x04,0x01,0x34 ]
arch: "xtensa"
options: [ ]
address: 0x0
expected:
insns:
- asm_text: "mul.ad.ll a1, m2"
- input:
bytes: [ 0x14,0x02,0x74 ]
arch: "xtensa"
options: [ ]
address: 0x0
expected:
insns:
- asm_text: "mul.aa.ll a2, a1"
- input:
bytes: [ 0x14,0x00,0x64 ]
arch: "xtensa"
options: [ ]
address: 0x0
expected:
insns:
- asm_text: "mul.da.ll m0, a1"
- input:
bytes: [ 0x04,0x00,0x24 ]
arch: "xtensa"
options: [ ]
address: 0x0
expected:
insns:
- asm_text: "mul.dd.ll m0, m2"
- input:
bytes: [ 0x04,0x01,0x38 ]
arch: "xtensa"
options: [ ]
address: 0x0
expected:
insns:
- asm_text: "mula.ad.ll a1, m2"
- input:
bytes: [ 0x14,0x02,0x78 ]
arch: "xtensa"
options: [ ]
address: 0x0
expected:
insns:
- asm_text: "mula.aa.ll a2, a1"
- input:
bytes: [ 0x14,0x00,0x68 ]
arch: "xtensa"
options: [ ]
address: 0x0
expected:
insns:
- asm_text: "mula.da.ll m0, a1"
- input:
bytes: [ 0x04,0x00,0x28 ]
arch: "xtensa"
options: [ ]
address: 0x0
expected:
insns:
- asm_text: "mula.dd.ll m0, m2"
- input:
bytes: [ 0x14,0x00,0x58 ]
arch: "xtensa"
options: [ ]
address: 0x0
expected:
insns:
- asm_text: "mula.da.ll.lddec m0, a0, m0, a1"
- input:
bytes: [ 0x14,0x00,0x48 ]
arch: "xtensa"
options: [ ]
address: 0x0
expected:
insns:
- asm_text: "mula.da.ll.ldinc m0, a0, m0, a1"
- input:
bytes: [ 0x04,0x00,0x18 ]
arch: "xtensa"
options: [ ]
address: 0x0
expected:
insns:
- asm_text: "mula.dd.ll.lddec m0, a0, m0, m2"
- input:
bytes: [ 0x04,0x00,0x08 ]
arch: "xtensa"
options: [ ]
address: 0x0
expected:
insns:
- asm_text: "mula.dd.ll.ldinc m0, a0, m0, m2"