Commit Graph

167 Commits

Author SHA1 Message Date
Wu ChenXu 66b08439ab
Update to Version 6.0.0-Alpha2 (#2554)
* Update changelog for V6.0.0-Alpha1 (#2493)

* update version to v6-alpha1

* update bindings const values

* Update changelog for V6.0.0-Alpha1

* Remove irrelevant changes. (#2495)

* Fixing UB santizer, `LITBASE` and assert errors. (#2499)

* Update labeler with Xtensa and v6 files. (#2500)

* Add hard asserts to all SStream functions and memset MCInst. (#2501)

* Only trigger on released action. (#2497)

* Fix cstest build with Ninja (#2506)

* Tricore EA calculation (#2504)

* Update libcyaml dependency in cstest to 1.4.2 (#2508)

* AArch64: Replace vararg add_cs_detail by multiple concrete functions

Fixes UB caused by various mismatches on how these arguments are passed
and read. This became visible when running on PowerPC hosts with e.g.
`cstool -d aarch64 204862f8`.
Apart from the UB fix, this is meant to be a pure refactor.

Partially addresses #2458

* xtensa: Fix Branch Target (#2516)

* xtensa: Fix Branch Target

* auto-sync: fix byte pattern

* xtensa: add branch insn tests

* Revert "auto-sync: fix byte pattern"

This reverts commit cf8e870f776889514b69a2f25a376f62ab2b291c.

* Fix #2509. (#2510)

Compatibility headers should always include the header in the same dir.

* Fix stringop-truncation warning some compilers raise. (#2522)

* Add CC and VAS compatibility macros (#2525)

* Fix endianess issue during assignment. (#2528)

* This time actually fix big endian issue. (#2530)

* tricore: fixes #2474 (#2523)

* tricore: fix auto-sync tricore

* tricore: fixes TriCoreGenCSMappingInsnName.inc

* tricore: fixes

* tricore: try fix ld.a SC

* tricore: fixes all

* Add TriCore to .github/workflows/auto-sync.yaml

* Add TriCore details tests(a15, d15, a10|sp)

* Change CI to create Debian Package to Release (#2521)

* Updating CI to create Debian package and version is assigned by tag
version. Also updating release CI to not use end-of-life workflows

* Clear up usage of static libraries.

- Python bindings only use the dynamic lib. But built and copied the static ones sometimes nonetheless.
- Add toggles to build only static, static/dyn or only dynamic.

---------

Co-authored-by: Rot127 <unisono@quyllur.org>

* Rename build arguments: (#2534)

- BUILD_SHARED_LIBS -> CAPSTONE_BUILD_SHARED_LIBS
- BUILD_STATIC_LIBS -> CAPSTONE_BUILD_STATIC_LIBS
- BUILD_STATIC_LIBS -> CAPSTONE_BUILD_STATIC_MSVC_RUNTIME

* xtensa: update to espressif/llvm-project (#2533)

* fix coverity (#2546)

- cid 514642

- cid 514643

- cid 514644

- cid 514645

* Move debian package generation to a dispatch only workflow (#2543)

* Move deb package gen files int package/deb

* Fix basename check

* Make debian package generation dispatch only

* Python package building rework (#2538)

* - Refactored setup.py to remove hacks regarding packaging of wheels for different platforms, improve and cleanup the code
- Updated README.txt
- Removed old Makefile and build_wheel.sh scripts
- Created a new workflow that takes care of building and testing python packages for different platforms/architectures/python versions

* Added SPDX headers to the setup.py

* - cstest_py: Fixed positional argument since it doesn't accept a `required` flag. It turns to have a mandatory tests folder path
- integration_tests.py: Use pathlib to determine the required path
- GitHub action: Simplified the tests execution command

* GitHub Actions: Run python 3.8 (lowest) and 3.13 (current highest) for native runners only during testings and the rest during tag release

* GitHub Action:
- Fixed the cibw_build matrix element
- Added a step to prepare artifact name

* GitHub Action: Added run_tests.py script to run all tests during CI workflow

* - Added SPDX headers to the run_tests.py script and to the build-wheels-publish.yml workflow file
- Minor fixes to the workflow as pointed out in the PR review
- Updated MANIFEST.in to reflect the actual libraries built during python wheel creation process
- Use subprocess.run in place of os.system in run_tests.py script

* GitHub Action:
- Run qemu step only if non-native Linux runner
- Added arch:universal2 matrix element for macos-latest runner

* Python bindings: Refreshed the list of files needed to be copied for sdist archive

* GitHub Action: Commented out arch:x86 matrix elements

* GitHub Action: Run qemu step only if non-native Linux runner

* GitHub Action: Minor fixes

* Python bindings: Added missing .in pattern when collecting src files for sdist archive

* Auto-Sync reproducability + ARM update (#2532)

* fix xtensa DecodeMR23RegisterClass and add tests for MAC16 instru… (#2551)

* fix xtensa `DecodeMR23RegisterClass` and add tests for `MAC16` instructions

* revert

* Prepare for update (#2552)

* Bindings(chore): Fix DeprecationWarning

* Version(upgrade): update bindings const

* Fix(chore): Fix ARMCC_Invalid is not defined

* Update Changelog Version to 6.0.0-Alpha2 (#2553)

* Bindings(chore): Fix DeprecationWarning

* Version(upgrade): update bindings const

* Fix(chore): Fix ARMCC_Invalid is not defined

* Changelog: Update to version 6.0.0-Alpha2

---------

Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>
Co-authored-by: Florian Märkl <info@florianmaerkl.de>
Co-authored-by: billow <billow.fun@gmail.com>
Co-authored-by: Andrew <afq2101@columbia.edu>
Co-authored-by: Rot127 <unisono@quyllur.org>
Co-authored-by: @Antelox <anteloxrce@gmail.com>
2024-11-24 23:55:49 +08:00
Rot127 0c90fe13f5
Replace `assert` with `CS_ASSERT` in modules (#2478)
* Replace asserts with macros for AArch64, Alpha, LoongArch, Mips, SystemZ inc files.

* Add missing clearing of MCInst

* Ensure correct dir name is used.

* Replace asserts in inc files for PPC, ARM, TriCore

* Replace all asserts in modules with CS_ASSERT.

Also enable the CS_ASSERTs if CMAKE_BUILD_TYPE=Debug

* Formatting
2024-09-25 14:58:06 +08:00
Rot127 3a2cd3c331
Coverity defects (#2469)
* Fix CID 508418 - Uninitialized struct

* Fix CID 509089 - Fix OOB read and write

* Fix CID 509088 - OOB.

Also adds tests and to ensure no OOB access.

* Fix CID 509085 - Resource leak.

* Fix CID 508414 and companions - Using undefined values.

* Fix CID 508405 - Use of uninitialized value

* Remove unnecessary and badly implemented dev fuzz code.

* Fix CID 508396 - Uninitialzied variable.

* Fix CID 508393, 508365 -- OOB read.

* Fix CID 432207 - OVerlapping memory access.

* Remove unused functions

* Fix CID 432170 - Overlapping memory access.

* Fix CID 166022 - Check for negative index

* Let strncat not depend n src operand.

* Fix 509083 and 509084 - NULL dereference

* Remove duplicated code.

* Initialize sysop

* Fix resource leak

* Remove unreachable code.

* Remove duplicate code.

* Add assert to check return value of cmoack

* Fixed: d should be a signed value, since it is checked against < 0

* Add missing break.

* Add NULL check

* Fix signs of binary search comparisons.

* Add explicit cast of or result

* Fix correct scope of case.

* Handle invalid integer type.

* Return UINT_MAX instead of implicitly casted -1

* Remove dead code

* Fix type of im

* Fix type of d

* Remove duplicated code.

* Add returns after CS_ASSERTS

* Check for len == 0 case.

* Ensure shift operates on uint64

* Replace strcpy with strncpy.

* Handle edge cases for 32bit rotate

* Fix some out of enum warnings

* Replace a strcpy with strncpy.

* Fix increment of address

* Skip some linting

* Fix: set instruction id

* Remove unused enum

* Replace the last usages of strcpy with SStream functions.

* Increase number of allowed AArch64 operands.

* Check safety of incrementing t the next operand.

* Fix naming of operand

* Update python constants

* Fix option setup of CS_OPT_DETAIL_REAL

* Document DETAIL_REAL has to be used with CS_OPT_ON.

* Run Coverity scan every Monday.

* Remove dead code

* Fix OOB read

* Rename macro to reflect it is only used with sstreams

* Fix rebase issues
2024-09-18 21:19:42 +08:00
Rot127 191db14531
Modern Testing (#2456) 2024-08-31 21:33:38 +08:00
Rot127 9c5b48b57f
AArch64 update to LLVM 18 (#2298)
* Run clang-format

* Remove arm.h header from AArch64 files

* Update all AArch64 module files to LLVM-18.

* Add check if the differs save file is up-to-date with the current files.

* Add new generator for MC test trnaslation.

* Fix warnings

* Update generated AsmWriter files

* Remove unused variable

* Change MCPhysReg type to int16_t as LLVM 18 dictates.

With LLVM 18 the MCPhysReg value's type is changed to int16_t.
If we update modules to LLVM 18, they will generate
compiler warnings that uint16_t* should not be casted to int16_t*.

This makes changing the all tables to int16_t necessary, because the alternative is
to duplicate all MCPhysReg related code. Which is even worse.

* Assign enum values to raw_struct member

* Add printAdrAdrpLabel def

* Add header to regression test files.

* Write files to build dir and ignore more parsing errors.

* Fix parsing of MC test files.

* Reset parser after every block

* Add write and patch header step.

* Add and update MC tests for AArch64

* Fix clang-tidy warnings

* Don't warn about padding issues.

They break automatically initialized structs we can not change easily.

* Fix: Incorrect access of LLVM instruction descriptions.

* Initialize DecoderComplete flag

* Add more mapping and flag details

* Add function to get MCInstDesc from table

* Fix incorrect memory operand access types.

* Fix test where memory was not written, ut only read.

* Attempt to fix Windows build

* Fix 2268

The enum values were different and hence lead to different decoding.

* Refactor SME operands.

- Splits SME operands in Matrix and Predicate operands.
- Fixes general problems of incorrect detections with
the vector select/index operands of predicate registers.
- Simplifies code.

* Fix up typo in WRITE

* Print actual path to struct fields

* Add Registers of SME operands to the reg-read list

* Add tests for SME operands.

* Use Capstone reg enum for comparison

* Fix tests: 'Vector arra...' to 'operands[x].vas'

* Add the developer fuzz option.

* Fix Python bindings for SME operands

* Fix variable shadowing.

* Fix clang-tidy warnings

* Add missing break.

* Fix varg usage

* Brackets for case

* Handle AArch64_OP_GROUP_AdrAdrpLabel

* Fix endian issue with fuzzing start bytes

* Move previous sme.pred to it's own operand type.

* Fix calculation for imm ranges

* Print list member flag

* Fix up operand strings for cstest

* Do only a shallow clone of the cmocka stable branch

* Fix: Don't categorize ZT0 as a SME matrix operand.

* Remove unused code.

* Add flag to distinguish Vn and Qn registers.

* Add all registers to detail struct, even if emitted in the asm text

* Fix: Increment op count after each list member is added.

* Remove implicit write to NZCV for MSR Imm instructions.

* Handle several alias operands.

* Add details for zero alias with za0.h

* Add SME tile to write list if written

* Add write access flags to operands which are zeroed.

* Add SME tests of #2285

* Fix tests with latest syntax changes.

* Fix segfault if memory operand is only a label without register.

* Fix python bindings

* Attempt to fix clang-tidy warning for some configurations.

* Add missing test file (accidentially blocked by gitignore.)

* Print clang-tidy version before linting.

* Update differ save file

* Formatting

* Use clang-tidy-15 as if possible.

* Remove search patterns for MC tests, since they need to be reworked anyways.

* Enum to upper case change

* Add information to read the OSS fuzz result.

* Fix special case of SVE2 operands.

Apparently ZT0 registers can an index attached,
get which is BOUND to it. We have no "index for reg" field.
So it is simply saved as an immediate.

* Handle LLVM expressions without asserts.

* Ensure choices are always saved.

* OP_GROUP enums can't be all upper case because they contain type information.

* Fix compatibility header patching

* Update saved_choices.json

* Allow mode == None in test_corpus
2024-07-08 10:28:54 +08:00
RainRat 972bd066bb
fix typos (#2346)
* fix typos

* fix typos

* fix typos
2024-05-12 21:17:20 +08:00
RainRat b91c727481
fix typos (#2344) 2024-04-30 10:37:53 +08:00
Ole André Vadla Ravnås 28d0b20ffe
Fix crash on x86 when building with MSVC (#2253)
There is a compiler bug in latest MSVC, which at the time of writing is
19.36.32535: given `switch (x)`, where `x` is 64 bits wide, the compiler
generates code that computes an incorrect jump table index. E.g. if
`x` is zero, it ends up reading the table entry at index -1.
2024-01-20 23:46:58 +08:00
Richard Henderson 25a69b55e3
Constify Alpha and TriCore (#2245) 2024-01-18 09:45:40 +08:00
Rot127 2fa9f60dcc
[TriCore] Replace one- and sign-extend with MathExtra.h functions. (#2212)
* Replace one- and sign-extend with MathExtra.h functions.

This fixes incorrect sign extensions and reachable
aborts().

* Wrap around PC relative values instead of abort in case of overflow.

---------

Co-authored-by: billow <billow.fun@gmail.com>
2023-12-03 19:15:17 +08:00
billow ce0b1b6744
Fix tricore UB (#2204) 2023-11-30 00:20:44 +08:00
Rot127 ef89b18a88 Architecture updater (auto-sync) - Updating AArch64 (#2026)
* Update sysop inc file

* Fix missing  braces warning

* Handle new system operands

* Fix build errors by renaming.

* Fix segfault

* Fix segfault

* Add custom MCOperand valiadtors

* Add AArch64 case for getFeatureBits

* Fix infinite loop

* Fix braces warning.

* Implement loopuo by name for sys operands

* Fix incorrect translation which remove else if statements.

* Fix several segfaults

* Rename GetRegFromClass patch

* Fix segfaults and asserts

* Fix segfault

* Move MRI setting to Mapping

* Remove unused code

* Add add_op_X functinos for AArch64.

* Add fill detail functins

* Handle RegWithShiftExtend operands

* Handle TypedVectorList operands.

* Handle ComplexRoatation operands

* Handle MemExtend operands

* Handle ImmRangeScale operands

* Handle ExactFPImm operands

* Handle GPRSeqPairsClass operands

* Handle Imm8OptLsl operands

* Handle ImmScale operands

* Handle LogicalImm operands

* Handle Matrix operands

* Handle SME Matrix tiles and vectors.

* Handle normal operands.

* Fix segfault.

* Handle PostInc operands.

* Reorder VecLayout enum to have no duplicate enum value.

* Handle PredicateAsCounter operands

* Handle ZPRasFPR operands

* Handle VectorIndex operands

* Handle UImm12Offset operands.

* Move reg suffix to enum val to single function.

* Handle SVERegOp operands

* Handle SVELogicalImm operands

* Handle SImm operand

* Handle PrefetchOp operands

* Handle Imm and ImmHex operands

* Handle GPR64as32 and GPR64x8 operands

* Add missing break

* Handle FPImm operand

* Handle ExtendedRegister opreand

* Handle CondCode operands

* Handle BTIHintOp operands

* Handle BarrierOption operands

* Handle BarrierXSOption

* Add not implemeted case again

* Handle ArithExtend operands

* Handle AdrpLabel and AlignedLabel operands

* Handle AMNoIndex operands

* Handle AddSubImm operands

* Handle MSRSystemRegisters and MRSSystemRegister operands

* Handle PSBHntOp and RPRFMOperand operands

* Remove unused variables

* Handle InverseCondCode operands

* Handle ImplicityTypedVectorList operands

* Handle ShiftedRegister operands

* Handle Shifter operands

* Handle SIMDType10Operand operands

* Handle SVCROp operands

* Handle SVEPattern operands

* Handle SVEVecLenSpecifier operands

* Handle SysCROperands

* Handle SysXzrPair operands

* Handle PState operands

* Handle VRegOperands

* Primt SME oeprands.

* Fix cs_operand.h include

* Rename arm64 -> aarch64 in python bindings.

* Add Python bindings for SH

* Fix ARM Python bindings (#2127)

* Restructure auto-sync update scripts.

* Move Helper functions to Updater dir

* Move requirements.txt

* Add basic ASUpdater.py

* Run black.

* Add inc file generater to updater

* Add option to select certain inc files fore generation.

* Enable clean build and implement patcher for inc files.

* Format config

* Patch main header files after inc generation.

* Implement clang-format function (unused yet, because it takes forever.)

* Copy generated inc files to arch dir

* Invert clean option (noramlly we need to clean the build dir.)

* Clearify arg doc

* Rename SystemRegister file for AArch64

* Centralize handling of path variables.

* Check if SystemOperands had to be generated before renaming on of its files.

* Replace class parameters by calling get_path

* Remove updater config which only contained paths.

* Add refactor option.

* Remove more path handling in the Configurator.

* Add translation step to updater.

* Fix includes after CppTranslator was moved into the Updater

* Remove updater config

* Fix several issue in the Configurator

* Fix file operations

* Remove addition argument from translator.

* Add Differ step to updater.

* Add path variable for arch_config

* Add diff step.

* Fix typo

* Introduce .clang-format path variable.

* Remove duplicate functions

* Add option to select update steps to execute.

* Check in write functions for write flag.

* Rename PatchMainHeader -> HeaderPatcher

* Move .gitignore

* Add README to vendor dir.

* Add all system operands to cstool output

* Update cstest with aarch64 changes

* Remove wb flag of aarch64 detail struct

* Set updates_flag after decoding

* Set writeback after decoding.

* Rename ARM64 -> AArch64

* Update printer and op mapping

* Exit normally

* Add AArch64 alias

* Fix some tmeplate function calls

* Fix flag check after rebase.

* Fix build by commentig unnused code.

* Add memory operand flag

* Handle memory operands printed via generic printOperand function.

* Handle UImm memory offsets

* Introduce MEM_REG and MEM_IMM op types

* Handle scaled memory immediates

* Check for op_count before checking for mem op at -1 index.

* Update memory operand flags.

* Pass imm/reg memory ops in set_imm/reg to set_mem.

* Add missing set_sme_operand call and fix assert.

* Remove CS_OP_MEM flag before entering switch.

* Preidcates are registers.

* Add shift info always to the previous operand

* Check for generic system regs

* Handle NumLanes = 0 LaneKind = q case

* Replace printImm call with normal print logic. Otherwise ops get added twice to detail.

* Handle FP operands in printOperand.

* Add access information to float operands.

* Rewrite SME matrix handling.

* Set correct SME layouts and allow for immediate range sme offsets.

* Handle cases of unknown system alias by setting their raw values

* Update cstool and header file with new SME offset handling

* Handle SME Tile lists.

* Fix build error in cstest

* Update MC tests for AArch64

* Handle TLBI operands and fix printing bug.

* Fix: Print signed value as signed.

* Add more system alias to detail.

* Remove duplicate hex prefix

* Set correct values for the register info

* Replace tabs with white spaces

* Move string append logic to own function.

* Set DecodeComplete = true before decoding (as originally in the LLVM code).

* Change type of feature argument, since only LLVM features are passed, not CS groups.

* Imitate lower_bound for the index table binary search.

* Remove trailing comments from test files.

* Print shift amount in decimal

* Save detail of shift alias instructions.

* Add extension details fot ext instruction alias

* Print LSB and width in decimal

* Fix LLVM bug. The feature check for V8_2a doesn't check if all features are enabled.

* Fix lower_bounds check.
For m == 0 we wrap around 0 of cause.

* Fix feature check. Add check for FeatureAll since it includes XS

* Operate on temporary MCInst when trying decoding.

* Add lower_bound behavior to IndexTypeStr binsearch.

* Fix MC tests which were incorrect because of missing FeatureAll check

* Add Alias handling for AArch64

* Update system operands with SYSIMM types and add additional sysop category.

* Add macros for meta programming (ARM64 <-> AArch64 selection).

* Fix union/struct confusion and add raw_value member to uninions.

* Allow to set Syntax and mode options for AArch64

* Fix build warning by using correct type

* Print shift value in decimal

* Add missing call to add_cs_detail.

* Update name map files with normalized names.

* Remove unused function

* Add check if detail should be filled.

* Fill detail for real instructions if only real detail is requested.

* Add always the extension.

* Make dir creation log message debug level

* Implement ADR immediate operand printer.

See: c3484b1fdc

* Check for flag registers beeing written and update flag.

* Move multiple CondCode helpers to aarch64.h because they are so freaking useful.

+ Print CC if it is EQ

* Fix incorrectly initialized CC and VectorLayout.

* Add LSL shift type for extensions.

* Fix case when shift amount is 0

* Fix post-index memory instructions.

* Pass raw immediate through getShiftValue to extract actual shift amount

* Setup AArch64 detail ops.

* Add flag for operands part of a list.

* Set vector indices for all relevant registers.

* Add missing call to add_cs_detail for postIncOperands

* Add ugly yet reliable way to determine post-index addressing mode

* Add support for old Capstone register alias.

* Remove leading space before some alias mnemonics.

* add AARCH64 to `cmake.sh`

* add HAS_AARCH64 to `cs.c`

* should probably just reference `cs_operand.h` in `aarch64.h`

* hint compiler at `AArch64_SYSREG` enum type for casting purposes

* update `Makefile` for AARCH64

leaves `CAPSTONE_HAS_ARM64` supported

* `testFeatureBits` platform function check

`testFeatureBits` should check if the platform function is visible first

* update tests to use AARCH64 convention

* hack: avoid enum casts for `MCInst` Values

Apple compiler really hates typecasting a enum, even if bounded from a unsigned. Lets set the raw_value directly

is a hack and needs proper review

* Check for present detail before accessing it.

* Add CS only groups

* Use general map ins_op type

* Fix build warning about str size computation.

* Disable warning about unitialized value for GCC 11.

Imm is initialized and the warning does not appear
in later versions.

* Use correct include guard for PPC

* Add missing requirements

* Update SystemOperand enums.

* Fix overlapping comparison warning

* Fix reachable assert where OpNum is not of type IMM

* Handle 0.0 operand for fcmp

* Fix incorrect variable passed.

* Fix for MacOS which doesn't know the warning and throws another one.

* Make getExtendEncoding static to fix build warning on MSVC.

* Fix build error: 'missing binary operator before token' by checking __GNUC__

* Add string search to add vector layout info.

* Add missing mem disponents of several ldr and str instructions.

* Add 0 immediates to several instructions.

* Rename v regs to q and d variant.

The cs_regname API can not pass the variant name of the register requested.
So we simply emit the default variant name.

* Fix incorrect enum value.

* Fix tests for system operands.

* Fix syntax issues in tests.

* Rename Arm64 -> AArch64 Python bindings.

* Fix Python bindings C structs.

* Fix generation of constants (ARMCC skipped because it starts with ARM)

* Update const files

* Remove -Wmaybe-uninitialized warning since it fails fuzz build

* Add missing comma

* Fix case

* Fix AArch64 Python bindings:

- Do not generate constants automatically (dscript is way too buggy).
- Update printing of details.

* Rename ARM64 -> AArch64 in test_corpus.py

* Rename test_arm64 -> test_aarch64

* Rename ARM-64 -> AArch64

* Fix diff CI test by disassembling AArch64 at former ARM64 place

* Fix several wrong types and remove unnecessary memebers from Python binding

* Fix: Same printing format of detail for cstool, test_ and test_*.py

* Fix: pass correct op index for mov alias with op[1] == reg wzr.

* Set prfm op manuall in case of unnown sysop. set_imm would add it to an memory operand wihtout base.

* Fix: If barrier ops are not set an assert is reached.

We fix it here by simply getting the immediate as the printing code does.

---------

Co-authored-by: Peace-Maker <peace-maker@wcfan.de>
Co-authored-by: Dayton <5340801+watbulb@users.noreply.github.com>
2023-11-15 12:12:14 +08:00
Rot127 926cfebd6b Architecture updater (auto-sync) - Updating PPC (#2013) 2023-09-05 12:24:59 +08:00
Bastian Koppelmann 489538fa05 Fixing TriCore disasm instructions (#2088) 2023-07-26 14:47:05 +08:00
Rot127 104f693c11 Architecture updater (auto-sync) - Updating ARM (#1949)
* Add auto-sync updater.

* Update Capstone core with auto-sync changes.

* Update ARM via auto-sync.

* Make changes to arch modules which are introduced by auto-sync.

* Update tests for ARM.

* Fix build warnings for make

* Remove meson.build

* Print shift amount in decimal

* Patch non LLVM register alias.

* Change type of immediate operand to unsiged (due to: #771)

* Replace all occurances of a register with its alias.

* Fix printing of signed imms

* Print rotate amount in decimal

* CHange imm type to int64_t to match LLVM imm type.

* Fix search for register names, by completing string first.

* Print ModImm operands always in decimal

* Use number format of previous capstone version.

* Correct implicit writes and update_flags according to SBit.

* Add missing test for RegImmShift

* Reverse incorrect comparision.

* Set shift information for move instructions.

* Set mem access for all memory operands

* Set subtracted flag if offset is negative.

* Add flag for post-index memory operands.

* Add detail op for BX_RET and MOVPCLR

* Use instruction post_index operand.

* Add VPOP and VPUSH as unique CS IDs.

* Add shifting info for MOVsr.

* Add TODOs.

* Add in LLVM hardcoded operands to detail.

* Move detail editing from InstPrinter to Mapping

* Formatting

* Add removed check.

* Add writeback register and constraints to RFEI instructions.

* Translate shift immediate

* Print negative immediates

* Remove duplicate invalid entry

* Add CS groups to instructions

* Fix write attriutes of stores.

* Add missing names of added instructions

* Fix LLVM bug

* Add more post_index flags

* http -> https

* Make generated functions static

* Remove tab prefix for alias instructions.

* Set ValidateMCOperand to NULL.

* Fix AddrMode3Operand operands

* Allow getting system and banked register name via API

* Add writeback to STC/LDC instructions.

* Fix (hopefully) last case where disp is negative and subtracted = true

* Remove accidentially introduced regressions
2023-07-19 17:56:27 +08:00
billow 568d179f85 Update tests and inc files
with llvm-capstone 78180b63f827ee38e23375e7a00825e848aa6956
2023-07-01 16:26:54 +08:00
billow a5bf3841b4 Add `#` prefix to tricore imm operand 2023-07-01 09:13:14 +08:00
Anton Kochkov 1befcbb723 Convert Tricore to Intel register syntax 2023-06-28 21:48:37 +08:00
billow 10a24a9a38 Add operands access support for TriCore 2023-05-30 12:27:38 +08:00
billow 06126191e3 Fix compile warning 2023-05-20 19:55:14 +08:00
billow 0fdff8dc33 Fix disassemble of `xor`
- update generate file using 78180b63f8
2023-05-18 07:29:02 +08:00
billow 6f44941806 Fix disp fill 2023-05-14 06:34:46 +08:00
billow b19a370f86 Update arch/TriCore/TriCoreInstPrinter.c
Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>
2023-05-13 03:38:27 +08:00
billow 35f151558f Update arch/TriCore/TriCoreInstPrinter.c
Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>
2023-05-13 03:38:21 +08:00
billow ec19bd9df2 Update arch/TriCore/TriCoreInstPrinter.c
Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>
2023-05-13 03:37:08 +08:00
billow 4ad9cb1b02 Refactor TriCoreInstPrinter.c 2023-05-13 03:01:24 +08:00
billow 44b8610297 Fix tricore disp print 2023-05-13 02:45:00 +08:00
billow b0f9097884 Fix tricore disp24 print 2023-05-13 02:29:26 +08:00
billow 404edd5772 Fix compilation warnings related to TriCore. (#2012)
* fix tricore compiler warn `-Wmissing-prototypes`

* include cstool.h
2023-05-09 20:46:10 +08:00
billow 114f1ad867 Upper all `inc` and fix 2023-05-01 22:52:47 +08:00
billow 2873d3b58c Fix tricore.h and remove `inc` folder 2023-04-25 09:24:07 +08:00
billow acc8c3fb13 Fix `print_insn_detail_tricore` and disp fill 2023-04-23 15:14:03 +08:00
billow 2c052afe3c Fix format error 2023-04-23 14:43:14 +08:00
billow 2785d31399 Format all .(c|h) code 2023-04-20 21:55:37 +08:00
billow 2919f94530 fix all tricore compile warnings 2023-04-20 09:22:25 +08:00
billow 26cb58dabc fix: support for TriCore call group mapping 2023-04-20 08:35:13 +08:00
billow a4118c4ec9 update TriCoreGenAsmWriter.inc 2023-04-14 00:36:16 +08:00
billow 008ef096d3 Update tricore `.inc` 2023-04-14 00:36:12 +08:00
billow b412f528c8 fix `TriCoreGenCSMappingInsnName.inc` 2023-04-14 00:36:11 +08:00
billow 36a975d8a2 fix `TRICORE_OP_MEM` 2023-04-14 00:36:11 +08:00
billow 2254e61515 cleanup 2023-04-14 00:36:10 +08:00
billow cf36371e5e fix `TriCore_getRegisterName` 2023-04-14 00:36:09 +08:00
billow 230ff6db56 fix tests 2023-04-14 00:36:08 +08:00
billow c78a086a55 fix `TRICORE_GENERIC` inst 2023-04-14 00:36:07 +08:00
billow d56c37ac07 fix tests 2023-04-14 00:36:06 +08:00
billow 2a7684d272 fix tests 2023-04-14 00:36:05 +08:00
billow e843a8df56 fix tests 2023-04-14 00:36:04 +08:00
billow dd04f4d98b Update TriCore instructions in TriCoreInstrInfo.td 2023-04-14 00:36:04 +08:00
billow 014c73de2e add tests 2023-04-14 00:36:03 +08:00
billow 3d2a56c2cd fix tc1.6.2 tests 2023-04-14 00:36:02 +08:00