6a4d27706a
x86: fix the pause instruction reported by @maijin in issue #298
2015-04-02 12:32:33 +08:00
d505d6d461
x86: initialize cs_x86.{xop_cc, eflags}
2015-04-01 01:30:34 +08:00
87d754dc3a
Merge branch 'next' of https://github.com/aquynh/capstone into next
2015-03-30 08:25:20 +08:00
228ec96de5
x86: LEA instruction should not access the second operand. bug reported by @chaplja
2015-03-30 08:24:12 +08:00
19ee2d10b3
inttypes.h fix
2015-03-29 21:16:38 +08:00
efffe787d1
Add new API and start to provide access information for instruction operands
...
- New API cs_regs_access() that provide registers being read & modified by instruction
- New field cs_x86_op.access provides access info (READ, WRITE) for each operand
- New field cs_x86.eflags provides EFLAGS affected by instruction
- Extend cs_detail.{regs_read, regs_write} from uint8_t to uint16_t type
2015-03-25 15:02:13 +08:00
5e5b1f5366
core: rename operand access symbols from CS_OP_* to CS_AC_*
2015-03-23 00:09:20 +08:00
5b93f59afe
x86: more fix for lots of OP_NOREG in insn_ops[]. also renamed it to OP_IGNORE
2015-03-21 01:35:14 +08:00
1271684973
x86: print interrupt number of INT instruction in positive form. bug reported by @pancake
2015-03-20 22:36:08 +08:00
8bb1f04bb8
x86: fix lots of issues with insn_op[], and move it to a separate file X86MappingInsnOp.inc
2015-03-20 17:18:01 +08:00
2c1b7f1398
x86: fix Immediate operand size when first register operand is embedded in mnemonic (CMP8i8). bug reported by @joelpx
2015-03-14 10:17:17 +08:00
09218a2dfd
x86: remove unsed field @prefixLocations of InternalInstruction struct
2015-03-11 11:29:33 +08:00
bcb75a2194
x86: F2 can be a part of instruction encoding, but not a prefix
2015-03-11 11:15:27 +08:00
914066be07
x86: CLI & STI are privileged instructions. issue reported by @pancake
2015-03-09 10:01:58 +08:00
0423562c42
x86: RDTSC is not a privilege instructions, but all VM instructions are
2015-03-09 09:57:51 +08:00
4dd0dcb9d4
add CS_GRP_PRIVILEGE group, and also add X86_GRP_PRIVILEGE group for bunch of X86 privileged instructions
2015-03-09 00:04:45 +08:00
bb5dccedfa
core: put insns[] into separate .inc files to make it easier to manage
2015-03-08 10:54:32 +08:00
d3d574ed05
x86: XCHG* do not implicitly access *AX registers (reduce mode)
2015-03-08 05:00:17 +08:00
8b8d762580
x86: XCHG* do not implicitly access *AX registers
2015-03-08 04:58:18 +08:00
78699e0ff8
x86: update insn_ops[]
2015-03-07 16:33:49 +08:00
e4ca35d561
x86: delete the fiction instruction X86_INS_VPCOM
2015-03-07 16:05:06 +08:00
7a94483452
x86: remove another fiction instruction VCMP
2015-03-07 14:37:59 +08:00
e402e021b8
x86: remove unreal instruction VPCMP
2015-03-07 14:33:40 +08:00
a81bf4247c
x86: add new field @xop_cc to struct @cs_x86
2015-03-07 13:37:32 +08:00
16f703efd8
x86: remove more abundant space at the end of instructions (ATT syntax)
2015-03-06 23:26:27 +08:00
a3c8505a13
x86: remove one extra space in ATT syntax
2015-03-06 23:18:34 +08:00
ca792b2bcb
x86: fix some groups X86_GRP* in insns[] in X86Mapping.c
2015-03-06 23:13:34 +08:00
dcbfc394ba
x86: fix ATT syntax
2015-03-06 22:48:00 +08:00
5a36377c7c
x86: add GRP_VM for some VMX instructions
2015-03-06 12:28:31 +08:00
3a1a77fa64
x86: reduce mode support for the upgraded core
2015-03-06 12:21:50 +08:00
cdc9e20a45
x86: add missing GRP_VM for some virtualization instructions
2015-03-06 11:24:25 +08:00
02a7675f7e
x86: cleanup
2015-03-06 09:12:26 +08:00
4c1d0970ca
x86: test [mem], reg
2015-03-06 09:11:25 +08:00
54d5071288
x86: update core. also update all the bindings Java, Ocaml & Python
2015-03-06 00:52:49 +08:00
bfcaba5851
2015
2015-03-04 17:45:23 +08:00
2c55b81f06
mips: fix conflict when merging with 'next' branch
2015-03-04 11:29:49 +08:00
6d2c6a7a97
Silencing Clang warning about losing precision
2015-03-04 11:26:49 +08:00
3973d8b11e
Silencing Clang warning bys casting values
...
Warnings were: "Implicit conversion loses integer precision: 'size_t' to 'cs_mode'/'cs_opt_value'"
2015-03-04 11:26:27 +08:00
c87ccd1b89
mips: fix bugs in the last update
2015-03-02 17:31:44 +08:00
96ee76fa2a
Merge branch 'next' of https://github.com/radare/capstone into test2
2015-02-28 08:29:21 +08:00
e84d2cd523
x86: allow prefixes to be positioned anywhere. this should fix the bug reported by Gabriel Quadros
2015-02-25 17:04:23 +08:00
651e3586d8
x86: update insn_ops[]
2015-02-24 22:00:11 +08:00
9c10ace558
Make pkg-config and source consistent with installation
2015-02-24 05:03:04 +01:00
e3bcbdb2fa
x86: REPNE can go with STOS/MOVS. bug reported by Gabriel Quadros
2015-02-13 11:26:21 +08:00
dfa396e6ff
x86: add the missing X86 instructions in X86_REDUCE mode in X86DisassemblerDecoder.c. bug reported by Julian Stecklina
2015-02-12 09:02:42 +08:00
4363911eb4
x86: fix operand size for 'CALL PTR [REG]'. bug reported by Gabriel Quadros
2015-02-10 00:21:00 +08:00
7ea921e539
x86: add work-in-progress mapping table on explicit operands access. this reused some code contributed by Vincent Bénony
2015-02-04 12:09:06 +08:00
f601fddc53
Merge branch 'next' of https://github.com/aquynh/capstone into python
2015-01-26 17:33:21 +01:00
e95a76611c
x86: remove some instructions unsupported in 3.x version
2015-01-13 14:35:43 +08:00
25525fb20c
x86: remove some instructions irrelevant for LOCK prefix in invalidPrefix()
2015-01-13 12:14:46 +08:00
Nguyen Anh Quynh