838b9aebd1
Fix missing-prototypes warnings ( #1348 )
2019-01-22 09:01:13 +08:00
d9b8079aba
Update SystemZ to LLVM commit 5ad902a6 ( #1306 )
2018-12-16 21:48:51 +08:00
afffa5d741
merge next to master
2018-07-20 12:36:50 +08:00
9b9844d276
Init cs_detail ( #1205 )
...
* Update init of cs_detail for AArch64
as @aquynh requested in #1125
* Update init of cs_detail for ARM
as @aquynh requested in #1125
* Update init of cs_detail for EVM
as @aquynh requested in #1125
* Update init of cs_detail for M680X
as @aquynh requested in #1125
* Update init of cs_detail for M68K
as @aquynh requested in #1125
* Update init of cs_detail for Mips
as @aquynh requested in #1125
* Update init of cs_detail for PowerPC
as @aquynh requested in #1125
* Update init of cs_detail for Sparc
as @aquynh requested in #1125
* Update init of cs_detail for SystemZ
as @aquynh requested in #1125
* Update init of cs_detail for TMS320C64x
as @aquynh requested in #1125
* Update init of cs_detail for XCore
as @aquynh requested in #1125
* Comment on init of cs_detail
* wrap long lines
2018-07-12 11:01:34 +07:00
22ead3e0bf
Constify backend data ( #1040 )
...
* Constify string literals
Use -Wwrite-strings to force string literals to be of
type "const char[]", then fix up all warning fallout.
* Constify common infrastructure
Step one in allowing backend data to be readonly.
Minimal changes to backends for now; just set all pointers
in common structs that aren't modified to const.
* Constify AArch64 backend
Section size changes within libcapstone.so are
-.rodata 602587
-.data.rel.ro 228416
-.data 1003746
+.rodata 769051
+.data.rel.ro 241120
+.data 824578
* Constify ARM backend
Section size changes within libcapstone.so are
-.rodata 769051
-.data.rel.ro 241120
-.data 824578
+.rodata 959835
+.data.rel.ro 245120
+.data 629506
* Constify Mips backend
Section size changes within libcapstone.so are
-.rodata 959835
-.data.rel.ro 245120
-.data 629506
+.rodata 1069851
+.data.rel.ro 256416
+.data 508194
* Constify PowerPC backend
Section size changes within libcapstone.so are
-.rodata 1069851
-.data.rel.ro 256416
-.data 508194
+.rodata 1142715
+.data.rel.ro 272224
+.data 419490
* Constify Sparc backend
Section size changes within libcapstone.so are
-.rodata 1142715
-.data.rel.ro 272224
-.data 419490
+.rodata 1175227
+.data.rel.ro 277536
+.data 381666
* Constify SystemZ backend
Section size changes within libcapstone.so are
-.rodata 1175227
-.data.rel.ro 277536
-.data 381666
+.rodata 1221883
+.data.rel.ro 278016
+.data 334498
* Constify X86 backend
Section size changes within libcapstone.so are
-.rodata 1221883
-.data.rel.ro 278016
-.data 334498
+.rodata 1533531
+.data.rel.ro 281184
+.data 19714
* Constify XCore backend
Section size changes within libcapstone.so are
-.rodata 1533531
-.data.rel.ro 281184
-.data 19714
+.rodata 1553026
+.data.rel.ro 281280
+.data 40
2017-10-22 08:45:40 +08:00
7d5266d64c
sparc, systemz, xcore: getInstruction() should return boolean instead of DecodeStatus
2015-03-10 15:22:06 +08:00
a7837a4ae3
sparc, systemz, xcore: getInstruction() should return boolean instead of DecodeStatus
2015-03-10 15:20:20 +08:00
bfcaba5851
2015
2015-03-04 17:45:23 +08:00
603a32e968
systemz: upgrade core
2015-03-04 13:58:07 +08:00
0c07cc9b06
zero-out instruction details, mnemonic & op_str so cs_insn doesnt have garbage in Diet mode
2014-08-27 22:31:54 +08:00
39d6b2f066
systemz: initialize detail->sysz in SystemZ_getInstruction. bug reported by Ben Nagy
2014-07-09 11:26:53 +08:00
cae09bf543
replace offset_of with offsetof from stddef.h
2014-06-17 14:58:39 +08:00
7062988855
systemz: use CreateImm0() & CreateReg0() to create MCOperand* to avoid using malloc/free
2014-06-16 13:09:15 +08:00
69582d71ae
initialize cs_insn.detail by properly zero-out right members for each arch
2014-06-09 17:50:01 +07:00
8598a219f3
enable arch code from source with CAPSTONE_HAS_* for MSVC to pick up
2014-05-14 11:26:41 +08:00
638835a1d5
fix some warnings reported by MSVC
2014-05-12 15:15:32 +08:00
958927eb56
clean up after the last removal of SubtargetFeature.h
2014-05-08 22:59:28 +08:00
a5ffdc3a80
x86: properly handle LOCK/REP in the core, so remove buch of hacks
2014-05-07 08:25:24 +08:00
2cff6f61fc
x86: handle instructions with LOCK/REP/REPNE prefix after other prefixes. bear with this until we have a better approach
2014-04-28 11:19:44 +08:00
48a14ca4ce
add SystemZ arch
2014-03-23 08:35:45 +08:00
Marius Melzer