6cfbd06b61
arch/M68k: do not return reg_name if beyond limits ( #1219 )
...
* arch/M68k: do not return reg_name if beyond limits
(patch coming from radare2)
* arch: checks index when returning reg names
2018-07-24 16:25:47 +08:00
afffa5d741
merge next to master
2018-07-20 12:36:50 +08:00
22ead3e0bf
Constify backend data ( #1040 )
...
* Constify string literals
Use -Wwrite-strings to force string literals to be of
type "const char[]", then fix up all warning fallout.
* Constify common infrastructure
Step one in allowing backend data to be readonly.
Minimal changes to backends for now; just set all pointers
in common structs that aren't modified to const.
* Constify AArch64 backend
Section size changes within libcapstone.so are
-.rodata 602587
-.data.rel.ro 228416
-.data 1003746
+.rodata 769051
+.data.rel.ro 241120
+.data 824578
* Constify ARM backend
Section size changes within libcapstone.so are
-.rodata 769051
-.data.rel.ro 241120
-.data 824578
+.rodata 959835
+.data.rel.ro 245120
+.data 629506
* Constify Mips backend
Section size changes within libcapstone.so are
-.rodata 959835
-.data.rel.ro 245120
-.data 629506
+.rodata 1069851
+.data.rel.ro 256416
+.data 508194
* Constify PowerPC backend
Section size changes within libcapstone.so are
-.rodata 1069851
-.data.rel.ro 256416
-.data 508194
+.rodata 1142715
+.data.rel.ro 272224
+.data 419490
* Constify Sparc backend
Section size changes within libcapstone.so are
-.rodata 1142715
-.data.rel.ro 272224
-.data 419490
+.rodata 1175227
+.data.rel.ro 277536
+.data 381666
* Constify SystemZ backend
Section size changes within libcapstone.so are
-.rodata 1175227
-.data.rel.ro 277536
-.data 381666
+.rodata 1221883
+.data.rel.ro 278016
+.data 334498
* Constify X86 backend
Section size changes within libcapstone.so are
-.rodata 1221883
-.data.rel.ro 278016
-.data 334498
+.rodata 1533531
+.data.rel.ro 281184
+.data 19714
* Constify XCore backend
Section size changes within libcapstone.so are
-.rodata 1533531
-.data.rel.ro 281184
-.data 19714
+.rodata 1553026
+.data.rel.ro 281280
+.data 40
2017-10-22 08:45:40 +08:00
9f6b28cc0b
Add name to relative branch group in supported architectures. ( #982 )
2017-08-01 16:49:43 +08:00
952d534d1b
Patch for issue #842
...
The SETEND instruction is a 16 bit Thumb instruction which is included
in T variants of ARMv6 and above, but is not available in M-Class cores
(see ARM Compiler toolchain Assembler Reference Ver 5.0).
To be consistent with other similar instructions its group flags have
been updated to be:
{ARM_GRP_THUMB, ARM_GRP_V6, ARM_GRP_NOTMCLASS,0}
2017-01-18 17:35:42 +00:00
a0f082d32c
arm: fix issue #744
2016-08-13 13:25:52 +08:00
45e5eab646
port Windows driver support
2016-05-11 21:48:32 -07:00
c7dcf9c9a0
Fix classification of ARM jump instructions
...
All jump instructions have been classified based on the direct
and indirect_branch flags instead of explicitly stating ARM_GRP_JUMP.
2015-12-17 12:36:48 +01:00
4caced62e6
arm: add missing group string for CALL & INT. bug reported by Ben Nagy
2015-05-27 16:14:49 +07:00
478595dc3a
arm: remove ASRS, LSRS, SUBS & MOVS from mapping table insns[]. backported from the 'next' branch, but do not really remove these 'dead' instructions for compatibility reason
2015-05-08 15:08:35 +08:00
5dba2c3742
arm: BLX should read PC & modify LR registers. bug reported by Zach Riggle
2015-05-08 15:04:09 +08:00
1182d25759
simplify ARCH_group_name() by using lookup table as suggested by @learn_more. also added the missing group name for GRP_PRIVILEGE
2015-04-27 12:13:34 +08:00
d2f47d065f
Remove enum for ASRS, LSRS, SUBS and MOVS
...
These instructions are now disassembled ASR, LSR, SUB and MOV, with the "update_flags" bit set.
2015-04-17 11:42:45 +02:00
29f777bdd9
arm: support cs_regs_access() API
2015-04-07 11:59:26 +08:00
efffe787d1
Add new API and start to provide access information for instruction operands
...
- New API cs_regs_access() that provide registers being read & modified by instruction
- New field cs_x86_op.access provides access info (READ, WRITE) for each operand
- New field cs_x86.eflags provides EFLAGS affected by instruction
- Extend cs_detail.{regs_read, regs_write} from uint8_t to uint16_t type
2015-03-25 15:02:13 +08:00
5e5b1f5366
core: rename operand access symbols from CS_OP_* to CS_AC_*
2015-03-23 00:09:20 +08:00
c79a8a03c4
arm: fix lots of issues with insn_op[], and move it to a separate file ARMMappingInsnOp.inc
2015-03-22 13:39:54 +08:00
e17124356e
arm: add the missing Virtualization group to group_name_maps[]. bug reported by Coverity
2015-03-12 00:26:08 +08:00
bb5dccedfa
core: put insns[] into separate .inc files to make it easier to manage
2015-03-08 10:54:32 +08:00
8e343885be
arm: update insn_ops[]
2015-03-07 16:38:35 +08:00
bfcaba5851
2015
2015-03-04 17:45:23 +08:00
d1fc2bd3b9
arm: update core
2015-03-03 16:26:32 +08:00
9f4b373f56
arm: fix some instructions in insn_ops[]
2015-02-24 18:38:56 +08:00
4c5039582b
arm: fix bugs in the last commit where some instructions in insn_ops[] do not update CPSR
2015-02-24 09:19:25 +08:00
10434df006
arm: some instructions update status flags in insns_ops[]
2015-02-24 08:58:22 +08:00
760c5486d2
arm: fix some more Thumb & vectored instructions in insn_ops[]
2015-02-24 00:16:03 +08:00
cea230f867
arm: fix some Thumb instructions in insn_ops[]
2015-02-23 23:56:40 +08:00
d0f96df26d
arm: add insn_ops[] (temporarily disable)
2015-02-23 23:50:15 +08:00
f2157deacc
arm: in Thumb mode, ADC & SBC do not update flags. bug reported by @jabba2989
2015-01-13 22:18:05 +08:00
07526e989b
arm: Thumb BL & BLX read ARM_REG_PC instead of ARM_REG_SP.
2014-12-30 10:47:04 +08:00
db684b2398
arm: BL & BLX do not read SP, but PC register. issue reported by Der Rek
2014-12-27 16:26:42 +08:00
c2ea812ea7
fix cs_group_name() after the change on generic group ids
2014-10-31 15:36:19 +08:00
11f8e7c596
arm: B, BL, BX, BLX, BXJ belong to ARM_GRP_JUMP group. issue reported by @nanomad
2014-10-21 17:35:34 +08:00
9235fdc504
arm: The Thumb2 ldrexd and strexd instructions are not defined for M-class architectures
2014-09-30 07:44:50 +08:00
d7e42b7d36
rename all the constants marking ending from _MAX to _ENDING. this also updates Java/Python/Ocaml bindings accordingly
2014-09-29 17:15:25 +08:00
d442fbc06e
arm: t2BXJ also belongs to groups ARM_GRP_NOTMCLASS & ARM_GRP_PREV8
2014-09-26 10:38:29 +08:00
04d9f8ee17
arm: update core with a lot more details provided in detail mode now. update Python & Java bindings to reflect the core's changes
2014-09-01 23:27:24 +08:00
b52f11f636
arm: update core. this added a new instruction UDF. also updated Python+Java bindings accordingly
2014-08-13 22:38:15 +08:00
26dfbc6677
fix indentation introduced by the latest merge. also move test_arm_regression.c into suite/arm/ and add Makefile for it
2014-07-31 18:24:51 +08:00
5d8067822b
Merge branch 'next' of https://github.com/flyingsymbols/capstone into arm
2014-07-31 15:36:13 +08:00
298d413bbc
* added a test file to suite for testing invalid and valid instruction sequences
...
* fixed and added a test for a thumb-2 invalid sequence that was incorrectly allowed before these changes (pop.w with sp argument included)
* fixed and added a test for a blx from thumb to ARM that had its immediate argument incorrect (misaligned)
* eliminated some warnings by explicitly casting so I could turn on
treat warnings as errors locally
General notes:
* probably worth turning on treat all warnings as errors in the msvc project files, had a subtle bug that resulted from a missing declaration causing differences in dll and static compilation modes
( code was working incorrectly in dll form because of missing declaration in arch/ARM/ARMMapping.h for new function ARM_blx_to_arm_mode. Something about the linking was confusing ld when making the dll, and the resulting offsets were wonky (e.g. the added ble test would show up as #0x1fc instead of #0x1fe like it should have )
* the invalid pop was being treated as a soft fail which then gets coerced
to a success because it is != MCDisassembler_Fail in Thumb_getInstruction
what are the semantics of a soft fail? Maybe we should be able to set up
whether or not we want a soft fail to be a real fail in the csh struct?
2014-07-15 04:33:40 -04:00
650f96ce43
add new API cs_group_name() to return group name in string, given the group id
2014-07-08 08:59:27 +08:00
73bbbb3800
arm: add ASRS, LSRS, VCLE, VCLT instructions. update Python & Java bindings at the same time
2014-06-17 13:29:54 +08:00
04f2ec6d0f
cleanup redundant headers included
2014-05-27 10:39:04 +08:00
8598a219f3
enable arch code from source with CAPSTONE_HAS_* for MSVC to pick up
2014-05-14 11:26:41 +08:00
d27b0155ef
arm: add BLX_pred into the list of relative branch instructions
2014-05-09 17:34:54 +08:00
bc80b3dc24
arm: fix some more Thumb relative branch instructions. bug reported by Giovanni Nanomad Condello
2014-05-09 17:31:41 +08:00
d43187d4f9
arm: BLXi is another relative branch instruction to be fixed. bug reported by Giovanni Nanomad Condello
2014-05-09 07:02:51 +08:00
49a1cb374c
arm: fix another relative jump issue. bug reported by Giovanni Nanomad Condello
2014-05-08 23:42:06 +08:00
79e1dcb5f1
arm: update target branch having relative offset. issue reported by Giovanni Condello
2014-05-07 14:12:50 +08:00
Riccardo Schirone