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DynamicTablesPkg: Enhance X64 PCIe SSDT _CRS generation

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X64 platforms supports WordIo and uncached PCIe resources.
Hence, include WordIo and uncached PCIe resources in _CRS.

Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
This commit is contained in:
Abdul Lateef Attar
2025-08-07 09:53:43 +00:00
committed by mergify[bot]
parent cec2c6bbcc
commit 0a3d688b1b
3 changed files with 83 additions and 0 deletions
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5
DynamicTablesPkg/Include/ArchCommonNameSpaceObjects.h
View File

@ -200,6 +200,11 @@ typedef struct CmArchCommonPciAddressMapInfo {
- 1: I/O Space
- 2: 32-bit-address Memory Space
- 3: 64-bit-address Memory Space
Custom values:
- 4: Word I/O Space
- 5: 32-bit-address uncache Memory Space
- 6: 64-bit-address uncache Memory Space
*/
UINT8 SpaceCode;

71
DynamicTablesPkg/Library/Acpi/Common/AcpiSsdtPcieLib/SsdtPcieGenerator.c
View File

@ -2,6 +2,7 @@
SSDT Pcie Table Generator.
Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.<BR>
Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@ -608,7 +609,77 @@ GeneratePciCrs (
NULL
);
break;
case PCI_SS_IO_WORD:
ASSERT ((AddrMapInfo->PciAddress & ~MAX_UINT16) == 0);
ASSERT (((AddrMapInfo->PciAddress + AddrMapInfo->AddressSize - 1) & ~MAX_UINT16) == 0);
ASSERT (((Translation ? AddrMapInfo->CpuAddress - AddrMapInfo->PciAddress : 0) & ~MAX_UINT16) == 0);
ASSERT ((AddrMapInfo->AddressSize & ~MAX_UINT16) == 0);
Status = AmlCodeGenRdWordIo (
FALSE,
TRUE,
TRUE,
IsPosDecode,
3,
0,
AddrMapInfo->PciAddress & MAX_UINT16,
(AddrMapInfo->PciAddress + AddrMapInfo->AddressSize - 1) & MAX_UINT16,
(Translation ? AddrMapInfo->CpuAddress - AddrMapInfo->PciAddress : 0) & MAX_UINT16,
AddrMapInfo->AddressSize & MAX_UINT16,
0,
NULL,
TRUE,
FALSE,
CrsNode,
NULL
);
break;
case PCI_SS_M32_UC:
ASSERT ((AddrMapInfo->PciAddress & ~MAX_UINT32) == 0);
ASSERT (((AddrMapInfo->PciAddress + AddrMapInfo->AddressSize - 1) & ~MAX_UINT32) == 0);
ASSERT (((Translation ? AddrMapInfo->CpuAddress - AddrMapInfo->PciAddress : 0) & ~MAX_UINT32) == 0);
ASSERT ((AddrMapInfo->AddressSize & ~MAX_UINT32) == 0);
Status = AmlCodeGenRdDWordMemory (
FALSE,
IsPosDecode,
TRUE,
TRUE,
AmlMemoryNonCacheable,
TRUE,
0,
(UINT32)(AddrMapInfo->PciAddress),
(UINT32)(AddrMapInfo->PciAddress + AddrMapInfo->AddressSize - 1),
(UINT32)(Translation ? AddrMapInfo->CpuAddress - AddrMapInfo->PciAddress : 0),
(UINT32)(AddrMapInfo->AddressSize),
0,
NULL,
AmlAddressRangeMemory,
TRUE,
CrsNode,
NULL
);
break;
case PCI_SS_M64_UC:
Status = AmlCodeGenRdQWordMemory (
FALSE,
IsPosDecode,
TRUE,
TRUE,
AmlMemoryNonCacheable,
TRUE,
0,
AddrMapInfo->PciAddress,
AddrMapInfo->PciAddress + AddrMapInfo->AddressSize - 1,
Translation ? AddrMapInfo->CpuAddress - AddrMapInfo->PciAddress : 0,
AddrMapInfo->AddressSize,
0,
NULL,
AmlAddressRangeMemory,
TRUE,
CrsNode,
NULL
);
break;
default:
Status = EFI_INVALID_PARAMETER;
} // switch

7
DynamicTablesPkg/Library/Acpi/Common/AcpiSsdtPcieLib/SsdtPcieGenerator.h
View File

@ -2,6 +2,8 @@
SSDT Pcie Table Generator.
Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Reference(s):
@ -25,6 +27,11 @@
#define PCI_SS_M32 2
#define PCI_SS_M64 3
/* Custom values. */
#define PCI_SS_IO_WORD 4
#define PCI_SS_M32_UC 5
#define PCI_SS_M64_UC 6
/** Maximum Pci root complexes supported by this generator.
Note: This is not a hard limitation and can be extended if needed.