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MdePkg: Remove ARM32 Support
edk2 is dropping support for the ARM32 architecture. This commit removes the remaining ARM32 code from MdePkg. This also removes irrelevant VALID_ARCHITECTURES comments from infs that are not arch specific. Signed-off-by: Oliver Smith-Denny <osde@microsoft.com>
This commit is contained in:
Oliver Smith-Denny
committed by
mergify[bot]
mergify[bot]
parent
c7ada42ce4
commit
84c026111c
@ -1,122 +0,0 @@
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/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef ARM_V7_H_
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#define ARM_V7_H_
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#include <Arm/AArch32Mmu.h>
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// ARM Interrupt ID in Exception Table
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#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_ARM_IRQ
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// ID_PFR1 - ARM Processor Feature Register 1 definitions
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#define ARM_PFR1_SEC (0xFUL << 4)
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#define ARM_PFR1_TIMER (0xFUL << 16)
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#define ARM_PFR1_GIC (0xFUL << 28)
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// Domain Access Control Register
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#define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))
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#define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))
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#define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a)))
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#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))
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#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))
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// CPSR - Coprocessor Status Register definitions
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#define CPSR_MODE_USER 0x10
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#define CPSR_MODE_FIQ 0x11
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#define CPSR_MODE_IRQ 0x12
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#define CPSR_MODE_SVC 0x13
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#define CPSR_MODE_ABORT 0x17
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#define CPSR_MODE_HYP 0x1A
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#define CPSR_MODE_UNDEFINED 0x1B
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#define CPSR_MODE_SYSTEM 0x1F
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#define CPSR_MODE_MASK 0x1F
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#define CPSR_ASYNC_ABORT (1 << 8)
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#define CPSR_IRQ (1 << 7)
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#define CPSR_FIQ (1 << 6)
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// CPACR - Coprocessor Access Control Register definitions
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#define CPACR_CP_DENIED(cp) 0x00
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#define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)
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#define CPACR_CP_FULL(cp) ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)
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#define CPACR_ASEDIS (1 << 31)
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#define CPACR_D32DIS (1 << 30)
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#define CPACR_CP_FULL_ACCESS 0x0FFFFFFF
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// NSACR - Non-Secure Access Control Register definitions
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#define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF)
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#define NSACR_NSD32DIS (1 << 14)
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#define NSACR_NSASEDIS (1 << 15)
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#define NSACR_PLE (1 << 16)
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#define NSACR_TL (1 << 17)
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#define NSACR_NS_SMP (1 << 18)
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#define NSACR_RFR (1 << 19)
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// SCR - Secure Configuration Register definitions
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#define SCR_NS (1 << 0)
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#define SCR_IRQ (1 << 1)
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#define SCR_FIQ (1 << 2)
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#define SCR_EA (1 << 3)
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#define SCR_FW (1 << 4)
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#define SCR_AW (1 << 5)
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// MIDR - Main ID Register definitions
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#define ARM_CPU_TYPE_SHIFT 4
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#define ARM_CPU_TYPE_MASK 0xFFF
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#define ARM_CPU_TYPE_AEMV8 0xD0F
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#define ARM_CPU_TYPE_A53 0xD03
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#define ARM_CPU_TYPE_A57 0xD07
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#define ARM_CPU_TYPE_A15 0xC0F
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#define ARM_CPU_TYPE_A12 0xC0D
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#define ARM_CPU_TYPE_A9 0xC09
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#define ARM_CPU_TYPE_A7 0xC07
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#define ARM_CPU_TYPE_A5 0xC05
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#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )
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#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))
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#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)
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VOID
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EFIAPI
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ArmEnableSWPInstruction (
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VOID
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);
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UINTN
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EFIAPI
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ArmReadCbar (
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VOID
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);
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UINTN
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EFIAPI
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ArmReadTpidrurw (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteTpidrurw (
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UINTN Value
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);
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UINT32
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EFIAPI
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ArmReadNsacr (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteNsacr (
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IN UINT32 Nsacr
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);
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#endif // ARM_V7_H_
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@ -1,216 +0,0 @@
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/** @file
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*
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* Copyright (c) 2011-2013, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#ifndef ARMV7_MMU_H_
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#define ARMV7_MMU_H_
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#define TTBR_NOT_OUTER_SHAREABLE BIT5
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#define TTBR_RGN_OUTER_NON_CACHEABLE 0
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#define TTBR_RGN_OUTER_WRITE_BACK_ALLOC BIT3
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#define TTBR_RGN_OUTER_WRITE_THROUGH BIT4
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#define TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC (BIT3|BIT4)
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#define TTBR_SHAREABLE BIT1
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#define TTBR_NON_SHAREABLE 0
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#define TTBR_INNER_CACHEABLE BIT0
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#define TTBR_INNER_NON_CACHEABLE 0
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#define TTBR_RGN_INNER_NON_CACHEABLE 0
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#define TTBR_RGN_INNER_WRITE_BACK_ALLOC BIT6
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#define TTBR_RGN_INNER_WRITE_THROUGH BIT0
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#define TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC (BIT0|BIT6)
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#define TTBR_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
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#define TTBR_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
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#define TTBR_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_INNER_NON_CACHEABLE )
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#define TTBR_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
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#define TTBR_MP_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_RGN_INNER_WRITE_THROUGH | TTBR_SHAREABLE)
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#define TTBR_MP_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC | TTBR_SHAREABLE)
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#define TTBR_MP_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_RGN_INNER_NON_CACHEABLE )
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#define TTBR_MP_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_RGN_INNER_WRITE_BACK_ALLOC | TTBR_SHAREABLE)
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#define TRANSLATION_TABLE_SECTION_COUNT 4096
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#define TRANSLATION_TABLE_SECTION_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)
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#define TRANSLATION_TABLE_SECTION_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)
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#define TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK (TRANSLATION_TABLE_SECTION_ALIGNMENT - 1)
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#define TRANSLATION_TABLE_PAGE_COUNT 256
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#define TRANSLATION_TABLE_PAGE_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)
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#define TRANSLATION_TABLE_PAGE_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)
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#define TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK (TRANSLATION_TABLE_PAGE_ALIGNMENT - 1)
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#define TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(table, address) ((UINT32 *)(table) + (((UINTN)(address)) >> 20))
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// Translation table descriptor types
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#define TT_DESCRIPTOR_SECTION_TYPE_MASK ((1UL << 18) | (3UL << 0))
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#define TT_DESCRIPTOR_SECTION_TYPE_FAULT (0UL << 0)
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#define TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE (1UL << 0)
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#define TT_DESCRIPTOR_SECTION_TYPE_SECTION ((0UL << 18) | (2UL << 0))
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#define TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION ((1UL << 18) | (2UL << 0))
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#define TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Desc) (((Desc) & 3UL) == TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE)
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// Translation table descriptor types
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#define TT_DESCRIPTOR_PAGE_TYPE_MASK (1UL << 1)
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#define TT_DESCRIPTOR_PAGE_TYPE_FAULT (0UL << 1)
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#define TT_DESCRIPTOR_PAGE_TYPE_PAGE (1UL << 1)
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// Section descriptor definitions
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#define TT_DESCRIPTOR_SECTION_SIZE (0x00100000)
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#define TT_DESCRIPTOR_SECTION_NS_MASK (1UL << 19)
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#define TT_DESCRIPTOR_SECTION_NS (1UL << 19)
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#define TT_DESCRIPTOR_SECTION_NG_MASK (1UL << 17)
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#define TT_DESCRIPTOR_SECTION_NG_GLOBAL (0UL << 17)
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#define TT_DESCRIPTOR_SECTION_NG_LOCAL (1UL << 17)
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#define TT_DESCRIPTOR_PAGE_NG_MASK (1UL << 11)
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#define TT_DESCRIPTOR_PAGE_NG_GLOBAL (0UL << 11)
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#define TT_DESCRIPTOR_PAGE_NG_LOCAL (1UL << 11)
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#define TT_DESCRIPTOR_SECTION_S_MASK (1UL << 16)
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#define TT_DESCRIPTOR_SECTION_S_NOT_SHARED (0UL << 16)
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#define TT_DESCRIPTOR_SECTION_S_SHARED (1UL << 16)
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#define TT_DESCRIPTOR_PAGE_S_MASK (1UL << 10)
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#define TT_DESCRIPTOR_PAGE_S_NOT_SHARED (0UL << 10)
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#define TT_DESCRIPTOR_PAGE_S_SHARED (1UL << 10)
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#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (1UL << 11))
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#define TT_DESCRIPTOR_SECTION_AP_NO_RW ((0UL << 15) | (0UL << 11))
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#define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (1UL << 11))
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#define TT_DESCRIPTOR_SECTION_AP_NO_RO ((1UL << 15) | (0UL << 11))
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#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (1UL << 11))
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#define TT_DESCRIPTOR_SECTION_AF (1UL << 10)
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#define TT_DESCRIPTOR_PAGE_AP_MASK ((1UL << 9) | (1UL << 5))
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#define TT_DESCRIPTOR_PAGE_AP_NO_RW ((0UL << 9) | (0UL << 5))
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#define TT_DESCRIPTOR_PAGE_AP_RW_RW ((0UL << 9) | (1UL << 5))
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#define TT_DESCRIPTOR_PAGE_AP_NO_RO ((1UL << 9) | (0UL << 5))
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#define TT_DESCRIPTOR_PAGE_AP_RO_RO ((1UL << 9) | (1UL << 5))
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#define TT_DESCRIPTOR_PAGE_AF (1UL << 4)
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#define TT_DESCRIPTOR_SECTION_XN_MASK (0x1UL << 4)
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#define TT_DESCRIPTOR_PAGE_XN_MASK (0x1UL << 0)
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#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2))
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#define TT_DESCRIPTOR_SECTION_CACHEABLE_MASK (1UL << 3)
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#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))
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#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))
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#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))
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#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))
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#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))
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#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))
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#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))
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#define TT_DESCRIPTOR_PAGE_SIZE (0x00001000)
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#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK ((3UL << 6) | (1UL << 3) | (1UL << 2))
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#define TT_DESCRIPTOR_PAGE_CACHEABLE_MASK (1UL << 3)
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#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 6) | (0UL << 3) | (0UL << 2))
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#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 6) | (0UL << 3) | (1UL << 2))
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#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 6) | (1UL << 3) | (0UL << 2))
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#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 6) | (1UL << 3) | (1UL << 2))
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#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 6) | (0UL << 3) | (0UL << 2))
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#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 6) | (1UL << 3) | (1UL << 2))
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#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 6) | (0UL << 3) | (0UL << 2))
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#define TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_AP_MASK) >> 6) & TT_DESCRIPTOR_PAGE_AP_MASK)
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#define TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_NG_MASK) >> 6) & TT_DESCRIPTOR_PAGE_NG_MASK)
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#define TT_DESCRIPTOR_CONVERT_TO_PAGE_S(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_S_MASK) >> 6) & TT_DESCRIPTOR_PAGE_S_MASK)
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#define TT_DESCRIPTOR_CONVERT_TO_PAGE_AF(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_AF) >> 6) & TT_DESCRIPTOR_PAGE_AF)
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#define TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_XN_MASK) >> 4) & TT_DESCRIPTOR_PAGE_XN_MASK)
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#define TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(Desc) ((((Desc) & (0x3 << 12)) >> 6) | (Desc & (0x3 << 2)))
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#define TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(Desc) ((((Desc) & TT_DESCRIPTOR_PAGE_AP_MASK) << 6) & TT_DESCRIPTOR_SECTION_AP_MASK)
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#define TT_DESCRIPTOR_CONVERT_TO_SECTION_S(Desc) ((((Desc) & TT_DESCRIPTOR_PAGE_S_MASK) << 6) & TT_DESCRIPTOR_SECTION_S_MASK)
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#define TT_DESCRIPTOR_CONVERT_TO_SECTION_AF(Desc) ((((Desc) & TT_DESCRIPTOR_PAGE_AF) << 6) & TT_DESCRIPTOR_SECTION_AF)
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#define TT_DESCRIPTOR_CONVERT_TO_SECTION_XN(Desc) ((((Desc) & TT_DESCRIPTOR_PAGE_XN_MASK) << 4) & TT_DESCRIPTOR_SECTION_XN_MASK)
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#define TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(Desc) ((((Desc) & (0x3 << 6)) << 6) | (Desc & (0x3 << 2)))
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#define TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK (TT_DESCRIPTOR_SECTION_NS_MASK | TT_DESCRIPTOR_SECTION_NG_MASK | \
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TT_DESCRIPTOR_SECTION_S_MASK | TT_DESCRIPTOR_SECTION_AP_MASK | \
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TT_DESCRIPTOR_SECTION_AF | \
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TT_DESCRIPTOR_SECTION_XN_MASK | TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK)
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#define TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK (TT_DESCRIPTOR_PAGE_NG_MASK | TT_DESCRIPTOR_PAGE_S_MASK | \
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TT_DESCRIPTOR_PAGE_AP_MASK | TT_DESCRIPTOR_PAGE_XN_MASK | \
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TT_DESCRIPTOR_PAGE_AF | \
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TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK)
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#define TT_DESCRIPTOR_SECTION_DOMAIN_MASK (0x0FUL << 5)
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#define TT_DESCRIPTOR_SECTION_DOMAIN(a) (((a) & 0x0FUL) << 5)
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#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK (0xFFF00000)
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#define TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK (0xFFFFFC00)
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#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)
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#define TT_DESCRIPTOR_SECTION_BASE_SHIFT 20
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#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK (0xFFFFF000)
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#define TT_DESCRIPTOR_PAGE_INDEX_MASK (0x000FF000)
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#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK)
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#define TT_DESCRIPTOR_PAGE_BASE_SHIFT 12
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#define TT_DESCRIPTOR_SECTION_DEFAULT (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
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TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
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TT_DESCRIPTOR_SECTION_S_SHARED | \
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TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
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TT_DESCRIPTOR_SECTION_AP_RW_RW | \
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TT_DESCRIPTOR_SECTION_AF)
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#define TT_DESCRIPTOR_SECTION_WRITE_BACK (TT_DESCRIPTOR_SECTION_DEFAULT | \
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TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)
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#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH (TT_DESCRIPTOR_SECTION_DEFAULT | \
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TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)
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#define TT_DESCRIPTOR_SECTION_DEVICE (TT_DESCRIPTOR_SECTION_DEFAULT | \
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TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE)
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#define TT_DESCRIPTOR_SECTION_UNCACHED (TT_DESCRIPTOR_SECTION_DEFAULT | \
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TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)
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#define TT_DESCRIPTOR_PAGE_WRITE_BACK (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
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TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
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TT_DESCRIPTOR_PAGE_S_SHARED | \
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TT_DESCRIPTOR_PAGE_AP_RW_RW | \
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TT_DESCRIPTOR_PAGE_AF | \
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TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC)
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#define TT_DESCRIPTOR_PAGE_WRITE_THROUGH (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
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TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
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TT_DESCRIPTOR_PAGE_S_SHARED | \
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TT_DESCRIPTOR_PAGE_AP_RW_RW | \
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TT_DESCRIPTOR_PAGE_AF | \
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TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)
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#define TT_DESCRIPTOR_PAGE_DEVICE (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
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TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
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TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \
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TT_DESCRIPTOR_PAGE_AP_RW_RW | \
|
||||
TT_DESCRIPTOR_PAGE_AF | \
|
||||
TT_DESCRIPTOR_PAGE_XN_MASK | \
|
||||
TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE)
|
||||
#define TT_DESCRIPTOR_PAGE_UNCACHED (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
|
||||
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
|
||||
TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \
|
||||
TT_DESCRIPTOR_PAGE_AP_RW_RW | \
|
||||
TT_DESCRIPTOR_PAGE_AF | \
|
||||
TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE)
|
||||
|
||||
// First Level Descriptors
|
||||
typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;
|
||||
|
||||
// Second Level Descriptors
|
||||
typedef UINT32 ARM_PAGE_TABLE_ENTRY;
|
||||
|
||||
UINT32
|
||||
ConvertSectionAttributesToPageAttributes (
|
||||
IN UINT32 SectionAttributes
|
||||
);
|
||||
|
||||
#endif // ARMV7_MMU_H_
|
||||
@ -1,38 +0,0 @@
|
||||
/** @file
|
||||
Macros to work around lack of Apple support for LDR register, =expr
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
|
||||
Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
|
||||
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
|
||||
**/
|
||||
|
||||
#ifndef ASM_MACRO_IO_LIB_H_
|
||||
#define ASM_MACRO_IO_LIB_H_
|
||||
|
||||
#define _ASM_FUNC(Name, Section) \
|
||||
.global Name ; \
|
||||
.section #Section, "ax" ; \
|
||||
.type Name, %function ; \
|
||||
.p2align 2 ; \
|
||||
Name:
|
||||
|
||||
#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
|
||||
|
||||
#define MOV32(Reg, Val) \
|
||||
movw Reg, #(Val) & 0xffff ; \
|
||||
movt Reg, #(Val) >> 16
|
||||
|
||||
#define ADRL(Reg, Sym) \
|
||||
movw Reg, #:lower16:(Sym) - (. + 16) ; \
|
||||
movt Reg, #:upper16:(Sym) - (. + 12) ; \
|
||||
add Reg, Reg, pc
|
||||
|
||||
#define LDRL(Reg, Sym) \
|
||||
movw Reg, #:lower16:(Sym) - (. + 16) ; \
|
||||
movt Reg, #:upper16:(Sym) - (. + 12) ; \
|
||||
ldr Reg, [pc, Reg]
|
||||
|
||||
#endif // ASM_MACRO_IO_LIB_H_
|
||||
@ -1,238 +0,0 @@
|
||||
/** @file
|
||||
Processor or Compiler specific defines and types for ARM.
|
||||
|
||||
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
|
||||
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __PROCESSOR_BIND_H__
|
||||
#define __PROCESSOR_BIND_H__
|
||||
|
||||
///
|
||||
/// Define the processor type so other code can make processor based choices
|
||||
///
|
||||
#define MDE_CPU_ARM
|
||||
|
||||
//
|
||||
// Make sure we are using the correct packing rules per EFI specification
|
||||
//
|
||||
#if !defined (__GNUC__) && !defined (__ASSEMBLER__)
|
||||
#pragma pack()
|
||||
#endif
|
||||
|
||||
#if defined (_MSC_EXTENSIONS)
|
||||
|
||||
//
|
||||
// Disable some level 4 compilation warnings (same as IA32 and X64)
|
||||
//
|
||||
|
||||
//
|
||||
// Disabling bitfield type checking warnings.
|
||||
//
|
||||
#pragma warning ( disable : 4214 )
|
||||
|
||||
//
|
||||
// Disabling the unreferenced formal parameter warnings.
|
||||
//
|
||||
#pragma warning ( disable : 4100 )
|
||||
|
||||
//
|
||||
// Disable slightly different base types warning as CHAR8 * can not be set
|
||||
// to a constant string.
|
||||
//
|
||||
#pragma warning ( disable : 4057 )
|
||||
|
||||
//
|
||||
// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning
|
||||
//
|
||||
#pragma warning ( disable : 4127 )
|
||||
|
||||
//
|
||||
// This warning is caused by functions defined but not used. For precompiled header only.
|
||||
//
|
||||
#pragma warning ( disable : 4505 )
|
||||
|
||||
//
|
||||
// This warning is caused by empty (after preprocessing) source file. For precompiled header only.
|
||||
//
|
||||
#pragma warning ( disable : 4206 )
|
||||
|
||||
//
|
||||
// Disable 'potentially uninitialized local variable X used' warnings
|
||||
//
|
||||
#pragma warning ( disable : 4701 )
|
||||
|
||||
//
|
||||
// Disable 'potentially uninitialized local pointer variable X used' warnings
|
||||
//
|
||||
#pragma warning ( disable : 4703 )
|
||||
|
||||
#endif
|
||||
|
||||
//
|
||||
// MSFT doesn't support the __builtin_unreachable() macro
|
||||
//
|
||||
#if defined (_MSC_EXTENSIONS)
|
||||
#define UNREACHABLE()
|
||||
#endif
|
||||
|
||||
#if defined (_MSC_EXTENSIONS)
|
||||
//
|
||||
// use Microsoft* C compiler dependent integer width types
|
||||
//
|
||||
typedef unsigned __int64 UINT64;
|
||||
typedef __int64 INT64;
|
||||
typedef unsigned __int32 UINT32;
|
||||
typedef __int32 INT32;
|
||||
typedef unsigned short UINT16;
|
||||
typedef unsigned short CHAR16;
|
||||
typedef short INT16;
|
||||
typedef unsigned char BOOLEAN;
|
||||
typedef unsigned char UINT8;
|
||||
typedef char CHAR8;
|
||||
typedef signed char INT8;
|
||||
#else
|
||||
//
|
||||
// Assume standard ARM alignment.
|
||||
// Need to check portability of long long
|
||||
//
|
||||
typedef unsigned long long UINT64;
|
||||
typedef long long INT64;
|
||||
typedef unsigned int UINT32;
|
||||
typedef int INT32;
|
||||
typedef unsigned short UINT16;
|
||||
typedef unsigned short CHAR16;
|
||||
typedef short INT16;
|
||||
typedef unsigned char BOOLEAN;
|
||||
typedef unsigned char UINT8;
|
||||
typedef char CHAR8;
|
||||
typedef signed char INT8;
|
||||
#endif
|
||||
|
||||
///
|
||||
/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,
|
||||
/// 8 bytes on supported 64-bit processor instructions)
|
||||
///
|
||||
typedef UINT32 UINTN;
|
||||
|
||||
///
|
||||
/// Signed value of native width. (4 bytes on supported 32-bit processor instructions,
|
||||
/// 8 bytes on supported 64-bit processor instructions)
|
||||
///
|
||||
typedef INT32 INTN;
|
||||
|
||||
//
|
||||
// Processor specific defines
|
||||
//
|
||||
|
||||
///
|
||||
/// A value of native width with the highest bit set.
|
||||
///
|
||||
#define MAX_BIT 0x80000000
|
||||
|
||||
///
|
||||
/// A value of native width with the two highest bits set.
|
||||
///
|
||||
#define MAX_2_BITS 0xC0000000
|
||||
|
||||
///
|
||||
/// Maximum legal ARM address
|
||||
///
|
||||
#define MAX_ADDRESS 0xFFFFFFFF
|
||||
|
||||
///
|
||||
/// Maximum usable address at boot time
|
||||
///
|
||||
#define MAX_ALLOC_ADDRESS MAX_ADDRESS
|
||||
|
||||
///
|
||||
/// Maximum legal ARM INTN and UINTN values.
|
||||
///
|
||||
#define MAX_INTN ((INTN)0x7FFFFFFF)
|
||||
#define MAX_UINTN ((UINTN)0xFFFFFFFF)
|
||||
|
||||
///
|
||||
/// Minimum legal ARM INTN value.
|
||||
///
|
||||
#define MIN_INTN (((INTN)-2147483647) - 1)
|
||||
|
||||
///
|
||||
/// The stack alignment required for ARM
|
||||
///
|
||||
#define CPU_STACK_ALIGNMENT sizeof(UINT64)
|
||||
|
||||
///
|
||||
/// Page allocation granularity for ARM
|
||||
///
|
||||
#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
|
||||
#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)
|
||||
|
||||
//
|
||||
// Modifier to ensure that all protocol member functions and EFI intrinsics
|
||||
// use the correct C calling convention. All protocol member functions and
|
||||
// EFI intrinsics are required to modify their member functions with EFIAPI.
|
||||
//
|
||||
#define EFIAPI
|
||||
|
||||
// When compiling with Clang, we still use GNU as for the assembler, so we still
|
||||
// need to define the GCC_ASM* macros.
|
||||
#if defined (__GNUC__) || defined (__clang__)
|
||||
///
|
||||
/// For GNU assembly code, .global or .globl can declare global symbols.
|
||||
/// Define this macro to unify the usage.
|
||||
///
|
||||
#define ASM_GLOBAL .globl
|
||||
|
||||
#if !defined (__APPLE__)
|
||||
///
|
||||
/// ARM EABI defines that the linker should not manipulate call relocations
|
||||
/// (do bl/blx conversion) unless the target symbol has function type.
|
||||
/// CodeSourcery 2010.09 started requiring the .type to function properly
|
||||
///
|
||||
#define INTERWORK_FUNC(func__) .type ASM_PFX(func__), %function
|
||||
|
||||
#define GCC_ASM_EXPORT(func__) \
|
||||
.global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\
|
||||
.type ASM_PFX(func__), %function
|
||||
|
||||
#define GCC_ASM_IMPORT(func__) \
|
||||
.extern _CONCATENATE (__USER_LABEL_PREFIX__, func__)
|
||||
|
||||
#else
|
||||
//
|
||||
// .type not supported by Apple Xcode tools
|
||||
//
|
||||
#define INTERWORK_FUNC(func__)
|
||||
|
||||
#define GCC_ASM_EXPORT(func__) \
|
||||
.globl _CONCATENATE (__USER_LABEL_PREFIX__, func__) \
|
||||
|
||||
#define GCC_ASM_IMPORT(name)
|
||||
|
||||
#endif
|
||||
#elif defined (_MSC_EXTENSIONS)
|
||||
//
|
||||
// PRESERVE8 is not supported by the MSFT assembler.
|
||||
//
|
||||
#define PRESERVE8
|
||||
#endif
|
||||
|
||||
/**
|
||||
Return the pointer to the first instruction of a function given a function pointer.
|
||||
On ARM CPU architectures, these two pointer values are the same,
|
||||
so the implementation of this macro is very simple.
|
||||
|
||||
@param FunctionPointer A pointer to a function.
|
||||
|
||||
@return The pointer to the first instruction of a function given a function pointer.
|
||||
|
||||
**/
|
||||
#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
|
||||
|
||||
#ifndef __USER_LABEL_PREFIX__
|
||||
#define __USER_LABEL_PREFIX__
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -262,18 +262,16 @@ typedef struct {
|
||||
///@{
|
||||
#define EFI_GENERIC_ERROR_PROC_TYPE_IA32_X64 0x00
|
||||
#define EFI_GENERIC_ERROR_PROC_TYPE_IA64 0x01
|
||||
#define EFI_GENERIC_ERROR_PROC_TYPE_ARM 0x02
|
||||
///@}
|
||||
|
||||
///
|
||||
/// The type of the instruction set executing when the error occurred in Proessor
|
||||
/// Generic Error section.
|
||||
///@{
|
||||
#define EFI_GENERIC_ERROR_PROC_ISA_IA32 0x00
|
||||
#define EFI_GENERIC_ERROR_PROC_ISA_IA64 0x01
|
||||
#define EFI_GENERIC_ERROR_PROC_ISA_X64 0x02
|
||||
#define EFI_GENERIC_ERROR_PROC_ISA_ARM_A32_T32 0x03
|
||||
#define EFI_GENERIC_ERROR_PROC_ISA_ARM_A64 0x04
|
||||
#define EFI_GENERIC_ERROR_PROC_ISA_IA32 0x00
|
||||
#define EFI_GENERIC_ERROR_PROC_ISA_IA64 0x01
|
||||
#define EFI_GENERIC_ERROR_PROC_ISA_X64 0x02
|
||||
#define EFI_GENERIC_ERROR_PROC_ISA_ARM_A64 0x04
|
||||
///@}
|
||||
|
||||
///
|
||||
|
||||
@ -12,14 +12,7 @@
|
||||
#define ARM_LIB_H_
|
||||
|
||||
#include <Uefi/UefiBaseType.h>
|
||||
|
||||
#ifdef MDE_CPU_ARM
|
||||
#include <Arm/AArch32.h>
|
||||
#elif defined (MDE_CPU_AARCH64)
|
||||
#include <AArch64/AArch64.h>
|
||||
#else
|
||||
#error "Unknown chipset."
|
||||
#endif
|
||||
#include <AArch64/AArch64.h>
|
||||
|
||||
#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \
|
||||
EFI_MEMORY_WT | EFI_MEMORY_WB | \
|
||||
@ -722,7 +715,6 @@ ArmHasCcidx (
|
||||
VOID
|
||||
);
|
||||
|
||||
#ifdef MDE_CPU_AARCH64
|
||||
///
|
||||
/// AArch64-only ID Register Helper functions
|
||||
///
|
||||
@ -763,25 +755,4 @@ ArmHasEte (
|
||||
VOID
|
||||
);
|
||||
|
||||
#endif // MDE_CPU_AARCH64
|
||||
|
||||
#ifdef MDE_CPU_ARM
|
||||
///
|
||||
/// AArch32-only ID Register Helper functions
|
||||
///
|
||||
|
||||
/**
|
||||
Check whether the CPU supports the Security extensions
|
||||
|
||||
@return Whether the Security extensions are implemented
|
||||
|
||||
**/
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
ArmHasSecurityExtensions (
|
||||
VOID
|
||||
);
|
||||
|
||||
#endif // MDE_CPU_ARM
|
||||
|
||||
#endif // ARM_LIB_H_
|
||||
|
||||
@ -77,26 +77,6 @@ typedef struct {
|
||||
|
||||
#endif // defined (MDE_CPU_EBC)
|
||||
|
||||
#if defined (MDE_CPU_ARM)
|
||||
|
||||
typedef struct {
|
||||
UINT32 R3; ///< A copy of R13.
|
||||
UINT32 R4;
|
||||
UINT32 R5;
|
||||
UINT32 R6;
|
||||
UINT32 R7;
|
||||
UINT32 R8;
|
||||
UINT32 R9;
|
||||
UINT32 R10;
|
||||
UINT32 R11;
|
||||
UINT32 R12;
|
||||
UINT32 R14;
|
||||
} BASE_LIBRARY_JUMP_BUFFER;
|
||||
|
||||
#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 4
|
||||
|
||||
#endif // defined (MDE_CPU_ARM)
|
||||
|
||||
#if defined (MDE_CPU_AARCH64)
|
||||
typedef struct {
|
||||
// GP regs
|
||||
|
||||
@ -15,7 +15,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
#define __PI_STATUS_CODE_H__
|
||||
|
||||
//
|
||||
// Required for IA32, X64, IPF, ARM and EBC defines for CPU exception types
|
||||
// Required for IA32, X64, IPF, and EBC defines for CPU exception types
|
||||
//
|
||||
#include <Protocol/DebugSupport.h>
|
||||
|
||||
|
||||
@ -849,7 +849,6 @@ typedef enum {
|
||||
IsaX64 = IMAGE_FILE_MACHINE_X64, ///< 0x8664
|
||||
IsaIpf = IMAGE_FILE_MACHINE_IA64, ///< 0x0200
|
||||
IsaEbc = IMAGE_FILE_MACHINE_EBC, ///< 0x0EBC
|
||||
IsaArm = IMAGE_FILE_MACHINE_ARMTHUMB_MIXED, ///< 0x01c2
|
||||
IsaAArch64 = IMAGE_FILE_MACHINE_ARM64 ///< 0xAA64
|
||||
} EFI_INSTRUCTION_SET_ARCHITECTURE;
|
||||
|
||||
|
||||
@ -153,8 +153,6 @@ typedef UINT16 EFI_PXE_BASE_CODE_UDP_PORT;
|
||||
#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x0006
|
||||
#elif defined (MDE_CPU_X64)
|
||||
#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x0007
|
||||
#elif defined (MDE_CPU_ARM)
|
||||
#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000A
|
||||
#elif defined (MDE_CPU_AARCH64)
|
||||
#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000B
|
||||
#elif defined (MDE_CPU_RISCV64)
|
||||
|
||||
@ -232,11 +232,6 @@ typedef union {
|
||||
///
|
||||
#define EFI_IMAGE_MACHINE_X64 0x8664
|
||||
|
||||
///
|
||||
/// PE32+ Machine type for ARM mixed ARM and Thumb/Thumb2 images.
|
||||
///
|
||||
#define EFI_IMAGE_MACHINE_ARMTHUMB_MIXED 0x01C2
|
||||
|
||||
///
|
||||
/// PE32+ Machine type for AARCH64 A64 images.
|
||||
///
|
||||
@ -270,12 +265,6 @@ typedef union {
|
||||
|
||||
#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_IA32)
|
||||
|
||||
#elif defined (MDE_CPU_ARM)
|
||||
|
||||
#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_ARMTHUMB_MIXED)
|
||||
|
||||
#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
|
||||
|
||||
#elif defined (MDE_CPU_AARCH64)
|
||||
|
||||
#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
|
||||
|
||||
@ -2267,7 +2267,7 @@ typedef struct {
|
||||
#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA32 L"\\EFI\\BOOT\\BOOTIA32.EFI"
|
||||
#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA64 L"\\EFI\\BOOT\\BOOTIA64.EFI"
|
||||
#define EFI_REMOVABLE_MEDIA_FILE_NAME_X64 L"\\EFI\\BOOT\\BOOTX64.EFI"
|
||||
#define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM L"\\EFI\\BOOT\\BOOTARM.EFI"
|
||||
#define EFI_REMOVABLE_MEDIA_FILE_NAME_EBC L"\\EFI\\BOOT\\BOOTARM.EFI"
|
||||
#define EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64 L"\\EFI\\BOOT\\BOOTAA64.EFI"
|
||||
#define EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64 L"\\EFI\\BOOT\\BOOTRISCV64.EFI"
|
||||
#define EFI_REMOVABLE_MEDIA_FILE_NAME_LOONGARCH64 L"\\EFI\\BOOT\\BOOTLOONGARCH64.EFI"
|
||||
@ -2278,8 +2278,7 @@ typedef struct {
|
||||
#elif defined (MDE_CPU_X64)
|
||||
#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_X64
|
||||
#elif defined (MDE_CPU_EBC)
|
||||
#elif defined (MDE_CPU_ARM)
|
||||
#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_ARM
|
||||
#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_EBC
|
||||
#elif defined (MDE_CPU_AARCH64)
|
||||
#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64
|
||||
#elif defined (MDE_CPU_RISCV64)
|
||||
|
||||
@ -16,10 +16,6 @@
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = ArmTrngLib
|
||||
|
||||
#
|
||||
# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64
|
||||
#
|
||||
|
||||
[Sources]
|
||||
BaseArmTrngLibNull.c
|
||||
|
||||
|
||||
@ -25,7 +25,7 @@
|
||||
|
||||
|
||||
#
|
||||
# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64 LOONGARCH64
|
||||
# VALID_ARCHITECTURES = IA32 X64 EBC AARCH64 RISCV64 LOONGARCH64
|
||||
#
|
||||
|
||||
[Sources.IA32]
|
||||
@ -37,9 +37,6 @@
|
||||
[Sources.EBC]
|
||||
EbcCache.c
|
||||
|
||||
[Sources.ARM]
|
||||
ArmCache.c
|
||||
|
||||
[Sources.AARCH64]
|
||||
ArmCache.c
|
||||
|
||||
|
||||
@ -15,10 +15,6 @@
|
||||
VERSION_STRING = 1.1
|
||||
LIBRARY_CLASS = CacheMaintenanceLib
|
||||
|
||||
#
|
||||
# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
|
||||
#
|
||||
|
||||
[Sources]
|
||||
BaseCacheMaintenanceLibNull.c
|
||||
|
||||
|
||||
@ -15,10 +15,6 @@
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = CpuLib
|
||||
|
||||
#
|
||||
# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
|
||||
#
|
||||
|
||||
[Sources]
|
||||
BaseCpuLibNull.c
|
||||
|
||||
|
||||
@ -21,7 +21,7 @@
|
||||
|
||||
|
||||
#
|
||||
# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
|
||||
# VALID_ARCHITECTURES = IA32 X64 EBC AARCH64
|
||||
#
|
||||
|
||||
[Sources]
|
||||
|
||||
@ -20,11 +20,6 @@
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = PciLib
|
||||
|
||||
|
||||
#
|
||||
# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
|
||||
#
|
||||
|
||||
[Sources]
|
||||
PciLib.c
|
||||
|
||||
|
||||
@ -16,10 +16,6 @@
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = RngLib
|
||||
|
||||
#
|
||||
# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 EBC
|
||||
#
|
||||
|
||||
[Sources]
|
||||
BaseRngLibNull.c
|
||||
|
||||
|
||||
@ -26,13 +26,13 @@
|
||||
#
|
||||
# The following information is for reference only and not required by the build tools.
|
||||
#
|
||||
# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64 LOONGARCH64
|
||||
# VALID_ARCHITECTURES = IA32 X64 AARCH64 RISCV64 LOONGARCH64
|
||||
#
|
||||
|
||||
[Sources]
|
||||
SafeIntLib.c
|
||||
|
||||
[Sources.Ia32, Sources.ARM]
|
||||
[Sources.Ia32]
|
||||
SafeIntLib32.c
|
||||
|
||||
[Sources.X64, Sources.AARCH64, Sources.RISCV64, Sources.LOONGARCH64]
|
||||
|
||||
@ -23,10 +23,6 @@
|
||||
CONSTRUCTOR = DxeRuntimeDebugLibSerialPortConstructor
|
||||
DESTRUCTOR = DxeRuntimeDebugLibSerialPortDestructor
|
||||
|
||||
#
|
||||
# VALID_ARCHITECTURES = AARCH64 ARM IA32 X64 EBC
|
||||
#
|
||||
|
||||
[Sources]
|
||||
DebugLib.c
|
||||
|
||||
|
||||
@ -41,9 +41,6 @@
|
||||
[Includes.EBC]
|
||||
Include/Ebc
|
||||
|
||||
[Includes.ARM]
|
||||
Include/Arm
|
||||
|
||||
[Includes.AARCH64]
|
||||
Include/AArch64
|
||||
|
||||
@ -345,7 +342,7 @@
|
||||
TdxLib|Include/Library/TdxLib.h
|
||||
|
||||
[LibraryClasses.X64]
|
||||
## @libraryclass Defines a set of interfaces for the MM core entrypoint. The ARM/AARCH64 version lives in ArmPkg
|
||||
## @libraryclass Defines a set of interfaces for the MM core entrypoint. The AARCH64 version lives in ArmPkg
|
||||
#
|
||||
StandaloneMmCoreEntryPoint|Include/Library/StandaloneMmCoreEntryPoint.h
|
||||
|
||||
@ -353,7 +350,7 @@
|
||||
## @libraryclass Provides function to make ecalls to SBI
|
||||
BaseRiscVSbiLib|Include/Library/BaseRiscVSbiLib.h
|
||||
|
||||
[LibraryClasses.ARM, LibraryClasses.AARCH64]
|
||||
[LibraryClasses.AARCH64]
|
||||
## @libraryclass Provides an interface to Arm registers.
|
||||
#
|
||||
ArmLib|Include/Library/ArmLib.h
|
||||
|
||||
@ -16,7 +16,7 @@
|
||||
PLATFORM_VERSION = 1.08
|
||||
DSC_SPECIFICATION = 0x00010005
|
||||
OUTPUT_DIRECTORY = Build/Mde
|
||||
SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64|RISCV64|LOONGARCH64
|
||||
SUPPORTED_ARCHITECTURES = IA32|X64|EBC|AARCH64|RISCV64|LOONGARCH64
|
||||
BUILD_TARGETS = DEBUG|RELEASE|NOOPT
|
||||
SKUID_IDENTIFIER = DEFAULT
|
||||
|
||||
@ -144,7 +144,7 @@
|
||||
MdePkg/Library/DynamicStackCookieEntryPointLib/UefiApplicationEntryPoint.inf
|
||||
MdePkg/Library/DynamicStackCookieEntryPointLib/UefiDriverEntryPoint.inf
|
||||
|
||||
[Components.IA32, Components.X64, Components.ARM, Components.AARCH64]
|
||||
[Components.IA32, Components.X64, Components.AARCH64]
|
||||
#
|
||||
# Add UEFI Target Based Unit Tests
|
||||
#
|
||||
@ -200,7 +200,7 @@
|
||||
MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
|
||||
MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
|
||||
|
||||
[Components.ARM, Components.AARCH64]
|
||||
[Components.AARCH64]
|
||||
MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.inf
|
||||
MdePkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
|
||||
MdePkg/Library/ArmSmcLib/ArmSmcLib.inf
|
||||
|
||||
Reference in New Issue
Block a user