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UefiCpuPkg/ArmMmuLib: Add support for LPA2
Add support for LPA2 (52-bit physical addressing). Signed-off-by: Sarah Walker <Sarah.Walker2@arm.com>
This commit is contained in:
Sarah Walker
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mergify[bot]
mergify[bot]
parent
5ec21149a7
commit
90771630bf
@ -1,7 +1,7 @@
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/** @file
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* File managing the MMU for ARMv8 architecture
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*
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* Copyright (c) 2011-2020, ARM Limited. All rights reserved.
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* Copyright (c) 2011-2025, ARM Limited. All rights reserved.
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* Copyright (c) 2016, Linaro Limited. All rights reserved.
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* Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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*
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@ -91,9 +91,41 @@ ArmMemoryAttributeToPageAttribute (
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}
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}
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// T0SZ can be below MIN_T0SZ when LPA2 is in use, meaning the page table starts at level -1
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#define MIN_T0SZ 16
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#define BITS_PER_LEVEL 9
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#define MAX_VA_BITS 48
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#define MAX_VA_BITS 52
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STATIC
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VOID
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SetOutputAddress (
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IN UINTN *Entry,
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IN UINTN Address,
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IN BOOLEAN Lpa2Enabled
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)
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{
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if (Lpa2Enabled) {
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*Entry &= ~(TT_ADDRESS_MASK_BLOCK_ENTRY_LPA2 | TT_UPPER_ADDRESS_MASK);
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*Entry |= ((UINTN)Address & TT_ADDRESS_MASK_BLOCK_ENTRY_LPA2) | (((UINTN)Address >> 50) << 8);
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} else {
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*Entry &= ~TT_ADDRESS_MASK_BLOCK_ENTRY;
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*Entry |= (Address & TT_ADDRESS_MASK_BLOCK_ENTRY);
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}
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}
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STATIC
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UINT64
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GetOutputAddress (
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IN UINT64 Entry,
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IN BOOLEAN Lpa2Enabled
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)
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{
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if (Lpa2Enabled) {
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return (Entry & TT_ADDRESS_MASK_BLOCK_ENTRY_LPA2) | ((Entry & TT_UPPER_ADDRESS_MASK) << (50 - 8));
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} else {
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return Entry & TT_ADDRESS_MASK_BLOCK_ENTRY;
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}
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}
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STATIC
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UINTN
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@ -105,12 +137,12 @@ GetRootTableEntryCount (
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}
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STATIC
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UINTN
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INTN
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GetRootTableLevel (
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IN UINTN T0SZ
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)
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{
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return (T0SZ - MIN_T0SZ) / BITS_PER_LEVEL;
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return (INTN)(T0SZ - MIN_T0SZ) / BITS_PER_LEVEL;
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}
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STATIC
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@ -159,8 +191,9 @@ ReplaceTableEntry (
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STATIC
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VOID
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FreePageTablesRecursive (
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IN UINT64 *TranslationTable,
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IN UINTN Level
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IN UINT64 *TranslationTable,
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IN UINTN Level,
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IN BOOLEAN Lpa2Enabled
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)
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{
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UINTN Index;
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@ -171,9 +204,12 @@ FreePageTablesRecursive (
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for (Index = 0; Index < TT_ENTRY_COUNT; Index++) {
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if ((TranslationTable[Index] & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) {
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FreePageTablesRecursive (
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(VOID *)(UINTN)(TranslationTable[Index] &
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TT_ADDRESS_MASK_BLOCK_ENTRY),
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Level + 1
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(VOID *)GetOutputAddress (
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TranslationTable[Index],
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Lpa2Enabled
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),
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Level + 1,
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Lpa2Enabled
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);
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}
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}
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@ -222,8 +258,10 @@ UpdateRegionMappingRecursive (
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IN UINT64 AttributeSetMask,
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IN UINT64 AttributeClearMask,
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IN UINT64 *PageTable,
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IN UINTN Level,
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IN BOOLEAN TableIsLive
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IN INTN Level,
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IN BOOLEAN IsRootTable,
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IN BOOLEAN TableIsLive,
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IN BOOLEAN Lpa2Enabled
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)
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{
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UINTN BlockShift;
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@ -316,7 +354,9 @@ UpdateRegionMappingRecursive (
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0,
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TranslationTable,
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Level + 1,
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FALSE
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FALSE,
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FALSE,
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Lpa2Enabled
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);
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if (EFI_ERROR (Status)) {
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//
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@ -331,7 +371,7 @@ UpdateRegionMappingRecursive (
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NextTableIsLive = FALSE;
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} else {
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TranslationTable = (VOID *)(UINTN)(*Entry & TT_ADDRESS_MASK_BLOCK_ENTRY);
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TranslationTable = (VOID *)GetOutputAddress (*Entry, Lpa2Enabled);
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NextTableIsLive = TableIsLive;
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}
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@ -345,7 +385,9 @@ UpdateRegionMappingRecursive (
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AttributeClearMask,
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TranslationTable,
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Level + 1,
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NextTableIsLive
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FALSE,
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NextTableIsLive,
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Lpa2Enabled
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);
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if (EFI_ERROR (Status)) {
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if (!IsTableEntry (*Entry, Level)) {
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@ -356,14 +398,16 @@ UpdateRegionMappingRecursive (
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// possible for existing table entries, since we cannot revert the
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// modifications we made to the subhierarchy it represents.)
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//
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FreePageTablesRecursive (TranslationTable, Level + 1);
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FreePageTablesRecursive (TranslationTable, Level + 1, Lpa2Enabled);
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}
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return Status;
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}
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if (!IsTableEntry (*Entry, Level)) {
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EntryValue = (UINTN)TranslationTable | TT_TYPE_TABLE_ENTRY;
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EntryValue = TT_TYPE_TABLE_ENTRY;
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SetOutputAddress (&EntryValue, (UINTN)TranslationTable, Lpa2Enabled);
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ReplaceTableEntry (
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Entry,
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EntryValue,
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@ -373,8 +417,9 @@ UpdateRegionMappingRecursive (
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);
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}
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} else {
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EntryValue = (*Entry & AttributeClearMask) | AttributeSetMask;
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EntryValue |= RegionStart;
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EntryValue = (*Entry & AttributeClearMask) | AttributeSetMask;
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// Below clears shareability bits when LPA2 is in use
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SetOutputAddress (&EntryValue, RegionStart, Lpa2Enabled);
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EntryValue |= (Level == 3) ? TT_TYPE_BLOCK_ENTRY_LEVEL3
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: TT_TYPE_BLOCK_ENTRY;
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@ -393,7 +438,8 @@ UpdateRegionMapping (
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IN UINT64 AttributeSetMask,
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IN UINT64 AttributeClearMask,
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IN UINT64 *RootTable,
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IN BOOLEAN TableIsLive
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IN BOOLEAN TableIsLive,
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IN BOOLEAN Lpa2Enabled
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)
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{
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UINTN T0SZ;
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@ -418,7 +464,9 @@ UpdateRegionMapping (
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AttributeClearMask,
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RootTable,
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GetRootTableLevel (T0SZ),
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TableIsLive
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TRUE,
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TableIsLive,
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Lpa2Enabled
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);
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}
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@ -426,7 +474,8 @@ STATIC
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EFI_STATUS
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FillTranslationTable (
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IN UINT64 *RootTable,
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IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
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IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion,
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IN BOOLEAN Lpa2Enabled
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)
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{
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return UpdateRegionMapping (
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@ -435,7 +484,8 @@ FillTranslationTable (
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ArmMemoryAttributeToPageAttribute (MemoryRegion->Attributes) | TT_AF,
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0,
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RootTable,
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FALSE
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FALSE,
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Lpa2Enabled
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);
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}
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@ -565,7 +615,8 @@ ArmSetMemoryAttributes (
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PageAttributes,
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PageAttributeMask,
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ArmGetTTBR0BaseAddress (),
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TRUE
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TRUE,
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ArmGetTCR () & TCR_DS
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);
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}
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@ -628,13 +679,15 @@ ArmConfigureMmu (
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TCR |= TCR_PS_16TB;
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} else if (MaxAddress < SIZE_256TB) {
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TCR |= TCR_PS_256TB;
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} else if ((MaxAddress < SIZE_4PB) && ArmHas52BitTgran4 ()) {
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TCR |= TCR_PS_4PB | TCR_DS;
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} else {
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DEBUG ((
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DEBUG_ERROR,
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"ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n",
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MaxAddress
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));
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ASSERT (0); // Bigger than 48-bit memory space are not supported
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ASSERT (0); // Bigger than 48/52-bit memory space are not supported
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return EFI_UNSUPPORTED;
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}
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} else {
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@ -654,13 +707,15 @@ ArmConfigureMmu (
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TCR |= TCR_IPS_16TB;
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} else if (MaxAddress < SIZE_256TB) {
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TCR |= TCR_IPS_256TB;
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} else if ((MaxAddress < SIZE_4PB) && ArmHas52BitTgran4 ()) {
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TCR |= TCR_IPS_4PB | TCR_DS;
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} else {
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DEBUG ((
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DEBUG_ERROR,
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"ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n",
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MaxAddress
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));
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ASSERT (0); // Bigger than 48-bit memory space are not supported
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ASSERT (0); // Bigger than 48/52-bit memory space are not supported
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return EFI_UNSUPPORTED;
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}
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}
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@ -709,7 +764,7 @@ ArmConfigureMmu (
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ZeroMem (TranslationTable, RootTableEntryCount * sizeof (UINT64));
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while (MemoryTable->Length != 0) {
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Status = FillTranslationTable (TranslationTable, MemoryTable);
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Status = FillTranslationTable (TranslationTable, MemoryTable, TCR & TCR_DS);
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if (EFI_ERROR (Status)) {
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goto FreeTranslationTable;
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}
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@ -730,7 +785,15 @@ ArmConfigureMmu (
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MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK)
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);
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ArmSetTTBR0 (TranslationTable);
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if ((TCR & TCR_IPS_MASK) == TCR_IPS_4PB) {
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ArmSetTTBR0 (
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(VOID *)
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(((UINTN)TranslationTable & 0xffffffffffc0) |
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(((UINTN)TranslationTable >> 48) << 2))
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);
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} else {
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ArmSetTTBR0 (TranslationTable);
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}
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if (!ArmMmuEnabled ()) {
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ArmDisableAlignmentCheck ();
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