mirror of
https://gitlab.com/qemu-project/edk2.git
synced 2025-10-30 07:56:39 +08:00
ArmPkg: Remove ARM32 Support from ArmLib
edk2 is dropping support for the ARM32 architecture. This commit removes ARM32 files from ArmLib. Signed-off-by: Oliver Smith-Denny <osde@microsoft.com>
This commit is contained in:
Oliver Smith-Denny
committed by
mergify[bot]
mergify[bot]
parent
4261eb1bef
commit
cdc8858e19
@ -1,153 +0,0 @@
|
||||
#------------------------------------------------------------------------------
|
||||
#
|
||||
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
# Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.
|
||||
# Copyright (c) 2016, Linaro Limited. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
#include <AsmMacroLib.h>
|
||||
|
||||
ASM_FUNC(ArmReadMidr)
|
||||
mrc p15,0,R0,c0,c0,0
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmCacheInfo)
|
||||
mrc p15,0,R0,c0,c0,1
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmGetInterruptState)
|
||||
mrs R0,CPSR
|
||||
tst R0,#0x80 @Check if IRQ is enabled.
|
||||
moveq R0,#1
|
||||
movne R0,#0
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmGetFiqState)
|
||||
mrs R0,CPSR
|
||||
tst R0,#0x40 @Check if FIQ is enabled.
|
||||
moveq R0,#1
|
||||
movne R0,#0
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmSetDomainAccessControl)
|
||||
mcr p15,0,r0,c3,c0,0
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(CPSRMaskInsert) @ on entry, r0 is the mask and r1 is the field to insert
|
||||
stmfd sp!, {r4-r12, lr} @ save all the banked registers
|
||||
mov r3, sp @ copy the stack pointer into a non-banked register
|
||||
mrs r2, cpsr @ read the cpsr
|
||||
bic r2, r2, r0 @ clear mask in the cpsr
|
||||
and r1, r1, r0 @ clear bits outside the mask in the input
|
||||
orr r2, r2, r1 @ set field
|
||||
msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)
|
||||
isb
|
||||
mov sp, r3 @ restore stack pointer
|
||||
ldmfd sp!, {r4-r12, lr} @ restore registers
|
||||
bx lr @ return (hopefully thumb-safe!)
|
||||
|
||||
ASM_FUNC(CPSRRead)
|
||||
mrs r0, cpsr
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmReadCpacr)
|
||||
mrc p15, 0, r0, c1, c0, 2
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmWriteCpacr)
|
||||
mcr p15, 0, r0, c1, c0, 2
|
||||
isb
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmWriteAuxCr)
|
||||
mcr p15, 0, r0, c1, c0, 1
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmReadAuxCr)
|
||||
mrc p15, 0, r0, c1, c0, 1
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmSetTTBR0)
|
||||
mcr p15,0,r0,c2,c0,0
|
||||
isb
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmSetTTBCR)
|
||||
mcr p15, 0, r0, c2, c0, 2
|
||||
isb
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmGetTTBR0BaseAddress)
|
||||
mrc p15,0,r0,c2,c0,0
|
||||
MOV32 (r1, 0xFFFFC000)
|
||||
and r0, r0, r1
|
||||
isb
|
||||
bx lr
|
||||
|
||||
//
|
||||
//VOID
|
||||
//ArmUpdateTranslationTableEntry (
|
||||
// IN VOID *TranslationTableEntry // R0
|
||||
// IN VOID *MVA // R1
|
||||
// );
|
||||
ASM_FUNC(ArmUpdateTranslationTableEntry)
|
||||
mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA
|
||||
mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
|
||||
dsb
|
||||
isb
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmInvalidateTlb)
|
||||
mov r0,#0
|
||||
mcr p15,0,r0,c8,c7,0
|
||||
mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
|
||||
dsb
|
||||
isb
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmReadHVBar)
|
||||
mrc p15, 4, r0, c12, c0, 0
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmWriteHVBar)
|
||||
mcr p15, 4, r0, c12, c0, 0
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmCallWFE)
|
||||
wfe
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmCallSEV)
|
||||
sev
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmReadSctlr)
|
||||
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmWriteSctlr)
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmReadCpuActlr)
|
||||
mrc p15, 0, r0, c1, c0, 1
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmWriteCpuActlr)
|
||||
mcr p15, 0, r0, c1, c0, 1
|
||||
dsb
|
||||
isb
|
||||
bx lr
|
||||
|
||||
ASM_FUNC (ArmGetPhysicalAddressBits)
|
||||
mrc p15, 0, r0, c0, c1, 4 // MMFR0
|
||||
and r0, r0, #0xf // VMSA [3:0]
|
||||
cmp r0, #5 // >= 5 implies LPAE support
|
||||
movlt r0, #32 // 32 bits if no LPAE
|
||||
movge r0, #40 // 40 bits if LPAE
|
||||
bx lr
|
||||
|
||||
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
||||
@ -1,103 +0,0 @@
|
||||
#------------------------------------------------------------------------------
|
||||
#
|
||||
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
|
||||
# Copyright (c) 2016, Linaro Limited. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
#include <AsmMacroLib.h>
|
||||
|
||||
ASM_FUNC(ArmIsMpCore)
|
||||
mrc p15,0,R0,c0,c0,5
|
||||
// Get Multiprocessing extension (bit31) & U bit (bit30)
|
||||
and R0, R0, #0xC0000000
|
||||
// if (bit31 == 1) && (bit30 == 0) then the processor is part of a multiprocessor system
|
||||
cmp R0, #0x80000000
|
||||
moveq R0, #1
|
||||
movne R0, #0
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmEnableAsynchronousAbort)
|
||||
cpsie a
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmDisableAsynchronousAbort)
|
||||
cpsid a
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmEnableIrq)
|
||||
cpsie i
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmDisableIrq)
|
||||
cpsid i
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmEnableFiq)
|
||||
cpsie f
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmDisableFiq)
|
||||
cpsid f
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmEnableInterrupts)
|
||||
cpsie if
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmDisableInterrupts)
|
||||
cpsid if
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmReadIdMmfr4)
|
||||
mrc p15,0,r0,c0,c2,6 @ Read ID_MMFR4 Register
|
||||
bx lr
|
||||
|
||||
// UINTN
|
||||
// ReadCCSIDR (
|
||||
// IN UINT32 CSSELR
|
||||
// )
|
||||
ASM_FUNC(ReadCCSIDR)
|
||||
mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)
|
||||
isb
|
||||
mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)
|
||||
bx lr
|
||||
|
||||
// UINT32
|
||||
// ReadCCSIDR2 (
|
||||
// IN UINT32 CSSELR
|
||||
// )
|
||||
ASM_FUNC(ReadCCSIDR2)
|
||||
mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)
|
||||
isb
|
||||
mrc p15,1,r0,c0,c0,2 @ Read current CP15 Cache Size ID Register (CCSIDR2)
|
||||
bx lr
|
||||
|
||||
// UINT32
|
||||
// ReadCLIDR (
|
||||
// IN UINT32 CSSELR
|
||||
// )
|
||||
ASM_FUNC(ReadCLIDR)
|
||||
mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmReadNsacr)
|
||||
mrc p15, 0, r0, c1, c1, 2
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmWriteNsacr)
|
||||
mcr p15, 0, r0, c1, c1, 2
|
||||
bx lr
|
||||
|
||||
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
||||
@ -1,92 +0,0 @@
|
||||
#------------------------------------------------------------------------------
|
||||
#
|
||||
# Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
# Copyright (c) 2016, Linaro Limited. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
#include <AsmMacroLib.h>
|
||||
|
||||
ASM_FUNC(ArmReadCntFrq)
|
||||
mrc p15, 0, r0, c14, c0, 0 @ Read CNTFRQ
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmWriteCntFrq)
|
||||
mcr p15, 0, r0, c14, c0, 0 @ Write to CNTFRQ
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmReadCntPct)
|
||||
mrrc p15, 0, r0, r1, c14 @ Read CNTPT (Physical counter register)
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmReadCntkCtl)
|
||||
mrc p15, 0, r0, c14, c1, 0 @ Read CNTK_CTL (Timer PL1 Control Register)
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmWriteCntkCtl)
|
||||
mcr p15, 0, r0, c14, c1, 0 @ Write to CNTK_CTL (Timer PL1 Control Register)
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmReadCntpTval)
|
||||
mrc p15, 0, r0, c14, c2, 0 @ Read CNTP_TVAL (PL1 physical timer value register)
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmWriteCntpTval)
|
||||
mcr p15, 0, r0, c14, c2, 0 @ Write to CNTP_TVAL (PL1 physical timer value register)
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmReadCntpCtl)
|
||||
mrc p15, 0, r0, c14, c2, 1 @ Read CNTP_CTL (PL1 Physical Timer Control Register)
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmWriteCntpCtl)
|
||||
mcr p15, 0, r0, c14, c2, 1 @ Write to CNTP_CTL (PL1 Physical Timer Control Register)
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmReadCntvTval)
|
||||
mrc p15, 0, r0, c14, c3, 0 @ Read CNTV_TVAL (Virtual Timer Value register)
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmWriteCntvTval)
|
||||
mcr p15, 0, r0, c14, c3, 0 @ Write to CNTV_TVAL (Virtual Timer Value register)
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmReadCntvCtl)
|
||||
mrc p15, 0, r0, c14, c3, 1 @ Read CNTV_CTL (Virtual Timer Control Register)
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmWriteCntvCtl)
|
||||
mcr p15, 0, r0, c14, c3, 1 @ Write to CNTV_CTL (Virtual Timer Control Register)
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmReadCntvCt)
|
||||
mrrc p15, 1, r0, r1, c14 @ Read CNTVCT (Virtual Count Register)
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmReadCntpCval)
|
||||
mrrc p15, 2, r0, r1, c14 @ Read CNTP_CTVAL (Physical Timer Compare Value Register)
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmWriteCntpCval)
|
||||
mcrr p15, 2, r0, r1, c14 @ Write to CNTP_CTVAL (Physical Timer Compare Value Register)
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmReadCntvCval)
|
||||
mrrc p15, 3, r0, r1, c14 @ Read CNTV_CTVAL (Virtual Timer Compare Value Register)
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmWriteCntvCval)
|
||||
mcrr p15, 3, r0, r1, c14 @ write to CNTV_CTVAL (Virtual Timer Compare Value Register)
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmReadCntvOff)
|
||||
mrrc p15, 4, r0, r1, c14 @ Read CNTVOFF (virtual Offset register)
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmWriteCntvOff)
|
||||
mcrr p15, 4, r0, r1, c14 @ Write to CNTVOFF (Virtual Offset register)
|
||||
bx lr
|
||||
|
||||
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
||||
@ -1,81 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
|
||||
Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
|
||||
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
|
||||
**/
|
||||
|
||||
#include <Base.h>
|
||||
|
||||
#include <Library/ArmLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
|
||||
#include <Arm/AArch32.h>
|
||||
|
||||
#include "ArmV7Lib.h"
|
||||
#include "ArmLibPrivate.h"
|
||||
|
||||
/**
|
||||
Check whether the CPU supports the GIC system register interface (any version)
|
||||
|
||||
@return Whether GIC System Register Interface is supported
|
||||
|
||||
**/
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
ArmHasGicSystemRegisters (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return ((ArmReadIdPfr1 () & ARM_PFR1_GIC) != 0);
|
||||
}
|
||||
|
||||
/**
|
||||
Check whether the CPU supports the GICv5 system register interface
|
||||
|
||||
@return Whether GICv5 System Register Interface is supported
|
||||
**/
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
ArmHasGicV5SystemRegisters (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
// GICv5 not supported in AArch32.
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/**
|
||||
Check whether the CPU supports the Security extensions
|
||||
|
||||
@return Whether the Security extensions are implemented
|
||||
|
||||
**/
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
ArmHasSecurityExtensions (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return ((ArmReadIdPfr1 () & ARM_PFR1_SEC) != 0);
|
||||
}
|
||||
|
||||
/** Checks if CCIDX is implemented.
|
||||
|
||||
@retval TRUE CCIDX is implemented.
|
||||
@retval FALSE CCIDX is not implemented.
|
||||
**/
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
ArmHasCcidx (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINTN Mmfr4;
|
||||
|
||||
Mmfr4 = ArmReadIdMmfr4 ();
|
||||
return (((Mmfr4 >> 24) & 0xF) == 1) ? TRUE : FALSE;
|
||||
}
|
||||
@ -1,42 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
|
||||
**/
|
||||
|
||||
#ifndef ARM_V7_LIB_H_
|
||||
#define ARM_V7_LIB_H_
|
||||
|
||||
#define ID_MMFR0_SHARELVL_SHIFT 12
|
||||
#define ID_MMFR0_SHARELVL_MASK 0xf
|
||||
#define ID_MMFR0_SHARELVL_ONE 0
|
||||
#define ID_MMFR0_SHARELVL_TWO 1
|
||||
|
||||
#define ID_MMFR0_INNERSHR_SHIFT 28
|
||||
#define ID_MMFR0_INNERSHR_MASK 0xf
|
||||
#define ID_MMFR0_OUTERSHR_SHIFT 8
|
||||
#define ID_MMFR0_OUTERSHR_MASK 0xf
|
||||
|
||||
#define ID_MMFR0_SHR_IMP_UNCACHED 0
|
||||
#define ID_MMFR0_SHR_IMP_HW_COHERENT 1
|
||||
#define ID_MMFR0_SHR_IGNORED 0xf
|
||||
|
||||
/** Reads the ID_MMFR4 register.
|
||||
|
||||
@return The contents of the ID_MMFR4 register.
|
||||
**/
|
||||
UINT32
|
||||
EFIAPI
|
||||
ArmReadIdMmfr4 (
|
||||
VOID
|
||||
);
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmReadIdPfr1 (
|
||||
VOID
|
||||
);
|
||||
|
||||
#endif // ARM_V7_LIB_H_
|
||||
@ -1,236 +0,0 @@
|
||||
#------------------------------------------------------------------------------
|
||||
#
|
||||
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
|
||||
# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
|
||||
# Copyright (c) 2016, Linaro Limited. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
#include <AsmMacroLib.h>
|
||||
|
||||
.set DC_ON, (0x1<<2)
|
||||
.set IC_ON, (0x1<<12)
|
||||
.set CTRL_M_BIT, (1 << 0)
|
||||
.set CTRL_C_BIT, (1 << 2)
|
||||
.set CTRL_B_BIT, (1 << 7)
|
||||
.set CTRL_I_BIT, (1 << 12)
|
||||
.set CTRL_AFE_BIT,(1 << 29)
|
||||
|
||||
|
||||
ASM_FUNC(ArmInvalidateDataCacheEntryByMVA)
|
||||
mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmCleanDataCacheEntryByMVA)
|
||||
mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
|
||||
bx lr
|
||||
|
||||
|
||||
ASM_FUNC(ArmCleanDataCacheEntryToPoUByMVA)
|
||||
mcr p15, 0, r0, c7, c11, 1 @clean single data cache line to PoU
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmInvalidateInstructionCacheEntryToPoUByMVA)
|
||||
mcr p15, 0, r0, c7, c5, 1 @Invalidate single instruction cache line to PoU
|
||||
mcr p15, 0, r0, c7, c5, 7 @Invalidate branch predictor
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmCleanInvalidateDataCacheEntryByMVA)
|
||||
mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
|
||||
bx lr
|
||||
|
||||
|
||||
ASM_FUNC(ArmInvalidateInstructionCache)
|
||||
mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache
|
||||
dsb
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmEnableMmu)
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
orr R0,R0,#1
|
||||
orr R0,R0,#CTRL_AFE_BIT
|
||||
mcr p15,0,R0,c1,c0,0
|
||||
dsb
|
||||
isb
|
||||
bx LR
|
||||
|
||||
|
||||
ASM_FUNC(ArmDisableMmu)
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
bic R0,R0,#1
|
||||
mcr p15,0,R0,c1,c0,0 @Disable MMU
|
||||
|
||||
mcr p15,0,R0,c8,c7,0 @Invalidate TLB
|
||||
mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array
|
||||
dsb
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmDisableCachesAndMmu)
|
||||
mrc p15, 0, r0, c1, c0, 0 @ Get control register
|
||||
bic r0, r0, #CTRL_M_BIT @ Disable MMU
|
||||
bic r0, r0, #CTRL_C_BIT @ Disable D Cache
|
||||
bic r0, r0, #CTRL_I_BIT @ Disable I Cache
|
||||
mcr p15, 0, r0, c1, c0, 0 @ Write control register
|
||||
dsb
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmMmuEnabled)
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
and R0,R0,#1
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmEnableDataCache)
|
||||
ldr R1,=DC_ON
|
||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||
orr R0,R0,R1 @Set C bit
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
dsb
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmDisableDataCache)
|
||||
ldr R1,=DC_ON
|
||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||
bic R0,R0,R1 @Clear C bit
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
dsb
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmEnableInstructionCache)
|
||||
ldr R1,=IC_ON
|
||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||
orr R0,R0,R1 @Set I bit
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
dsb
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmDisableInstructionCache)
|
||||
ldr R1,=IC_ON
|
||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||
bic R0,R0,R1 @Clear I bit.
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
dsb
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmEnableSWPInstruction)
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
orr r0, r0, #0x00000400
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmEnableBranchPrediction)
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
orr r0, r0, #0x00000800
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
dsb
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmDisableBranchPrediction)
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
bic r0, r0, #0x00000800
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
dsb
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmSetLowVectors)
|
||||
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
|
||||
bic r0, r0, #0x00002000 @ clear V bit
|
||||
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmSetHighVectors)
|
||||
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
|
||||
orr r0, r0, #0x00002000 @ Set V bit
|
||||
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmDataMemoryBarrier)
|
||||
dmb
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmDataSynchronizationBarrier)
|
||||
dsb
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmInstructionSynchronizationBarrier)
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ASM_FUNC(ArmReadVBar)
|
||||
# Set the Address of the Vector Table in the VBAR register
|
||||
mrc p15, 0, r0, c12, c0, 0
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmWriteVBar)
|
||||
# Set the Address of the Vector Table in the VBAR register
|
||||
mcr p15, 0, r0, c12, c0, 0
|
||||
# Ensure the SCTLR.V bit is clear
|
||||
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
|
||||
bic r0, r0, #0x00002000 @ clear V bit
|
||||
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
|
||||
isb
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmEnableVFP)
|
||||
# Read CPACR (Coprocessor Access Control Register)
|
||||
mrc p15, 0, r0, c1, c0, 2
|
||||
# Enable VPF access (Full Access to CP10, CP11) (V* instructions)
|
||||
orr r0, r0, #0x00f00000
|
||||
# Write back CPACR (Coprocessor Access Control Register)
|
||||
mcr p15, 0, r0, c1, c0, 2
|
||||
isb
|
||||
# Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
|
||||
mov r0, #0x40000000
|
||||
#ifndef __clang__
|
||||
mcr p10,#0x7,r0,c8,c0,#0
|
||||
#else
|
||||
# Set the FPU model so Clang does not choke on the next instruction
|
||||
.fpu neon
|
||||
vmsr fpexc, r0
|
||||
#endif
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmCallWFI)
|
||||
wfi
|
||||
bx lr
|
||||
|
||||
#Note: Return 0 in Uniprocessor implementation
|
||||
ASM_FUNC(ArmReadCbar)
|
||||
mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmReadMpidr)
|
||||
mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmReadTpidrurw)
|
||||
mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmWriteTpidrurw)
|
||||
mcr p15, 0, r0, c13, c0, 2 @ write TPIDRURW
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmIsArchTimerImplemented)
|
||||
mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1
|
||||
and r0, r0, #0x000F0000
|
||||
bx lr
|
||||
|
||||
ASM_FUNC(ArmReadIdPfr1)
|
||||
mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1 Register
|
||||
bx lr
|
||||
|
||||
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
||||
@ -21,15 +21,6 @@
|
||||
ArmLibPrivate.h
|
||||
ArmLib.c
|
||||
|
||||
[Sources.ARM]
|
||||
Arm/ArmV7Lib.h
|
||||
Arm/ArmV7Lib.c
|
||||
|
||||
Arm/ArmLibSupport.S | GCC
|
||||
Arm/ArmLibSupportV7.S | GCC
|
||||
Arm/ArmV7Support.S | GCC
|
||||
Arm/ArmV7ArchTimerSupport.S | GCC
|
||||
|
||||
[Sources.AARCH64]
|
||||
AArch64/AArch64Lib.h
|
||||
AArch64/AArch64Lib.c
|
||||
|
||||
Reference in New Issue
Block a user