mirror of
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ArmPkg: Remove ARM32 Support from ArmLib
edk2 is dropping support for the ARM32 architecture. This commit removes ARM32 files from ArmLib. Signed-off-by: Oliver Smith-Denny <osde@microsoft.com>
This commit is contained in:
Oliver Smith-Denny
committed by
mergify[bot]
mergify[bot]
parent
4261eb1bef
commit
cdc8858e19
@ -1,153 +0,0 @@
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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# Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.
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# Copyright (c) 2016, Linaro Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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#------------------------------------------------------------------------------
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#include <AsmMacroLib.h>
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ASM_FUNC(ArmReadMidr)
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mrc p15,0,R0,c0,c0,0
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bx LR
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ASM_FUNC(ArmCacheInfo)
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mrc p15,0,R0,c0,c0,1
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bx LR
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ASM_FUNC(ArmGetInterruptState)
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mrs R0,CPSR
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tst R0,#0x80 @Check if IRQ is enabled.
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moveq R0,#1
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movne R0,#0
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bx LR
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ASM_FUNC(ArmGetFiqState)
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mrs R0,CPSR
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tst R0,#0x40 @Check if FIQ is enabled.
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moveq R0,#1
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movne R0,#0
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bx LR
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ASM_FUNC(ArmSetDomainAccessControl)
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mcr p15,0,r0,c3,c0,0
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bx lr
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ASM_FUNC(CPSRMaskInsert) @ on entry, r0 is the mask and r1 is the field to insert
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stmfd sp!, {r4-r12, lr} @ save all the banked registers
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mov r3, sp @ copy the stack pointer into a non-banked register
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mrs r2, cpsr @ read the cpsr
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bic r2, r2, r0 @ clear mask in the cpsr
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and r1, r1, r0 @ clear bits outside the mask in the input
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orr r2, r2, r1 @ set field
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msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)
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isb
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mov sp, r3 @ restore stack pointer
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ldmfd sp!, {r4-r12, lr} @ restore registers
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bx lr @ return (hopefully thumb-safe!)
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ASM_FUNC(CPSRRead)
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mrs r0, cpsr
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bx lr
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ASM_FUNC(ArmReadCpacr)
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mrc p15, 0, r0, c1, c0, 2
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bx lr
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ASM_FUNC(ArmWriteCpacr)
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mcr p15, 0, r0, c1, c0, 2
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isb
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bx lr
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ASM_FUNC(ArmWriteAuxCr)
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mcr p15, 0, r0, c1, c0, 1
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bx lr
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ASM_FUNC(ArmReadAuxCr)
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mrc p15, 0, r0, c1, c0, 1
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bx lr
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ASM_FUNC(ArmSetTTBR0)
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mcr p15,0,r0,c2,c0,0
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isb
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bx lr
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ASM_FUNC(ArmSetTTBCR)
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mcr p15, 0, r0, c2, c0, 2
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isb
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bx lr
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ASM_FUNC(ArmGetTTBR0BaseAddress)
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mrc p15,0,r0,c2,c0,0
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MOV32 (r1, 0xFFFFC000)
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and r0, r0, r1
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isb
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bx lr
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//
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//VOID
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//ArmUpdateTranslationTableEntry (
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// IN VOID *TranslationTableEntry // R0
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// IN VOID *MVA // R1
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// );
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ASM_FUNC(ArmUpdateTranslationTableEntry)
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mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA
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mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
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dsb
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isb
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bx lr
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ASM_FUNC(ArmInvalidateTlb)
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mov r0,#0
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mcr p15,0,r0,c8,c7,0
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mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
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dsb
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isb
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bx lr
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ASM_FUNC(ArmReadHVBar)
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mrc p15, 4, r0, c12, c0, 0
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bx lr
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ASM_FUNC(ArmWriteHVBar)
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mcr p15, 4, r0, c12, c0, 0
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bx lr
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ASM_FUNC(ArmCallWFE)
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wfe
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bx lr
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ASM_FUNC(ArmCallSEV)
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sev
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bx lr
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ASM_FUNC(ArmReadSctlr)
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mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
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bx lr
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ASM_FUNC(ArmWriteSctlr)
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mcr p15, 0, r0, c1, c0, 0
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bx lr
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ASM_FUNC(ArmReadCpuActlr)
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mrc p15, 0, r0, c1, c0, 1
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bx lr
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ASM_FUNC(ArmWriteCpuActlr)
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mcr p15, 0, r0, c1, c0, 1
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dsb
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isb
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bx lr
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ASM_FUNC (ArmGetPhysicalAddressBits)
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mrc p15, 0, r0, c0, c1, 4 // MMFR0
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and r0, r0, #0xf // VMSA [3:0]
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cmp r0, #5 // >= 5 implies LPAE support
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movlt r0, #32 // 32 bits if no LPAE
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movge r0, #40 // 40 bits if LPAE
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bx lr
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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@ -1,103 +0,0 @@
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
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# Copyright (c) 2016, Linaro Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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#------------------------------------------------------------------------------
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#include <AsmMacroLib.h>
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ASM_FUNC(ArmIsMpCore)
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mrc p15,0,R0,c0,c0,5
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// Get Multiprocessing extension (bit31) & U bit (bit30)
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and R0, R0, #0xC0000000
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// if (bit31 == 1) && (bit30 == 0) then the processor is part of a multiprocessor system
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cmp R0, #0x80000000
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moveq R0, #1
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movne R0, #0
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bx LR
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ASM_FUNC(ArmEnableAsynchronousAbort)
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cpsie a
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isb
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bx LR
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ASM_FUNC(ArmDisableAsynchronousAbort)
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cpsid a
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isb
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bx LR
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ASM_FUNC(ArmEnableIrq)
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cpsie i
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isb
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bx LR
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ASM_FUNC(ArmDisableIrq)
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cpsid i
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isb
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bx LR
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ASM_FUNC(ArmEnableFiq)
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cpsie f
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isb
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bx LR
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ASM_FUNC(ArmDisableFiq)
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cpsid f
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isb
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bx LR
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ASM_FUNC(ArmEnableInterrupts)
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cpsie if
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isb
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bx LR
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ASM_FUNC(ArmDisableInterrupts)
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cpsid if
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isb
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bx LR
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ASM_FUNC(ArmReadIdMmfr4)
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mrc p15,0,r0,c0,c2,6 @ Read ID_MMFR4 Register
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bx lr
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// UINTN
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// ReadCCSIDR (
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// IN UINT32 CSSELR
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// )
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ASM_FUNC(ReadCCSIDR)
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mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)
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isb
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mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)
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bx lr
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// UINT32
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// ReadCCSIDR2 (
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// IN UINT32 CSSELR
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// )
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ASM_FUNC(ReadCCSIDR2)
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mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)
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isb
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mrc p15,1,r0,c0,c0,2 @ Read current CP15 Cache Size ID Register (CCSIDR2)
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bx lr
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// UINT32
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// ReadCLIDR (
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// IN UINT32 CSSELR
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// )
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ASM_FUNC(ReadCLIDR)
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mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
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bx lr
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ASM_FUNC(ArmReadNsacr)
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mrc p15, 0, r0, c1, c1, 2
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bx lr
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ASM_FUNC(ArmWriteNsacr)
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mcr p15, 0, r0, c1, c1, 2
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bx lr
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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@ -1,92 +0,0 @@
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2011, ARM Limited. All rights reserved.
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# Copyright (c) 2016, Linaro Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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#------------------------------------------------------------------------------
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#include <AsmMacroLib.h>
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ASM_FUNC(ArmReadCntFrq)
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mrc p15, 0, r0, c14, c0, 0 @ Read CNTFRQ
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bx lr
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ASM_FUNC(ArmWriteCntFrq)
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mcr p15, 0, r0, c14, c0, 0 @ Write to CNTFRQ
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bx lr
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ASM_FUNC(ArmReadCntPct)
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mrrc p15, 0, r0, r1, c14 @ Read CNTPT (Physical counter register)
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bx lr
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ASM_FUNC(ArmReadCntkCtl)
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mrc p15, 0, r0, c14, c1, 0 @ Read CNTK_CTL (Timer PL1 Control Register)
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bx lr
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ASM_FUNC(ArmWriteCntkCtl)
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mcr p15, 0, r0, c14, c1, 0 @ Write to CNTK_CTL (Timer PL1 Control Register)
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bx lr
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ASM_FUNC(ArmReadCntpTval)
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mrc p15, 0, r0, c14, c2, 0 @ Read CNTP_TVAL (PL1 physical timer value register)
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bx lr
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ASM_FUNC(ArmWriteCntpTval)
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mcr p15, 0, r0, c14, c2, 0 @ Write to CNTP_TVAL (PL1 physical timer value register)
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bx lr
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ASM_FUNC(ArmReadCntpCtl)
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mrc p15, 0, r0, c14, c2, 1 @ Read CNTP_CTL (PL1 Physical Timer Control Register)
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bx lr
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ASM_FUNC(ArmWriteCntpCtl)
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mcr p15, 0, r0, c14, c2, 1 @ Write to CNTP_CTL (PL1 Physical Timer Control Register)
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bx lr
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ASM_FUNC(ArmReadCntvTval)
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mrc p15, 0, r0, c14, c3, 0 @ Read CNTV_TVAL (Virtual Timer Value register)
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bx lr
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ASM_FUNC(ArmWriteCntvTval)
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mcr p15, 0, r0, c14, c3, 0 @ Write to CNTV_TVAL (Virtual Timer Value register)
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bx lr
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ASM_FUNC(ArmReadCntvCtl)
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mrc p15, 0, r0, c14, c3, 1 @ Read CNTV_CTL (Virtual Timer Control Register)
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bx lr
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ASM_FUNC(ArmWriteCntvCtl)
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mcr p15, 0, r0, c14, c3, 1 @ Write to CNTV_CTL (Virtual Timer Control Register)
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bx lr
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ASM_FUNC(ArmReadCntvCt)
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mrrc p15, 1, r0, r1, c14 @ Read CNTVCT (Virtual Count Register)
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bx lr
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ASM_FUNC(ArmReadCntpCval)
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mrrc p15, 2, r0, r1, c14 @ Read CNTP_CTVAL (Physical Timer Compare Value Register)
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bx lr
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ASM_FUNC(ArmWriteCntpCval)
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mcrr p15, 2, r0, r1, c14 @ Write to CNTP_CTVAL (Physical Timer Compare Value Register)
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bx lr
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ASM_FUNC(ArmReadCntvCval)
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mrrc p15, 3, r0, r1, c14 @ Read CNTV_CTVAL (Virtual Timer Compare Value Register)
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bx lr
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ASM_FUNC(ArmWriteCntvCval)
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mcrr p15, 3, r0, r1, c14 @ write to CNTV_CTVAL (Virtual Timer Compare Value Register)
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bx lr
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ASM_FUNC(ArmReadCntvOff)
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mrrc p15, 4, r0, r1, c14 @ Read CNTVOFF (virtual Offset register)
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bx lr
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ASM_FUNC(ArmWriteCntvOff)
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mcrr p15, 4, r0, r1, c14 @ Write to CNTVOFF (Virtual Offset register)
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bx lr
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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@ -1,81 +0,0 @@
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/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
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Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <Library/ArmLib.h>
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#include <Library/DebugLib.h>
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#include <Arm/AArch32.h>
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#include "ArmV7Lib.h"
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#include "ArmLibPrivate.h"
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/**
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Check whether the CPU supports the GIC system register interface (any version)
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@return Whether GIC System Register Interface is supported
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**/
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BOOLEAN
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EFIAPI
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ArmHasGicSystemRegisters (
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VOID
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)
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{
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return ((ArmReadIdPfr1 () & ARM_PFR1_GIC) != 0);
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}
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/**
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Check whether the CPU supports the GICv5 system register interface
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|
|
||||||
@return Whether GICv5 System Register Interface is supported
|
|
||||||
**/
|
|
||||||
BOOLEAN
|
|
||||||
EFIAPI
|
|
||||||
ArmHasGicV5SystemRegisters (
|
|
||||||
VOID
|
|
||||||
)
|
|
||||||
{
|
|
||||||
// GICv5 not supported in AArch32.
|
|
||||||
return FALSE;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
Check whether the CPU supports the Security extensions
|
|
||||||
|
|
||||||
@return Whether the Security extensions are implemented
|
|
||||||
|
|
||||||
**/
|
|
||||||
BOOLEAN
|
|
||||||
EFIAPI
|
|
||||||
ArmHasSecurityExtensions (
|
|
||||||
VOID
|
|
||||||
)
|
|
||||||
{
|
|
||||||
return ((ArmReadIdPfr1 () & ARM_PFR1_SEC) != 0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/** Checks if CCIDX is implemented.
|
|
||||||
|
|
||||||
@retval TRUE CCIDX is implemented.
|
|
||||||
@retval FALSE CCIDX is not implemented.
|
|
||||||
**/
|
|
||||||
BOOLEAN
|
|
||||||
EFIAPI
|
|
||||||
ArmHasCcidx (
|
|
||||||
VOID
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINTN Mmfr4;
|
|
||||||
|
|
||||||
Mmfr4 = ArmReadIdMmfr4 ();
|
|
||||||
return (((Mmfr4 >> 24) & 0xF) == 1) ? TRUE : FALSE;
|
|
||||||
}
|
|
||||||
@ -1,42 +0,0 @@
|
|||||||
/** @file
|
|
||||||
|
|
||||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
|
||||||
|
|
||||||
**/
|
|
||||||
|
|
||||||
#ifndef ARM_V7_LIB_H_
|
|
||||||
#define ARM_V7_LIB_H_
|
|
||||||
|
|
||||||
#define ID_MMFR0_SHARELVL_SHIFT 12
|
|
||||||
#define ID_MMFR0_SHARELVL_MASK 0xf
|
|
||||||
#define ID_MMFR0_SHARELVL_ONE 0
|
|
||||||
#define ID_MMFR0_SHARELVL_TWO 1
|
|
||||||
|
|
||||||
#define ID_MMFR0_INNERSHR_SHIFT 28
|
|
||||||
#define ID_MMFR0_INNERSHR_MASK 0xf
|
|
||||||
#define ID_MMFR0_OUTERSHR_SHIFT 8
|
|
||||||
#define ID_MMFR0_OUTERSHR_MASK 0xf
|
|
||||||
|
|
||||||
#define ID_MMFR0_SHR_IMP_UNCACHED 0
|
|
||||||
#define ID_MMFR0_SHR_IMP_HW_COHERENT 1
|
|
||||||
#define ID_MMFR0_SHR_IGNORED 0xf
|
|
||||||
|
|
||||||
/** Reads the ID_MMFR4 register.
|
|
||||||
|
|
||||||
@return The contents of the ID_MMFR4 register.
|
|
||||||
**/
|
|
||||||
UINT32
|
|
||||||
EFIAPI
|
|
||||||
ArmReadIdMmfr4 (
|
|
||||||
VOID
|
|
||||||
);
|
|
||||||
|
|
||||||
UINTN
|
|
||||||
EFIAPI
|
|
||||||
ArmReadIdPfr1 (
|
|
||||||
VOID
|
|
||||||
);
|
|
||||||
|
|
||||||
#endif // ARM_V7_LIB_H_
|
|
||||||
@ -1,236 +0,0 @@
|
|||||||
#------------------------------------------------------------------------------
|
|
||||||
#
|
|
||||||
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
|
|
||||||
# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
|
|
||||||
# Copyright (c) 2016, Linaro Limited. All rights reserved.
|
|
||||||
#
|
|
||||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
|
||||||
#
|
|
||||||
#------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
#include <AsmMacroLib.h>
|
|
||||||
|
|
||||||
.set DC_ON, (0x1<<2)
|
|
||||||
.set IC_ON, (0x1<<12)
|
|
||||||
.set CTRL_M_BIT, (1 << 0)
|
|
||||||
.set CTRL_C_BIT, (1 << 2)
|
|
||||||
.set CTRL_B_BIT, (1 << 7)
|
|
||||||
.set CTRL_I_BIT, (1 << 12)
|
|
||||||
.set CTRL_AFE_BIT,(1 << 29)
|
|
||||||
|
|
||||||
|
|
||||||
ASM_FUNC(ArmInvalidateDataCacheEntryByMVA)
|
|
||||||
mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
ASM_FUNC(ArmCleanDataCacheEntryByMVA)
|
|
||||||
mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
|
|
||||||
ASM_FUNC(ArmCleanDataCacheEntryToPoUByMVA)
|
|
||||||
mcr p15, 0, r0, c7, c11, 1 @clean single data cache line to PoU
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
ASM_FUNC(ArmInvalidateInstructionCacheEntryToPoUByMVA)
|
|
||||||
mcr p15, 0, r0, c7, c5, 1 @Invalidate single instruction cache line to PoU
|
|
||||||
mcr p15, 0, r0, c7, c5, 7 @Invalidate branch predictor
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
ASM_FUNC(ArmCleanInvalidateDataCacheEntryByMVA)
|
|
||||||
mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
|
|
||||||
ASM_FUNC(ArmInvalidateInstructionCache)
|
|
||||||
mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache
|
|
||||||
dsb
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ASM_FUNC(ArmEnableMmu)
|
|
||||||
mrc p15,0,R0,c1,c0,0
|
|
||||||
orr R0,R0,#1
|
|
||||||
orr R0,R0,#CTRL_AFE_BIT
|
|
||||||
mcr p15,0,R0,c1,c0,0
|
|
||||||
dsb
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
|
|
||||||
ASM_FUNC(ArmDisableMmu)
|
|
||||||
mrc p15,0,R0,c1,c0,0
|
|
||||||
bic R0,R0,#1
|
|
||||||
mcr p15,0,R0,c1,c0,0 @Disable MMU
|
|
||||||
|
|
||||||
mcr p15,0,R0,c8,c7,0 @Invalidate TLB
|
|
||||||
mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array
|
|
||||||
dsb
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ASM_FUNC(ArmDisableCachesAndMmu)
|
|
||||||
mrc p15, 0, r0, c1, c0, 0 @ Get control register
|
|
||||||
bic r0, r0, #CTRL_M_BIT @ Disable MMU
|
|
||||||
bic r0, r0, #CTRL_C_BIT @ Disable D Cache
|
|
||||||
bic r0, r0, #CTRL_I_BIT @ Disable I Cache
|
|
||||||
mcr p15, 0, r0, c1, c0, 0 @ Write control register
|
|
||||||
dsb
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ASM_FUNC(ArmMmuEnabled)
|
|
||||||
mrc p15,0,R0,c1,c0,0
|
|
||||||
and R0,R0,#1
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ASM_FUNC(ArmEnableDataCache)
|
|
||||||
ldr R1,=DC_ON
|
|
||||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
|
||||||
orr R0,R0,R1 @Set C bit
|
|
||||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
|
||||||
dsb
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ASM_FUNC(ArmDisableDataCache)
|
|
||||||
ldr R1,=DC_ON
|
|
||||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
|
||||||
bic R0,R0,R1 @Clear C bit
|
|
||||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
|
||||||
dsb
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ASM_FUNC(ArmEnableInstructionCache)
|
|
||||||
ldr R1,=IC_ON
|
|
||||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
|
||||||
orr R0,R0,R1 @Set I bit
|
|
||||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
|
||||||
dsb
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ASM_FUNC(ArmDisableInstructionCache)
|
|
||||||
ldr R1,=IC_ON
|
|
||||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
|
||||||
bic R0,R0,R1 @Clear I bit.
|
|
||||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
|
||||||
dsb
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ASM_FUNC(ArmEnableSWPInstruction)
|
|
||||||
mrc p15, 0, r0, c1, c0, 0
|
|
||||||
orr r0, r0, #0x00000400
|
|
||||||
mcr p15, 0, r0, c1, c0, 0
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ASM_FUNC(ArmEnableBranchPrediction)
|
|
||||||
mrc p15, 0, r0, c1, c0, 0
|
|
||||||
orr r0, r0, #0x00000800
|
|
||||||
mcr p15, 0, r0, c1, c0, 0
|
|
||||||
dsb
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ASM_FUNC(ArmDisableBranchPrediction)
|
|
||||||
mrc p15, 0, r0, c1, c0, 0
|
|
||||||
bic r0, r0, #0x00000800
|
|
||||||
mcr p15, 0, r0, c1, c0, 0
|
|
||||||
dsb
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ASM_FUNC(ArmSetLowVectors)
|
|
||||||
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
|
|
||||||
bic r0, r0, #0x00002000 @ clear V bit
|
|
||||||
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ASM_FUNC(ArmSetHighVectors)
|
|
||||||
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
|
|
||||||
orr r0, r0, #0x00002000 @ Set V bit
|
|
||||||
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ASM_FUNC(ArmDataMemoryBarrier)
|
|
||||||
dmb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ASM_FUNC(ArmDataSynchronizationBarrier)
|
|
||||||
dsb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ASM_FUNC(ArmInstructionSynchronizationBarrier)
|
|
||||||
isb
|
|
||||||
bx LR
|
|
||||||
|
|
||||||
ASM_FUNC(ArmReadVBar)
|
|
||||||
# Set the Address of the Vector Table in the VBAR register
|
|
||||||
mrc p15, 0, r0, c12, c0, 0
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
ASM_FUNC(ArmWriteVBar)
|
|
||||||
# Set the Address of the Vector Table in the VBAR register
|
|
||||||
mcr p15, 0, r0, c12, c0, 0
|
|
||||||
# Ensure the SCTLR.V bit is clear
|
|
||||||
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
|
|
||||||
bic r0, r0, #0x00002000 @ clear V bit
|
|
||||||
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
|
|
||||||
isb
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
ASM_FUNC(ArmEnableVFP)
|
|
||||||
# Read CPACR (Coprocessor Access Control Register)
|
|
||||||
mrc p15, 0, r0, c1, c0, 2
|
|
||||||
# Enable VPF access (Full Access to CP10, CP11) (V* instructions)
|
|
||||||
orr r0, r0, #0x00f00000
|
|
||||||
# Write back CPACR (Coprocessor Access Control Register)
|
|
||||||
mcr p15, 0, r0, c1, c0, 2
|
|
||||||
isb
|
|
||||||
# Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
|
|
||||||
mov r0, #0x40000000
|
|
||||||
#ifndef __clang__
|
|
||||||
mcr p10,#0x7,r0,c8,c0,#0
|
|
||||||
#else
|
|
||||||
# Set the FPU model so Clang does not choke on the next instruction
|
|
||||||
.fpu neon
|
|
||||||
vmsr fpexc, r0
|
|
||||||
#endif
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
ASM_FUNC(ArmCallWFI)
|
|
||||||
wfi
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
#Note: Return 0 in Uniprocessor implementation
|
|
||||||
ASM_FUNC(ArmReadCbar)
|
|
||||||
mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
ASM_FUNC(ArmReadMpidr)
|
|
||||||
mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
ASM_FUNC(ArmReadTpidrurw)
|
|
||||||
mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
ASM_FUNC(ArmWriteTpidrurw)
|
|
||||||
mcr p15, 0, r0, c13, c0, 2 @ write TPIDRURW
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
ASM_FUNC(ArmIsArchTimerImplemented)
|
|
||||||
mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1
|
|
||||||
and r0, r0, #0x000F0000
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
ASM_FUNC(ArmReadIdPfr1)
|
|
||||||
mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1 Register
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
|
||||||
@ -21,15 +21,6 @@
|
|||||||
ArmLibPrivate.h
|
ArmLibPrivate.h
|
||||||
ArmLib.c
|
ArmLib.c
|
||||||
|
|
||||||
[Sources.ARM]
|
|
||||||
Arm/ArmV7Lib.h
|
|
||||||
Arm/ArmV7Lib.c
|
|
||||||
|
|
||||||
Arm/ArmLibSupport.S | GCC
|
|
||||||
Arm/ArmLibSupportV7.S | GCC
|
|
||||||
Arm/ArmV7Support.S | GCC
|
|
||||||
Arm/ArmV7ArchTimerSupport.S | GCC
|
|
||||||
|
|
||||||
[Sources.AARCH64]
|
[Sources.AARCH64]
|
||||||
AArch64/AArch64Lib.h
|
AArch64/AArch64Lib.h
|
||||||
AArch64/AArch64Lib.c
|
AArch64/AArch64Lib.c
|
||||||
|
|||||||
Reference in New Issue
Block a user