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Use full 36-bit physical address space on SS10

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git-svn-id: svn://coreboot.org/openbios/openbios-devel@149 f158a5a8-5612-0410-a976-696ce0be7e32
This commit is contained in:
Blue Swirl
2007-05-19 12:55:01 +00:00
parent e8dfc37756
commit 21fb003090
12 changed files with 193 additions and 180 deletions
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84
arch/sparc32/console.c
View File

@@ -17,10 +17,10 @@
#ifdef CONFIG_DEBUG_CONSOLE_SERIAL
static unsigned long kbd_base, serial_base;
static volatile unsigned char *kbd_dev, *serial_dev;
#define CTRL(port) (serial_base + (port) * 2 + 0)
#define DATA(port) (serial_base + (port) * 2 + 2)
#define CTRL(port) serial_dev[(port) * 2 + 0]
#define DATA(port) serial_dev[(port) * 2 + 2]
/* Conversion routines to/from brg time constants from/to bits
* per second.
@@ -54,53 +54,62 @@ static unsigned long kbd_base, serial_base;
static int uart_charav(int port)
{
return ((inb(CTRL(port)) & Rx_CH_AV) != 0);
return ((CTRL(port) & Rx_CH_AV) != 0);
}
static char uart_getchar(int port)
{
while (!uart_charav(port));
return ((char) (inb(DATA(port))) & 0177);
while (!uart_charav(port))
;
return DATA(port) & 0177;
}
static void uart_putchar(int port, unsigned char c)
{
if (c == '\n')
uart_putchar(port, '\r');
while (!inb(CTRL(port)) & 4);
outb(c, DATA(port));
if (!serial_dev)
return;
if (c == '\n')
uart_putchar(port, '\r');
while (!(CTRL(port) & 4))
;
DATA(port) = c;
}
static void uart_init_line(int port, unsigned long baud)
{
outb(4, CTRL(port)); // reg 4
outb(SB1 | X16CLK, CTRL(port)); // no parity, async, 1 stop
// bit, 16x clock
CTRL(port) = 4; // reg 4
CTRL(port) = SB1 | X16CLK; // no parity, async, 1 stop bit, 16x
// clock
baud = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
baud = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
outb(12, CTRL(port)); // reg 12
outb(baud & 0xff, CTRL(port));
outb(13, CTRL(port)); // reg 13
outb((baud >> 8) & 0xff, CTRL(port));
outb(14, CTRL(port)); // reg 14
outb(BRSRC | BRENAB, CTRL(port));
CTRL(port) = 12; // reg 12
CTRL(port) = baud & 0xff;
CTRL(port) = 13; // reg 13
CTRL(port) = (baud >> 8) & 0xff;
CTRL(port) = 14; // reg 14
CTRL(port) = BRSRC | BRENAB;
outb(3, CTRL(port)); // reg 3
outb(RxENAB | Rx8, CTRL(port)); // enable rx, 8 bits/char
CTRL(port) = 3; // reg 3
CTRL(port) = RxENAB | Rx8; // enable rx, 8 bits/char
outb(5, CTRL(port)); // reg 5
outb(RTS | TxENAB | Tx8 | DTR, CTRL(port)); // enable tx, 8
// bits/char, set
// RTS & DTR
CTRL(port) = 5; // reg 5
CTRL(port) = RTS | TxENAB | Tx8 | DTR; // enable tx, 8 bits/char,
// set RTS & DTR
}
int uart_init(int port, unsigned long speed)
int uart_init(uint64_t port, unsigned long speed)
{
serial_base = ((unsigned long)port) & ~3;
uart_init_line(port & 3, speed);
return -1;
int line;
serial_dev = map_io(port & ~7ULL, 2 * 4);
serial_dev += port & 7ULL;
line = port & 3ULL;
uart_init_line(line, speed);
return -1;
}
static void serial_putchar(int c)
@@ -126,9 +135,9 @@ static void serial_cls(void)
#ifdef CONFIG_DEBUG_CONSOLE_VIDEO
#define VMEM_BASE 0x00800000
#define VMEM_BASE 0x00800000ULL
#define VMEM_SIZE (1024*768*1)
#define DAC_BASE 0x00200000
#define DAC_BASE 0x00200000ULL
#define DAC_SIZE 16
static unsigned char *vmem;
@@ -170,7 +179,7 @@ static void video_cls(void)
memset((void *)vmem, 0, VMEM_SIZE);
}
void tcx_init(unsigned long base)
void tcx_init(uint64_t base)
{
vmem = map_io(base + VMEM_BASE, VMEM_SIZE);
dac = map_io(base + DAC_BASE, DAC_SIZE);
@@ -178,9 +187,10 @@ void tcx_init(unsigned long base)
console_init();
}
void kbd_init(unsigned long base)
void kbd_init(uint64_t base)
{
kbd_base = base + 4;
kbd_dev = map_io(base, 2 * 4);
kbd_dev += 4;
}
static const unsigned char sunkbd_keycode[128] = {
@@ -216,7 +226,7 @@ static int shiftstate;
int
keyboard_dataready(void)
{
return ((inb(kbd_base) & 1) == 1);
return ((kbd_dev[0] & 1) == 1);
}
unsigned char
@@ -227,7 +237,7 @@ keyboard_readdata(void)
while (!keyboard_dataready()) { }
do {
ch = inb(kbd_base + 2) & 0xff;
ch = kbd_dev[2] & 0xff;
if (ch == 99)
shiftstate |= 1;
else if (ch == 110)

29
arch/sparc32/entry.S
View File

@@ -14,8 +14,8 @@
#define PHYS_JJ_EEPROM 0x71200000 /* [2000] MK48T08 */
#define PHYS_JJ_INTR0 0x71E00000 /* CPU0 interrupt control registers */
#define PHYS_SS10_EEPROM 0xf1200000 /* XXX Actually at 0xff1200000ULL (36 bits)*/
#define PHYS_SS10_INTR0 0xf1400000 /* 0xff1400000ULL */
#define PHYS_SS10_EEPROM 0xf1200000
#define PHYS_SS10_INTR0 0xf1400000
#define WRITE_PAUSE nop; nop; nop; /* Have to do this after %wim/%psr chg */
@@ -58,6 +58,7 @@ entry:
set PHYS_JJ_EEPROM + 0x2E, %g1
lduba [%g1] ASI_M_BYPASS, %g2
set PHYS_JJ_EEPROM + 0x30, %g1
lda [%g1] ASI_M_BYPASS, %g1
tst %g2
bz first_cpu
nop
@@ -89,30 +90,29 @@ bad_nvram:
nop
ss10:
set PHYS_SS10_EEPROM, %g1
! XXX use full 36 bits access
lduba [%g1] ASI_M_BYPASS, %g2
lduba [%g1] ASI_M_CTL, %g2
cmp %g2, 'Q'
bne bad_nvram
inc %g1
lduba [%g1] ASI_M_BYPASS, %g2
lduba [%g1] ASI_M_CTL, %g2
cmp %g2, 'E'
bne bad_nvram
inc %g1
lduba [%g1] ASI_M_BYPASS, %g2
lduba [%g1] ASI_M_CTL, %g2
cmp %g2, 'M'
bne bad_nvram
inc %g1
lduba [%g1] ASI_M_BYPASS, %g2
lduba [%g1] ASI_M_CTL, %g2
cmp %g2, 'U'
bne bad_nvram
! Ok, this is SS-10
mov 0x72, %y
! Check if this not the first SMP CPU, if so, bypass PROM entirely
! XXX use full 36 bits access
set PHYS_SS10_EEPROM + 0x2E, %g1
lduba [%g1] ASI_M_BYPASS, %g2
lduba [%g1] ASI_M_CTL, %g2
set PHYS_SS10_EEPROM + 0x30, %g1
lda [%g1] ASI_M_CTL, %g1
tst %g2
bz first_cpu
nop
@@ -120,19 +120,19 @@ ss10:
sll %g2, 12, %g2
add %g1, %g2, %g2
set 0xffffffff, %g1
sta %g1, [%g2] ASI_M_BYPASS ! clear softints
sta %g1, [%g2] ASI_M_CTL ! clear softints
add %g2, 4, %g2
sta %g0, [%g2] ASI_M_BYPASS ! clear softints
sta %g0, [%g2] ASI_M_CTL ! clear softints
set PHYS_SS10_EEPROM + 0x3C, %g1
lda [%g1] ASI_M_BYPASS, %g1
lda [%g1] ASI_M_CTL, %g1
set AC_M_CTPR, %g2
sta %g1, [%g2] ASI_M_MMUREGS ! set ctx table ptr
set PHYS_JJ_EEPROM + 0x40, %g1
lda [%g1] ASI_M_BYPASS, %g1
lda [%g1] ASI_M_CTL, %g1
set AC_M_CXR, %g2
sta %g1, [%g2] ASI_M_MMUREGS ! set context
set PHYS_SS10_EEPROM + 0x38, %g1
lda [%g1] ASI_M_BYPASS, %g2
lda [%g1] ASI_M_CTL, %g2
set 1, %g1
jmp %g2 ! jump to kernel
sta %g1, [%g0] ASI_M_MMUREGS ! enable mmu
@@ -140,7 +140,6 @@ ss10:
first_cpu:
/* Create temporary page tables and map the ROM area to end of
RAM. This will be done properly in iommu.c later. */
lda [%g1] ASI_M_BYPASS, %g1
set _end, %g3
set 0xfff, %g2
add %g3, %g2, %g3

43
arch/sparc32/openbios.c
View File

@@ -18,28 +18,25 @@
void boot(void);
void ob_ide_init(void);
void tcx_init(unsigned long base);
void kbd_init(unsigned long base);
void tcx_init(uint64_t base);
void kbd_init(uint64_t base);
int qemu_machine_type;
struct hwdef {
unsigned long iommu_high, iommu_base;
unsigned long slavio_high, slavio_base;
unsigned long intctl_base, counter_base, nvram_base, ms_kb_base, serial_base;
uint64_t iommu_base, slavio_base;
uint64_t intctl_base, counter_base, nvram_base, ms_kb_base, serial_base;
unsigned long fd_offset, counter_offset, intr_offset;
unsigned long dma_base, esp_base, le_base;
unsigned long tcx_base;
uint64_t dma_base, esp_base, le_base;
uint64_t tcx_base;
int machine_id;
};
static const struct hwdef hwdefs[] = {
/* SS-5 */
{
.iommu_high = 0x0,
.iommu_base = 0x10000000,
.tcx_base = 0x50000000,
.slavio_high = 0x0,
.slavio_base = 0x71000000,
.ms_kb_base = 0x71000000,
.serial_base = 0x71100000,
@@ -54,20 +51,18 @@ static const struct hwdef hwdefs[] = {
},
/* SS-10 */
{
.iommu_high = 0xf,
.iommu_base = 0xe0000000, // XXX Actually at 0xfe0000000ULL (36 bits)
.tcx_base = 0x20000000, // 0xe20000000ULL,
.slavio_high = 0xf,
.slavio_base = 0xf1000000, // 0xff1000000ULL,
.ms_kb_base = 0xf1000000, // 0xff1000000ULL,
.serial_base = 0xf1100000, // 0xff1100000ULL,
.nvram_base = 0xf1200000, // 0xff1200000ULL,
.iommu_base = 0xfe0000000ULL,
.tcx_base = 0xe20000000ULL,
.slavio_base = 0xff1000000ULL,
.ms_kb_base = 0xff1000000ULL,
.serial_base = 0xff1100000ULL,
.nvram_base = 0xff1200000ULL,
.fd_offset = 0x00700000, // 0xff1700000ULL,
.counter_offset = 0x00300000, // 0xff1300000ULL,
.intr_offset = 0x00400000, // 0xff1400000ULL,
.dma_base = 0xf0400000, // 0xef0400000ULL,
.esp_base = 0xf0800000, // 0xef0800000ULL,
.le_base = 0xf0c00000, // 0xef0c00000ULL,
.dma_base = 0xef0400000ULL,
.esp_base = 0xef0800000ULL,
.le_base = 0xef0c00000ULL,
.machine_id = 0x72,
},
};
@@ -95,9 +90,9 @@ arch_init( void )
void setup_timers(void);
modules_init();
ob_init_mmu(hwdef->iommu_high, hwdef->iommu_base);
ob_init_mmu(hwdef->iommu_base);
#ifdef CONFIG_DRIVER_OBIO
ob_obio_init(hwdef->slavio_high, hwdef->slavio_base, hwdef->fd_offset,
ob_obio_init(hwdef->slavio_base, hwdef->fd_offset,
hwdef->counter_offset, hwdef->intr_offset);
nvram_init();
#endif
@@ -105,7 +100,7 @@ arch_init( void )
#ifdef CONFIG_DEBUG_CONSOLE_VIDEO
init_video();
#endif
ob_sbus_init(hwdef->iommu_high, hwdef->iommu_base + 0x1000, hwdef->machine_id);
ob_sbus_init(hwdef->iommu_base + 0x1000ULL, hwdef->machine_id);
#endif
device_end();
@@ -133,7 +128,7 @@ int openbios(void)
#endif
#ifdef CONFIG_DEBUG_CONSOLE
#ifdef CONFIG_DEBUG_CONSOLE_SERIAL
uart_init(hwdef->serial_base | (CONFIG_SERIAL_PORT? 0: 4),
uart_init(hwdef->serial_base | (CONFIG_SERIAL_PORT? 0ULL: 4ULL),
CONFIG_SERIAL_SPEED);
#endif
#ifdef CONFIG_DEBUG_CONSOLE_VIDEO

2
arch/sparc32/openbios.h
View File

@@ -22,7 +22,7 @@ int openbios(void);
/* console.c */
extern void cls(void);
#ifdef CONFIG_DEBUG_CONSOLE
extern int uart_init(int port, unsigned long speed);
extern int uart_init(uint64_t port, unsigned long speed);
extern void video_init(void);
#endif

12
arch/sparc32/romvec.c
View File

@@ -313,18 +313,20 @@ static char *obp_dumb_mmap(char *va, __attribute__((unused)) int which_io,
unsigned int npages;
unsigned int off;
unsigned int mva;
uint64_t mpa = ((uint64_t)which_io << 32) | (uint64_t)pa;
DPRINTF("obp_dumb_mmap: virta 0x%x, which_io %d, paddr 0x%x, sz %d\n", (unsigned int)va, which_io, pa, size);
DPRINTF("obp_dumb_mmap: virta 0x%x, paddr 0x%llx, sz %d\n",
(unsigned int)va, mpa, size);
off = pa & (PAGE_SIZE-1);
npages = (off + size + (PAGE_SIZE-1)) / PAGE_SIZE;
pa &= ~(PAGE_SIZE-1);
npages = (off + (size - 1) + (PAGE_SIZE-1)) / PAGE_SIZE;
mpa &= ~(uint64_t)(PAGE_SIZE - 1);
mva = (unsigned int) va;
while (npages-- != 0) {
map_page(mva, pa, 1);
map_page(mva, mpa, 1);
mva += PAGE_SIZE;
pa += PAGE_SIZE;
mpa += (uint64_t)PAGE_SIZE;
}
return va;

13
drivers/esp.c
View File

@@ -25,8 +25,8 @@
#include "asm/dma.h"
#include "esp.h"
#define MACIO_ESPDMA 0x00400000 /* ESP DMA controller */
#define MACIO_ESP 0x00800000 /* ESP SCSI */
#define MACIO_ESPDMA 0x00400000ULL /* ESP DMA controller */
#define MACIO_ESP 0x00800000ULL /* ESP SCSI */
#define BUFSIZE 4096
@@ -309,10 +309,10 @@ NODE_METHODS(ob_sd) = {
static int
espdma_init(unsigned int slot, unsigned long base, unsigned long offset,
espdma_init(unsigned int slot, uint64_t base, unsigned long offset,
struct esp_dma *espdma)
{
espdma->regs = (void *)map_io(base + offset + MACIO_ESPDMA, 0x10);
espdma->regs = (void *)map_io(base + (uint64_t)offset + MACIO_ESPDMA, 0x10);
if (espdma->regs == 0) {
DPRINTF("espdma_init: cannot map registers\n");
@@ -424,7 +424,7 @@ add_alias(const char *device, const char *alias)
}
int
ob_esp_init(unsigned int slot, unsigned long base, unsigned long offset)
ob_esp_init(unsigned int slot, uint64_t base, unsigned long offset)
{
int id, diskcount = 0, cdcount = 0, *counter_ptr;
char nodebuff[256], aliasbuff[256];
@@ -444,7 +444,8 @@ ob_esp_init(unsigned int slot, unsigned long base, unsigned long offset)
return -1;
}
/* Get the IO region */
esp->ll = (void *)map_io(base + offset + MACIO_ESP, sizeof(struct esp_regs));
esp->ll = (void *)map_io(base + (uint64_t)offset + MACIO_ESP,
sizeof(struct esp_regs));
if (esp->ll == 0) {
DPRINTF("Can't map ESP registers\n");
return -1;

30
drivers/iommu.c
View File

@@ -62,7 +62,7 @@ struct iommu {
struct iommu ciommu;
static struct iommu_regs *regs;
static void iommu_init(struct iommu *t, unsigned long base);
static void iommu_init(struct iommu *t, uint64_t base);
static void
iommu_invalidate(struct iommu_regs *iregs)
@@ -159,7 +159,7 @@ find_pte(unsigned long va, int alloc)
* Create a memory mapping from va to epa.
*/
int
map_page(unsigned long va, unsigned long epa, int type)
map_page(unsigned long va, uint64_t epa, int type)
{
uint32_t pte;
unsigned long pa;
@@ -176,7 +176,7 @@ map_page(unsigned long va, unsigned long epa, int type)
pte |= SRMMU_PRIV; /* Supervisor only access */
}
*(uint32_t *)pa = pte;
DPRINTF("map_page: va 0x%lx pa 0x%lx pte 0x%x\n", va, epa, pte);
DPRINTF("map_page: va 0x%lx pa 0x%llx pte 0x%x\n", va, epa, pte);
return 0;
}
@@ -186,7 +186,7 @@ map_page(unsigned long va, unsigned long epa, int type)
* Returns va of the mapping or 0 if unsuccessful.
*/
void *
map_io(unsigned pa, int size)
map_io(uint64_t pa, int size)
{
void *va;
unsigned int npages;
@@ -202,7 +202,7 @@ map_io(unsigned pa, int size)
return va;
mva = (unsigned int) va;
DPRINTF("map_io: va 0x%p pa 0x%x off 0x%x npages %d\n", va, pa, off, npages); /* P3 */
DPRINTF("map_io: va 0x%p pa 0x%llx off 0x%x npages %d\n", va, pa, off, npages); /* P3 */
while (npages-- != 0) {
map_page(mva, pa, 1);
mva += PAGE_SIZE;
@@ -258,13 +258,15 @@ pgmap_store(void)
static void
map_pages(void)
{
unsigned long va, pa;
unsigned long va;
int size;
uint64_t pa;
size = POP();
va = POP();
(void) POP();
pa = POP();
pa <<= 32;
pa |= POP() & 0xffffffff;
for (; size > 0; size -= PAGE_SIZE, pa += PAGE_SIZE, va += PAGE_SIZE)
map_page(va, pa, 1);
@@ -273,7 +275,7 @@ map_pages(void)
void
ob_init_mmu(unsigned long bus, unsigned long base)
ob_init_mmu(uint64_t base)
{
extern unsigned int qemu_mem_size;
@@ -305,9 +307,9 @@ ob_init_mmu(unsigned long bus, unsigned long base)
push_str("/virtual-memory");
fword("find-device");
PUSH(bus);
PUSH(base >> 32);
fword("encode-int");
PUSH(base);
PUSH(base & 0xffffffff);
fword("encode-int");
fword("encode+");
PUSH(IOMMU_REGS);
@@ -344,9 +346,9 @@ ob_init_mmu(unsigned long bus, unsigned long base)
push_str("address");
fword("property");
PUSH(bus);
PUSH(base >> 32);
fword("encode-int");
PUSH(base);
PUSH(base & 0xffffffff);
fword("encode-int");
fword("encode+");
PUSH(IOMMU_REGS);
@@ -367,7 +369,7 @@ ob_init_mmu(unsigned long bus, unsigned long base)
* Switch page tables.
*/
void
init_mmu_swift(unsigned long base)
init_mmu_swift(uint64_t base)
{
unsigned int addr, i;
unsigned long pa, va;
@@ -473,7 +475,7 @@ dvma_alloc(int size, unsigned int *pphys)
* the routine is higher in food chain.
*/
static void
iommu_init(struct iommu *t, unsigned long base)
iommu_init(struct iommu *t, uint64_t base)
{
unsigned int *ptab;
int ptsize;

37
drivers/obio.c
View File

@@ -71,7 +71,7 @@ ob_new_obio_device(const char *name, const char *type)
}
static unsigned long
ob_reg(unsigned long base, unsigned long offset, unsigned long size, int map)
ob_reg(uint64_t base, uint64_t offset, unsigned long size, int map)
{
PUSH(0);
fword("encode-int");
@@ -248,7 +248,7 @@ NODE_METHODS(zs_keyboard) = {
};
static void
ob_zs_init(unsigned long base, unsigned long offset, int intr, int slave, int keyboard)
ob_zs_init(uint64_t base, uint64_t offset, int intr, int slave, int keyboard)
{
char nodebuff[256];
@@ -277,7 +277,7 @@ ob_zs_init(unsigned long base, unsigned long offset, int intr, int slave, int ke
fword("finish-device");
sprintf(nodebuff, "/obio/zs@0,%x", offset);
sprintf(nodebuff, "/obio/zs@0,%x", (int)offset & 0xffffffff);
if (keyboard) {
REGISTER_NODE_METHODS(zs_keyboard, nodebuff);
} else {
@@ -532,7 +532,7 @@ id_cpu(void)
}
static void
ob_nvram_init(unsigned long base, unsigned long offset)
ob_nvram_init(uint64_t base, uint64_t offset)
{
extern uint32_t kernel_image;
extern uint32_t kernel_size;
@@ -777,7 +777,7 @@ ob_nvram_init(unsigned long base, unsigned long offset)
}
static void
ob_fd_init(unsigned long base, unsigned long offset, int intr)
ob_fd_init(uint64_t base, uint64_t offset, int intr)
{
ob_new_obio_device("SUNW,fdtwo", "block");
@@ -790,7 +790,7 @@ ob_fd_init(unsigned long base, unsigned long offset, int intr)
static void
ob_sconfig_init(unsigned long base, unsigned long offset)
ob_sconfig_init(uint64_t base, uint64_t offset)
{
ob_new_obio_device("slavioconfig", NULL);
@@ -800,7 +800,7 @@ ob_sconfig_init(unsigned long base, unsigned long offset)
}
static void
ob_auxio_init(unsigned long base, unsigned long offset)
ob_auxio_init(uint64_t base, uint64_t offset)
{
ob_new_obio_device("auxio", NULL);
@@ -810,7 +810,7 @@ ob_auxio_init(unsigned long base, unsigned long offset)
}
static void
ob_power_init(unsigned long base, unsigned long offset, int intr)
ob_power_init(uint64_t base, uint64_t offset, int intr)
{
ob_new_obio_device("power", NULL);
@@ -822,7 +822,7 @@ ob_power_init(unsigned long base, unsigned long offset, int intr)
}
static void
ob_counter_init(unsigned long base, unsigned long offset)
ob_counter_init(uint64_t base, unsigned long offset)
{
volatile struct sun4m_timer_regs *regs;
int i;
@@ -855,7 +855,7 @@ ob_counter_init(unsigned long base, unsigned long offset)
fword("property");
regs = map_io(base + offset, sizeof(*regs));
regs = map_io(base + (uint64_t)offset, sizeof(*regs));
regs->l10_timer_limit = (((1000000/100) + 1) << 10);
regs->cpu_timers[0].l14_timer_limit = 0;
@@ -877,7 +877,7 @@ ob_counter_init(unsigned long base, unsigned long offset)
static volatile struct sun4m_intregs *intregs;
static void
ob_interrupt_init(unsigned long base, unsigned long offset)
ob_interrupt_init(uint64_t base, unsigned long offset)
{
int i;
@@ -908,7 +908,7 @@ ob_interrupt_init(unsigned long base, unsigned long offset)
push_str("reg");
fword("property");
intregs = map_io(base + offset, sizeof(*intregs));
intregs = map_io(base | (uint64_t)offset, sizeof(*intregs));
intregs->set = ~SUN4M_INT_MASKALL;
intregs->cpu_intregs[0].clear = ~0x17fff;
@@ -984,7 +984,7 @@ ob_obio_initialize(__attribute__((unused))int *idx)
}
static void
ob_set_obio_ranges(unsigned long high, unsigned long base)
ob_set_obio_ranges(uint64_t base)
{
push_str("/obio");
fword("find-device");
@@ -993,10 +993,10 @@ ob_set_obio_ranges(unsigned long high, unsigned long base)
PUSH(0);
fword("encode-int");
fword("encode+");
PUSH(high);
PUSH(base >> 32);
fword("encode-int");
fword("encode+");
PUSH(base);
PUSH(base & 0xffffffff);
fword("encode-int");
fword("encode+");
PUSH(SLAVIO_SIZE);
@@ -1029,9 +1029,8 @@ NODE_METHODS(ob_obio) = {
int
ob_obio_init(unsigned long slavio_high, unsigned long slavio_base,
unsigned long fd_offset, unsigned long counter_offset,
unsigned long intr_offset)
ob_obio_init(uint64_t slavio_base, unsigned long fd_offset,
unsigned long counter_offset, unsigned long intr_offset)
{
// All devices were integrated to NCR89C105, see
@@ -1042,7 +1041,7 @@ ob_obio_init(unsigned long slavio_high, unsigned long slavio_base,
REGISTER_NAMED_NODE(ob_obio, "/obio");
device_end();
#endif
ob_set_obio_ranges(slavio_high, slavio_base);
ob_set_obio_ranges(slavio_base);
// Zilog Z8530 serial ports, see http://www.zilog.com
// Must be before zs@0,0 or Linux won't boot

18
drivers/obio.h
View File

@@ -1,32 +1,32 @@
/* Addresses, interrupt numbers, register sizes */
#define SLAVIO_ZS 0x00000000
#define SLAVIO_ZS1 0x00100000
#define SLAVIO_ZS 0x00000000ULL
#define SLAVIO_ZS1 0x00100000ULL
#define ZS_INTR 0x2c
#define ZS_REGS 8
#define SLAVIO_NVRAM 0x00200000
#define SLAVIO_NVRAM 0x00200000ULL
#define NVRAM_SIZE 0x2000
#define NVRAM_IDPROM 0x1fd8
#define SLAVIO_FD 0x00400000
#define SLAVIO_FD 0x00400000ULL
#define FD_REGS 15
#define FD_INTR 0x2b
#define SLAVIO_SCONFIG 0x00800000
#define SLAVIO_SCONFIG 0x00800000ULL
#define SCONFIG_REGS 1
#define SLAVIO_AUXIO 0x00900000
#define SLAVIO_AUXIO 0x00900000ULL
#define AUXIO_REGS 1
#define SLAVIO_POWER 0x00910000
#define SLAVIO_POWER 0x00910000ULL
#define POWER_REGS 1
#define POWER_INTR 0x22
#define SLAVIO_COUNTER 0x00d00000
#define SLAVIO_COUNTER 0x00d00000ULL
#define COUNTER_REGS 0x10
#define SLAVIO_INTERRUPT 0x00e00000
#define SLAVIO_INTERRUPT 0x00e00000ULL
#define INTERRUPT_REGS 0x10
#define SLAVIO_SIZE 0x01000000

88
drivers/sbus.c
View File

@@ -21,21 +21,21 @@
#define SBUS_REGS 0x28
#define SBUS_SLOTS 16
#define POWER_REGS 0x10
#define POWER_OFFSET 0x0a000000
#define POWER_OFFSET 0x0a000000ULL
#define CS4231_REGS 0x40
#define CS4231_OFFSET 0x0c000000
#define CS4231_OFFSET 0x0c000000ULL
static void
ob_sbus_node_init(unsigned long bus, unsigned long base)
ob_sbus_node_init(uint64_t base)
{
void *regs;
push_str("/iommu/sbus");
fword("find-device");
PUSH(bus);
PUSH(base >> 32);
fword("encode-int");
PUSH(base);
PUSH(base & 0xffffffff);
fword("encode-int");
fword("encode+");
PUSH(SBUS_REGS);
@@ -344,7 +344,7 @@ ob_cs4231_init(unsigned int slot, unsigned long base)
}
static void
ob_macio_init(unsigned int slot, unsigned long base, unsigned long offset)
ob_macio_init(unsigned int slot, uint64_t base, unsigned long offset)
{
// All devices were integrated to NCR89C100, see
// http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
@@ -366,7 +366,7 @@ ob_macio_init(unsigned int slot, unsigned long base, unsigned long offset)
}
static void
sbus_probe_slot_ss5(unsigned int slot, unsigned long base)
sbus_probe_slot_ss5(unsigned int slot, uint64_t base)
{
// OpenBIOS and Qemu don't know how to do Sbus probing
switch(slot) {
@@ -385,7 +385,7 @@ sbus_probe_slot_ss5(unsigned int slot, unsigned long base)
}
static void
sbus_probe_slot_ss10(unsigned int slot, unsigned long base)
sbus_probe_slot_ss10(unsigned int slot, uint64_t base)
{
// OpenBIOS and Qemu don't know how to do Sbus probing
switch(slot) {
@@ -425,99 +425,105 @@ NODE_METHODS(ob_sbus_node) = {
{ "close", ob_sbus_close },
};
static const unsigned long sbus_offsets_ss5[SBUS_SLOTS][5] = {
{ 0, 0, 0x0, 0x20000000, 0x10000000,},
{ 1, 0, 0x0, 0x30000000, 0x10000000,},
{ 2, 0, 0x0, 0x40000000, 0x10000000,},
{ 3, 0, 0x0, 0x50000000, 0x10000000,},
{ 4, 0, 0x0, 0x60000000, 0x10000000,},
{ 5, 0, 0x0, 0x70000000, 0x10000000,},
struct sbus_offset {
int slot, type;
uint64_t base;
unsigned long size;
};
static const unsigned long sbus_offsets_ss10[SBUS_SLOTS][5] = {
{ 0, 0, 0xe, 0x00000000, 0x10000000,},
{ 1, 0, 0xe, 0x10000000, 0x10000000,},
{ 2, 0, 0xe, 0x20000000, 0x10000000,},
{ 3, 0, 0xe, 0x30000000, 0x10000000,},
[0xf] = { 0xf, 0, 0xe, 0xf0000000, 0x10000000,},
static const struct sbus_offset sbus_offsets_ss5[SBUS_SLOTS] = {
{ 0, 0, 0x20000000, 0x10000000,},
{ 1, 0, 0x30000000, 0x10000000,},
{ 2, 0, 0x40000000, 0x10000000,},
{ 3, 0, 0x50000000, 0x10000000,},
{ 4, 0, 0x60000000, 0x10000000,},
{ 5, 0, 0x70000000, 0x10000000,},
};
static const struct sbus_offset sbus_offsets_ss10[SBUS_SLOTS] = {
{ 0, 0, 0xe00000000ULL, 0x10000000,},
{ 1, 0, 0xe10000000ULL, 0x10000000,},
{ 2, 0, 0xe20000000ULL, 0x10000000,},
{ 3, 0, 0xe30000000ULL, 0x10000000,},
[0xf] = { 0xf, 0, 0xef0000000ULL, 0x10000000,},
};
static void
ob_add_sbus_range(const unsigned long *range, int notfirst)
ob_add_sbus_range(const struct sbus_offset *range, int notfirst)
{
if (!notfirst) {
push_str("/iommu/sbus");
fword("find-device");
}
PUSH(range[0]);
PUSH(range->slot);
fword("encode-int");
if (notfirst)
fword("encode+");
PUSH(range[1]);
PUSH(range->type);
fword("encode-int");
fword("encode+");
PUSH(range[2]);
PUSH(range->base >> 32);
fword("encode-int");
fword("encode+");
PUSH(range[3]);
PUSH(range->base & 0xffffffff);
fword("encode-int");
fword("encode+");
PUSH(range[4]);
PUSH(range->size);
fword("encode-int");
fword("encode+");
}
static int
ob_sbus_init_ss5(unsigned long bus, unsigned long base)
ob_sbus_init_ss5(uint64_t base)
{
unsigned int slot;
int notfirst = 0;
for (slot = 0; slot < SBUS_SLOTS; slot++) {
if (sbus_offsets_ss5[slot][4] > 0)
ob_add_sbus_range(sbus_offsets_ss5[slot], notfirst++);
if (sbus_offsets_ss5[slot].size > 0)
ob_add_sbus_range(&sbus_offsets_ss5[slot], notfirst++);
}
push_str("ranges");
fword("property");
for (slot = 0; slot < SBUS_SLOTS; slot++) {
if (sbus_offsets_ss5[slot][4] > 0)
sbus_probe_slot_ss5(slot, sbus_offsets_ss5[slot][3]);
if (sbus_offsets_ss5[slot].size > 0)
sbus_probe_slot_ss5(slot, sbus_offsets_ss5[slot].base);
}
return 0;
}
static int
ob_sbus_init_ss10(unsigned long bus, unsigned long base)
ob_sbus_init_ss10(uint64_t base)
{
unsigned int slot;
int notfirst = 0;
for (slot = 0; slot < SBUS_SLOTS; slot++) {
if (sbus_offsets_ss10[slot][4] > 0)
ob_add_sbus_range(sbus_offsets_ss10[slot], notfirst++);
if (sbus_offsets_ss10[slot].size > 0)
ob_add_sbus_range(&sbus_offsets_ss10[slot], notfirst++);
}
push_str("ranges");
fword("property");
for (slot = 0; slot < SBUS_SLOTS; slot++) {
if (sbus_offsets_ss10[slot][4] > 0)
sbus_probe_slot_ss10(slot, sbus_offsets_ss10[slot][3]);
if (sbus_offsets_ss10[slot].size > 0)
sbus_probe_slot_ss10(slot, sbus_offsets_ss10[slot].base);
}
return 0;
}
int ob_sbus_init(unsigned long bus, unsigned long base, int machine_id)
int ob_sbus_init(uint64_t base, int machine_id)
{
ob_sbus_node_init(bus, base);
ob_sbus_node_init(base);
switch (machine_id) {
case 0x72:
return ob_sbus_init_ss10(bus, base);
return ob_sbus_init_ss10(base);
case 0x80:
return ob_sbus_init_ss5(bus, base);
return ob_sbus_init_ss5(base);
default:
return -1;
}

9
include/openbios/drivers.h
View File

@@ -15,17 +15,16 @@
int ob_pci_init(void);
#endif
#ifdef CONFIG_DRIVER_SBUS
int ob_sbus_init(unsigned long bus, unsigned long base, int machine_id);
int ob_sbus_init(uint64_t base, int machine_id);
#endif
#ifdef CONFIG_DRIVER_IDE
int ob_ide_init(void);
#endif
#ifdef CONFIG_DRIVER_ESP
int ob_esp_init(unsigned int slot, unsigned long base, unsigned long offset);
int ob_esp_init(unsigned int slot, uint64_t base, unsigned long offset);
#endif
#ifdef CONFIG_DRIVER_OBIO
int ob_obio_init(unsigned long slavio_high, unsigned long slavio_base,
unsigned long fd_offset, unsigned long counter_offset,
unsigned long intr_offset);
int ob_obio_init(uint64_t slavio_base, unsigned long fd_offset,
unsigned long counter_offset, unsigned long intr_offset);
#endif

8
include/sparc32/io.h
View File

@@ -36,10 +36,10 @@ struct mem;
void mem_init(struct mem *t, char *begin, char *limit);
void *mem_alloc(struct mem *t, int size, int align);
void *mem_zalloc(struct mem *t, int size, int align);
int map_page(unsigned long va, unsigned long epa, int type);
void *map_io(unsigned pa, int size);
void ob_init_mmu(unsigned long bus, unsigned long base);
void init_mmu_swift(unsigned long base);
int map_page(unsigned long va, uint64_t epa, int type);
void *map_io(uint64_t pa, int size);
void ob_init_mmu(uint64_t base);
void init_mmu_swift(uint64_t base);
void *dvma_alloc(int size, unsigned int *pphys);
#ifndef BOOTSTRAP