Virtualization/openbios
1
0
Fork 0
mirror of https://gitlab.com/qemu-project/openbios.git synced 2024-02-13 08:34:06 +08:00
Code Issues Projects Releases Wiki Activity

Try to fix system reset for SMP and SS-10 cases

Browse Source 
git-svn-id: svn://coreboot.org/openbios/openbios-devel@150 f158a5a8-5612-0410-a976-696ce0be7e32
This commit is contained in:
Blue Swirl
2007-05-27 19:49:35 +00:00
parent 21fb003090
commit f4151ed546
4 changed files with 41 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
arch/sparc32/entry.S
View File

@@ -57,6 +57,7 @@ entry:
! Check if this not the first SMP CPU, if so, bypass PROM entirely ! Check if this not the first SMP CPU, if so, bypass PROM entirely
set PHYS_JJ_EEPROM + 0x2E, %g1 set PHYS_JJ_EEPROM + 0x2E, %g1
lduba [%g1] ASI_M_BYPASS, %g2 lduba [%g1] ASI_M_BYPASS, %g2
stba %g0, [%g1] ASI_M_BYPASS
set PHYS_JJ_EEPROM + 0x30, %g1 set PHYS_JJ_EEPROM + 0x30, %g1
lda [%g1] ASI_M_BYPASS, %g1 lda [%g1] ASI_M_BYPASS, %g1
tst %g2 tst %g2
@@ -71,15 +72,18 @@ entry:
add %g2, 4, %g2 add %g2, 4, %g2
sta %g0, [%g2] ASI_M_BYPASS ! clear softints sta %g0, [%g2] ASI_M_BYPASS ! clear softints
set PHYS_JJ_EEPROM + 0x3C, %g1 set PHYS_JJ_EEPROM + 0x3C, %g1
lda [%g1] ASI_M_BYPASS, %g1 lda [%g1] ASI_M_BYPASS, %g2
set AC_M_CTPR, %g2 sta %g0, [%g1] ASI_M_BYPASS
sta %g1, [%g2] ASI_M_MMUREGS ! set ctx table ptr set AC_M_CTPR, %g1
sta %g2, [%g1] ASI_M_MMUREGS ! set ctx table ptr
set PHYS_JJ_EEPROM + 0x40, %g1 set PHYS_JJ_EEPROM + 0x40, %g1
lda [%g1] ASI_M_BYPASS, %g1 lda [%g1] ASI_M_BYPASS, %g2
set AC_M_CXR, %g2 sta %g0, [%g1] ASI_M_BYPASS
sta %g1, [%g2] ASI_M_MMUREGS ! set context set AC_M_CXR, %g1
sta %g2, [%g1] ASI_M_MMUREGS ! set context
set PHYS_JJ_EEPROM + 0x38, %g1 set PHYS_JJ_EEPROM + 0x38, %g1
lda [%g1] ASI_M_BYPASS, %g2 lda [%g1] ASI_M_BYPASS, %g2
sta %g0, [%g1] ASI_M_BYPASS
set 1, %g1 set 1, %g1
jmp %g2 ! jump to kernel jmp %g2 ! jump to kernel
sta %g1, [%g0] ASI_M_MMUREGS ! enable mmu sta %g1, [%g0] ASI_M_MMUREGS ! enable mmu
@@ -111,6 +115,7 @@ ss10:
! Check if this not the first SMP CPU, if so, bypass PROM entirely ! Check if this not the first SMP CPU, if so, bypass PROM entirely
set PHYS_SS10_EEPROM + 0x2E, %g1 set PHYS_SS10_EEPROM + 0x2E, %g1
lduba [%g1] ASI_M_CTL, %g2 lduba [%g1] ASI_M_CTL, %g2
stba %g0, [%g2] ASI_M_CTL
set PHYS_SS10_EEPROM + 0x30, %g1 set PHYS_SS10_EEPROM + 0x30, %g1
lda [%g1] ASI_M_CTL, %g1 lda [%g1] ASI_M_CTL, %g1
tst %g2 tst %g2
@@ -124,15 +129,18 @@ ss10:
add %g2, 4, %g2 add %g2, 4, %g2
sta %g0, [%g2] ASI_M_CTL ! clear softints sta %g0, [%g2] ASI_M_CTL ! clear softints
set PHYS_SS10_EEPROM + 0x3C, %g1 set PHYS_SS10_EEPROM + 0x3C, %g1
lda [%g1] ASI_M_CTL, %g1 lda [%g1] ASI_M_CTL, %g2
set AC_M_CTPR, %g2 sta %g0, [%g1] ASI_M_CTL
sta %g1, [%g2] ASI_M_MMUREGS ! set ctx table ptr set AC_M_CTPR, %g1
sta %g2, [%g1] ASI_M_MMUREGS ! set ctx table ptr
set PHYS_JJ_EEPROM + 0x40, %g1 set PHYS_JJ_EEPROM + 0x40, %g1
lda [%g1] ASI_M_CTL, %g1 lda [%g1] ASI_M_CTL, %g2
set AC_M_CXR, %g2 sta %g0, [%g1] ASI_M_CTL
sta %g1, [%g2] ASI_M_MMUREGS ! set context set AC_M_CXR, %g1
sta %g2, [%g1] ASI_M_MMUREGS ! set context
set PHYS_SS10_EEPROM + 0x38, %g1 set PHYS_SS10_EEPROM + 0x38, %g1
lda [%g1] ASI_M_CTL, %g2 lda [%g1] ASI_M_CTL, %g2
sta %g0, [%g1] ASI_M_CTL
set 1, %g1 set 1, %g1
jmp %g2 ! jump to kernel jmp %g2 ! jump to kernel
sta %g1, [%g0] ASI_M_MMUREGS ! enable mmu sta %g1, [%g0] ASI_M_MMUREGS ! enable mmu

15
arch/sparc32/romvec.c
View File

@@ -246,22 +246,31 @@ static int obp_nbputchar(int ch)
static void obp_reboot(char *str) static void obp_reboot(char *str)
{ {
extern volatile int *reset_reg;
printk("rebooting (%s)\n", str); printk("rebooting (%s)\n", str);
outb(1, 0x71f00000); *reset_reg = 1;
printk("reboot failed\n");
for (;;) {} for (;;) {}
} }
static void obp_abort(void) static void obp_abort(void)
{ {
extern volatile int *power_reg;
printk("abort, power off\n"); printk("abort, power off\n");
outb(1, 0x71910000); *power_reg = 1;
printk("power off failed\n");
for (;;) {} for (;;) {}
} }
static void obp_halt(void) static void obp_halt(void)
{ {
extern volatile int *power_reg;
printk("halt, power off\n"); printk("halt, power off\n");
outb(1, 0x71910000); *power_reg = 1;
printk("power off failed\n");
for (;;) {} for (;;) {}
} }

7
drivers/obio.c
View File

@@ -809,12 +809,17 @@ ob_auxio_init(uint64_t base, uint64_t offset)
fword("finish-device"); fword("finish-device");
} }
volatile int *power_reg, *reset_reg;
static void static void
ob_power_init(uint64_t base, uint64_t offset, int intr) ob_power_init(uint64_t base, uint64_t offset, int intr)
{ {
ob_new_obio_device("power", NULL); ob_new_obio_device("power", NULL);
ob_reg(base, offset, POWER_REGS, 0); power_reg = ob_reg(base, offset, POWER_REGS, 1);
// Not in device tree
reset_reg = map_io(base + (uint64_t)SLAVIO_RESET, RESET_REGS);
ob_intr(intr); ob_intr(intr);

3
drivers/obio.h
View File

@@ -29,6 +29,9 @@
#define SLAVIO_INTERRUPT 0x00e00000ULL #define SLAVIO_INTERRUPT 0x00e00000ULL
#define INTERRUPT_REGS 0x10 #define INTERRUPT_REGS 0x10
#define SLAVIO_RESET 0x00f00000ULL
#define RESET_REGS 1
#define SLAVIO_SIZE 0x01000000 #define SLAVIO_SIZE 0x01000000
struct qemu_nvram_v1 { struct qemu_nvram_v1 {