Use pci_arch_t also on Sparc64 (but disable PCI probing for now, hangs)

git-svn-id: svn://coreboot.org/openbios/openbios-devel@270 f158a5a8-5612-0410-a976-696ce0be7e32

arch/ppc/qemu/init.c

@@ -61,7 +61,6 @@ pci_arch_t known_arch[] = {
 			    0xfe000000, 0x00800000, 0xfd000000, 0x01000000,
 			  },
 };
-pci_arch_t *arch;
 uint32_t isa_io_base;
 
 void

arch/sparc64/openbios.c

@@ -16,6 +16,8 @@
 #include "openbios/nvram.h"
 #include "sys_info.h"
 #include "openbios.h"
+#include "openbios/pci.h"
+#include "asm/pci.h"
 #include "libc/byteorder.h"
 #define cpu_to_be16(x) __cpu_to_be16(x)
 #include "openbios/firmware_abi.h"
@@ -30,6 +32,10 @@
 #define BIOS_CFG_CMD  0x510
 #define BIOS_CFG_DATA 0x511
 
+#define APB_SPECIAL_BASE     0x1fe00000000ULL
+#define PCI_CONFIG           (APB_SPECIAL_BASE + 0x1000000ULL)
+#define APB_MEM_BASE         0x1ff00000000ULL
+
 static unsigned char intdict[256 * 1024];
 
 // XXX
@@ -45,6 +51,26 @@ static char obio_cmdline[OBIO_CMDLINE_MAX];
 
 static uint8_t idprom[32];
 
+struct hwdef {
+    pci_arch_t pci;
+    uint8_t machine_id_low, machine_id_high;
+};
+
+static const struct hwdef hwdefs[] = {
+    {
+        .pci.cfg_addr = PCI_CONFIG,
+        .pci.cfg_data = 0,
+        .pci.cfg_base = 0x80000000ULL,
+        .pci.cfg_len = 0,
+        .pci.mem_base = 0,
+        .pci.mem_len = 0,
+        .pci.io_base = 0,
+        .pci.io_len = 0,
+        .machine_id_low = 0,
+        .machine_id_high = 255,
+    },
+};
+
 struct cpudef {
     unsigned long iu_version;
     const char *name;
@@ -818,9 +844,26 @@ static void init_memory(void)
 static void
 arch_init( void )
 {
+        unsigned int i;
+        uint8_t qemu_machine_type;
+        const struct hwdef *hwdef;
+
+        outw(__cpu_to_le16(FW_CFG_MACHINE_ID), BIOS_CFG_CMD);
+        qemu_machine_type = inb(BIOS_CFG_DATA);
+
+        for (i = 0; i < sizeof(hwdefs) / sizeof(struct hwdef); i++) {
+            if (hwdefs[i].machine_id_low <= qemu_machine_type &&
+                hwdefs[i].machine_id_high >= qemu_machine_type) {
+                hwdef = &hwdefs[i];
+                break;
+            }
+        }
+        if (!hwdef)
+            for(;;); // Internal inconsistency, hang
+
 	modules_init();
 #ifdef CONFIG_DRIVER_PCI
-	ob_pci_init();
+        //ob_pci_init();
 #endif
 #ifdef CONFIG_DRIVER_IDE
 	setup_timers();

drivers/pci.c

@@ -29,6 +29,8 @@
 /* DECLARE data structures for the nodes.  */
 DECLARE_UNNAMED_NODE( ob_pci_node, INSTALL_OPEN, 2*sizeof(int) );
 
+pci_arch_t *arch;
+
 static void
 ob_pci_open(int *idx)
 {

drivers/pci.h

@@ -54,8 +54,6 @@
 #define PCI_MIN_GNT             0x3e    /* 8 bits */
 #define PCI_MAX_LAT             0x3f    /* 8 bits */
 
-typedef uint32_t pci_addr;
-
 typedef struct {
         u16     signature;
         u8      reserved[0x16];

include/openbios/pci.h

@@ -1,22 +1,26 @@
 #ifndef _H_PCI
 #define _H_PCI
 
+typedef uint32_t pci_addr;
+
 typedef struct pci_arch_t pci_arch_t;
 
 struct pci_arch_t {
-	char * name;
+    const char * name;
-	uint16_t vendor_id;
+    uint16_t vendor_id;
-	uint16_t device_id;
+    uint16_t device_id;
-	uint32_t cfg_addr;
+    unsigned long cfg_addr;
-	uint32_t cfg_data;
+    unsigned long cfg_data;
-	uint32_t cfg_base;
+    unsigned long cfg_base;
-	uint32_t cfg_len;
+    unsigned long cfg_len;
-	uint32_t mem_base;
+    unsigned long mem_base;
-	uint32_t mem_len;
+    unsigned long mem_len;
-	uint32_t io_base;
+    unsigned long io_base;
-	uint32_t io_len;
+    unsigned long io_len;
-	uint32_t rbase;
+    unsigned long rbase;
-	uint32_t rlen;
+    unsigned long rlen;
 };
 
+extern pci_arch_t *arch;
+
 #endif	/* _H_PCI */

include/ppc/pci.h

@@ -3,7 +3,7 @@
 
 #include "asm/io.h"
 
-#if !(PCI_CONFIG_1 || PCI_CONFIG_2)
+#if !(defined(PCI_CONFIG_1) || defined(PCI_CONFIG_2))
 #define PCI_CONFIG_1 1 /* default */
 #endif
 
@@ -11,8 +11,6 @@
 
 /* PCI Configuration Mechanism #1 */
 
-extern pci_arch_t *arch;
-
 #define PCI_ADDR(bus, dev, fn) \
     ((pci_addr) (arch->cfg_base \
 		| (uint32_t) (bus) << 16 \

include/sparc64/pci.h

@@ -11,10 +11,8 @@
 
 /* PCI Configuration Mechanism #1 */
 
-/* Have pci_addr in the same format as the values written to 0xcf8
- * so register accesses can be made easy. */
 #define PCI_ADDR(bus, dev, fn) \
-    ((pci_addr) (0x80000000u \
+    ((pci_addr) (arch->cfg_base \
 		| (uint32_t) (bus) << 16 \
 		| (uint32_t) (dev) << 11 \
 		| (uint32_t) (fn) << 8))
@@ -23,46 +21,47 @@
 #define PCI_DEV(pcidev) ((uint8_t) ((pcidev) >> 11) & 0x1f)
 #define PCI_FN(pcidev) ((uint8_t) ((pcidev) >> 8) & 7)
 
-#define APB_SPECIAL_BASE     0x1fe00000000ULL
-#define PCI_CONFIG           (APB_SPECIAL_BASE + 0x1000000ULL)
-#define APB_MEM_BASE	     0x1ff00000000ULL
-
 static inline uint8_t pci_config_read8(pci_addr dev, uint8_t reg)
 {
-    out_le32((void *)PCI_CONFIG, dev | (reg & ~3));
+	uint8_t res;
-    return in_8((void *)(APB_MEM_BASE | (reg & 3)));
+	out_le32((unsigned *)arch->cfg_addr, dev | (reg & ~3));
+	res = in_8((unsigned char*)(arch->cfg_data + (reg & 3)));
+	return res;
 }
 
 static inline uint16_t pci_config_read16(pci_addr dev, uint8_t reg)
 {
-    out_le32((void *)PCI_CONFIG, dev | (reg & ~3));
+	uint16_t res;
-    return in_le16((void *)(APB_MEM_BASE | (reg & 2)));
+	out_le32((unsigned *)arch->cfg_addr, dev | (reg & ~3));
+	res = in_le16((unsigned short*)(arch->cfg_data + (reg & 2)));
+	return res;
 }
 
 static inline uint32_t pci_config_read32(pci_addr dev, uint8_t reg)
 {
-    out_le32((void *)PCI_CONFIG, dev | reg);
+	uint32_t res;
-    return in_le32((void *)(APB_MEM_BASE | reg));
+	out_le32((unsigned *)arch->cfg_addr, dev | reg);
+	res = in_le32((unsigned *)(arch->cfg_data + reg));
+	return res;
 }
 
 static inline void pci_config_write8(pci_addr dev, uint8_t reg, uint8_t val)
 {
-    out_le32((void *)PCI_CONFIG, dev | (reg & ~3));
+	out_le32((unsigned *)arch->cfg_addr, dev | (reg & ~3));
-    out_8((void *)(APB_MEM_BASE | (reg & 3)), val);
+	out_8((unsigned char*)(arch->cfg_data + (reg & 3)), val);
 }
 
 static inline void pci_config_write16(pci_addr dev, uint8_t reg, uint16_t val)
 {
-    out_le32((void *)PCI_CONFIG, dev | (reg & ~3));
+	out_le32((unsigned *)arch->cfg_addr, dev | (reg & ~3));
-    out_le16((void *)(APB_MEM_BASE | (reg & 2)), val);
+	out_le16((unsigned short *)(arch->cfg_data + (reg & 2)), val);
 }
 
 static inline void pci_config_write32(pci_addr dev, uint8_t reg, uint32_t val)
 {
-    out_le32((void *)PCI_CONFIG, dev | reg);
+	out_le32((unsigned *)arch->cfg_addr, dev | reg);
-    out_le32((void *)(APB_MEM_BASE | reg), val);
+	out_le32((unsigned *)(arch->cfg_data + reg), val);
 }
-
 #else /* !PCI_CONFIG_1 */
 #error PCI Configuration Mechanism is not specified or implemented
 #endif