2018-12-11 21:54:06 +08:00
|
|
|
/*
|
2019-01-24 14:11:10 +08:00
|
|
|
* SPDX-License-Identifier: BSD-2-Clause
|
|
|
|
*
|
|
|
|
* Copyright (c) 2019 Western Digital Corporation or its affiliates.
|
2018-12-11 21:54:06 +08:00
|
|
|
*
|
|
|
|
* Authors:
|
|
|
|
* Anup Patel <anup.patel@wdc.com>
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <sbi/riscv_asm.h>
|
|
|
|
#include <sbi/riscv_encoding.h>
|
|
|
|
#include <sbi/sbi_error.h>
|
2019-11-26 18:36:29 +08:00
|
|
|
#include <sbi/sbi_platform.h>
|
2021-09-16 12:32:50 +08:00
|
|
|
#include <sbi/sbi_console.h>
|
2019-11-26 18:36:29 +08:00
|
|
|
|
2019-11-27 14:16:52 +08:00
|
|
|
/* determine CPU extension, return non-zero support */
|
|
|
|
int misa_extension_imp(char ext)
|
2019-11-26 18:36:29 +08:00
|
|
|
{
|
|
|
|
unsigned long misa = csr_read(CSR_MISA);
|
|
|
|
|
2020-05-05 14:16:25 +08:00
|
|
|
if (misa) {
|
|
|
|
if ('A' <= ext && ext <= 'Z')
|
|
|
|
return misa & (1 << (ext - 'A'));
|
|
|
|
if ('a' <= ext && ext <= 'z')
|
|
|
|
return misa & (1 << (ext - 'a'));
|
|
|
|
return 0;
|
|
|
|
}
|
2019-11-26 18:36:29 +08:00
|
|
|
|
|
|
|
return sbi_platform_misa_extension(sbi_platform_thishart_ptr(), ext);
|
|
|
|
}
|
|
|
|
|
|
|
|
int misa_xlen(void)
|
|
|
|
{
|
|
|
|
long r;
|
|
|
|
|
|
|
|
if (csr_read(CSR_MISA) == 0)
|
|
|
|
return sbi_platform_misa_xlen(sbi_platform_thishart_ptr());
|
|
|
|
|
|
|
|
__asm__ __volatile__(
|
|
|
|
"csrr t0, misa\n\t"
|
|
|
|
"slti t1, t0, 0\n\t"
|
|
|
|
"slli t1, t1, 1\n\t"
|
|
|
|
"slli t0, t0, 1\n\t"
|
|
|
|
"slti t0, t0, 0\n\t"
|
|
|
|
"add %0, t0, t1"
|
|
|
|
: "=r"(r)
|
|
|
|
:
|
|
|
|
: "t0", "t1");
|
|
|
|
|
|
|
|
return r ? r : -1;
|
|
|
|
}
|
2018-12-11 21:54:06 +08:00
|
|
|
|
2020-05-05 14:16:25 +08:00
|
|
|
void misa_string(int xlen, char *out, unsigned int out_sz)
|
|
|
|
{
|
|
|
|
unsigned int i, pos = 0;
|
|
|
|
const char valid_isa_order[] = "iemafdqclbjtpvnsuhkorwxyzg";
|
|
|
|
|
|
|
|
if (!out)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (5 <= (out_sz - pos)) {
|
|
|
|
out[pos++] = 'r';
|
|
|
|
out[pos++] = 'v';
|
|
|
|
switch (xlen) {
|
|
|
|
case 1:
|
|
|
|
out[pos++] = '3';
|
|
|
|
out[pos++] = '2';
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
out[pos++] = '6';
|
|
|
|
out[pos++] = '4';
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
out[pos++] = '1';
|
|
|
|
out[pos++] = '2';
|
|
|
|
out[pos++] = '8';
|
|
|
|
break;
|
|
|
|
default:
|
lib: sbi: Improve fatal error handling
BUG and BUG_ON are not informative and are rather lazy interfaces, only
telling the user that something went wrong in a given function, but not
what, requiring the user to find the sources corresponding to their
firmware (which may not be available) and figure out how that BUG(_ON)
was hit. Even SBI_ASSERT in its current form, which does include the
condition that triggered it in the output, isn't necessarily very
informative. In some cases, the error may be fixable by the user, but
they need to know the problem in order to have any hope of fixing it.
It's also a nuisance for developers, whose development trees may have
changed significantly since the release in question being used, and so
line numbers can make it harder for them to understand which error case
a user has hit.
This patch introduces a new sbi_panic function which is printf-like,
allowing detailed error messages to be printed to the console. BUG and
BUG_ON are removed, since the former is just a worse form of sbi_panic
and the latter is a worse version of SBI_ASSERT. Finally, SBI_ASSERT is
augmented to take a set of arguments to pass to sbi_panic on failure,
used like so (sbi_boot_print_hart's current error case, which currently
manually calls sbi_printf and sbi_hart_hang):
SBI_ASSERT(xlen >= 1, ("Error %d getting MISA XLEN\n", xlen));
The existing users of BUG are replaced with calls to sbi_panic along
with informative error messages. BUG_ON and SBI_ASSERT were unused (and,
in the case of SBI_ASSERT, remain unused).
Many existing users of sbi_hart_hang should be converted to use either
sbi_panic or SBI_ASSERT after this commit.
Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
2021-11-22 01:30:22 +08:00
|
|
|
sbi_panic("%s: Unknown misa.MXL encoding %d",
|
|
|
|
__func__, xlen);
|
2020-05-05 14:16:25 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < array_size(valid_isa_order) && (pos < out_sz); i++) {
|
|
|
|
if (misa_extension_imp(valid_isa_order[i]))
|
|
|
|
out[pos++] = valid_isa_order[i];
|
|
|
|
}
|
|
|
|
|
|
|
|
if (pos < out_sz)
|
|
|
|
out[pos++] = '\0';
|
|
|
|
}
|
|
|
|
|
2018-12-11 21:54:06 +08:00
|
|
|
unsigned long csr_read_num(int csr_num)
|
|
|
|
{
|
2020-08-18 15:58:08 +08:00
|
|
|
#define switchcase_csr_read(__csr_num, __val) \
|
|
|
|
case __csr_num: \
|
|
|
|
__val = csr_read(__csr_num); \
|
|
|
|
break;
|
|
|
|
#define switchcase_csr_read_2(__csr_num, __val) \
|
|
|
|
switchcase_csr_read(__csr_num + 0, __val) \
|
|
|
|
switchcase_csr_read(__csr_num + 1, __val)
|
|
|
|
#define switchcase_csr_read_4(__csr_num, __val) \
|
|
|
|
switchcase_csr_read_2(__csr_num + 0, __val) \
|
|
|
|
switchcase_csr_read_2(__csr_num + 2, __val)
|
|
|
|
#define switchcase_csr_read_8(__csr_num, __val) \
|
|
|
|
switchcase_csr_read_4(__csr_num + 0, __val) \
|
|
|
|
switchcase_csr_read_4(__csr_num + 4, __val)
|
|
|
|
#define switchcase_csr_read_16(__csr_num, __val) \
|
|
|
|
switchcase_csr_read_8(__csr_num + 0, __val) \
|
|
|
|
switchcase_csr_read_8(__csr_num + 8, __val)
|
|
|
|
#define switchcase_csr_read_32(__csr_num, __val) \
|
|
|
|
switchcase_csr_read_16(__csr_num + 0, __val) \
|
|
|
|
switchcase_csr_read_16(__csr_num + 16, __val)
|
|
|
|
#define switchcase_csr_read_64(__csr_num, __val) \
|
|
|
|
switchcase_csr_read_32(__csr_num + 0, __val) \
|
|
|
|
switchcase_csr_read_32(__csr_num + 32, __val)
|
|
|
|
|
2018-12-11 21:54:06 +08:00
|
|
|
unsigned long ret = 0;
|
|
|
|
|
|
|
|
switch (csr_num) {
|
2020-08-18 15:58:08 +08:00
|
|
|
switchcase_csr_read_16(CSR_PMPCFG0, ret)
|
|
|
|
switchcase_csr_read_64(CSR_PMPADDR0, ret)
|
2021-07-11 00:18:09 +08:00
|
|
|
switchcase_csr_read(CSR_MCYCLE, ret)
|
|
|
|
switchcase_csr_read(CSR_MINSTRET, ret)
|
|
|
|
switchcase_csr_read(CSR_MHPMCOUNTER3, ret)
|
|
|
|
switchcase_csr_read_4(CSR_MHPMCOUNTER4, ret)
|
|
|
|
switchcase_csr_read_8(CSR_MHPMCOUNTER8, ret)
|
|
|
|
switchcase_csr_read_16(CSR_MHPMCOUNTER16, ret)
|
2021-11-09 02:52:57 +08:00
|
|
|
switchcase_csr_read(CSR_MCOUNTINHIBIT, ret)
|
|
|
|
switchcase_csr_read(CSR_MHPMEVENT3, ret)
|
|
|
|
switchcase_csr_read_4(CSR_MHPMEVENT4, ret)
|
|
|
|
switchcase_csr_read_8(CSR_MHPMEVENT8, ret)
|
|
|
|
switchcase_csr_read_16(CSR_MHPMEVENT16, ret)
|
2021-07-11 00:18:09 +08:00
|
|
|
#if __riscv_xlen == 32
|
|
|
|
switchcase_csr_read(CSR_MCYCLEH, ret)
|
|
|
|
switchcase_csr_read(CSR_MINSTRETH, ret)
|
|
|
|
switchcase_csr_read(CSR_MHPMCOUNTER3H, ret)
|
|
|
|
switchcase_csr_read_4(CSR_MHPMCOUNTER4H, ret)
|
|
|
|
switchcase_csr_read_8(CSR_MHPMCOUNTER8H, ret)
|
|
|
|
switchcase_csr_read_16(CSR_MHPMCOUNTER16H, ret)
|
2022-04-29 02:48:29 +08:00
|
|
|
/**
|
|
|
|
* The CSR range MHPMEVENT[3-16]H are available only if sscofpmf
|
|
|
|
* extension is present. The caller must ensure that.
|
|
|
|
*/
|
2021-11-09 02:52:57 +08:00
|
|
|
switchcase_csr_read(CSR_MHPMEVENT3H, ret)
|
|
|
|
switchcase_csr_read_4(CSR_MHPMEVENT4H, ret)
|
|
|
|
switchcase_csr_read_8(CSR_MHPMEVENT8H, ret)
|
|
|
|
switchcase_csr_read_16(CSR_MHPMEVENT16H, ret)
|
2021-07-11 00:18:09 +08:00
|
|
|
#endif
|
|
|
|
|
2018-12-11 21:54:06 +08:00
|
|
|
default:
|
lib: sbi: Improve fatal error handling
BUG and BUG_ON are not informative and are rather lazy interfaces, only
telling the user that something went wrong in a given function, but not
what, requiring the user to find the sources corresponding to their
firmware (which may not be available) and figure out how that BUG(_ON)
was hit. Even SBI_ASSERT in its current form, which does include the
condition that triggered it in the output, isn't necessarily very
informative. In some cases, the error may be fixable by the user, but
they need to know the problem in order to have any hope of fixing it.
It's also a nuisance for developers, whose development trees may have
changed significantly since the release in question being used, and so
line numbers can make it harder for them to understand which error case
a user has hit.
This patch introduces a new sbi_panic function which is printf-like,
allowing detailed error messages to be printed to the console. BUG and
BUG_ON are removed, since the former is just a worse form of sbi_panic
and the latter is a worse version of SBI_ASSERT. Finally, SBI_ASSERT is
augmented to take a set of arguments to pass to sbi_panic on failure,
used like so (sbi_boot_print_hart's current error case, which currently
manually calls sbi_printf and sbi_hart_hang):
SBI_ASSERT(xlen >= 1, ("Error %d getting MISA XLEN\n", xlen));
The existing users of BUG are replaced with calls to sbi_panic along
with informative error messages. BUG_ON and SBI_ASSERT were unused (and,
in the case of SBI_ASSERT, remain unused).
Many existing users of sbi_hart_hang should be converted to use either
sbi_panic or SBI_ASSERT after this commit.
Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
2021-11-22 01:30:22 +08:00
|
|
|
sbi_panic("%s: Unknown CSR %#x", __func__, csr_num);
|
2018-12-11 21:54:06 +08:00
|
|
|
break;
|
|
|
|
};
|
|
|
|
|
|
|
|
return ret;
|
2020-08-18 15:58:08 +08:00
|
|
|
|
|
|
|
#undef switchcase_csr_read_64
|
|
|
|
#undef switchcase_csr_read_32
|
|
|
|
#undef switchcase_csr_read_16
|
|
|
|
#undef switchcase_csr_read_8
|
|
|
|
#undef switchcase_csr_read_4
|
|
|
|
#undef switchcase_csr_read_2
|
|
|
|
#undef switchcase_csr_read
|
2018-12-11 21:54:06 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void csr_write_num(int csr_num, unsigned long val)
|
|
|
|
{
|
2020-08-18 15:58:08 +08:00
|
|
|
#define switchcase_csr_write(__csr_num, __val) \
|
|
|
|
case __csr_num: \
|
|
|
|
csr_write(__csr_num, __val); \
|
|
|
|
break;
|
|
|
|
#define switchcase_csr_write_2(__csr_num, __val) \
|
|
|
|
switchcase_csr_write(__csr_num + 0, __val) \
|
|
|
|
switchcase_csr_write(__csr_num + 1, __val)
|
|
|
|
#define switchcase_csr_write_4(__csr_num, __val) \
|
|
|
|
switchcase_csr_write_2(__csr_num + 0, __val) \
|
|
|
|
switchcase_csr_write_2(__csr_num + 2, __val)
|
|
|
|
#define switchcase_csr_write_8(__csr_num, __val) \
|
|
|
|
switchcase_csr_write_4(__csr_num + 0, __val) \
|
|
|
|
switchcase_csr_write_4(__csr_num + 4, __val)
|
|
|
|
#define switchcase_csr_write_16(__csr_num, __val) \
|
|
|
|
switchcase_csr_write_8(__csr_num + 0, __val) \
|
|
|
|
switchcase_csr_write_8(__csr_num + 8, __val)
|
|
|
|
#define switchcase_csr_write_32(__csr_num, __val) \
|
|
|
|
switchcase_csr_write_16(__csr_num + 0, __val) \
|
|
|
|
switchcase_csr_write_16(__csr_num + 16, __val)
|
|
|
|
#define switchcase_csr_write_64(__csr_num, __val) \
|
|
|
|
switchcase_csr_write_32(__csr_num + 0, __val) \
|
|
|
|
switchcase_csr_write_32(__csr_num + 32, __val)
|
|
|
|
|
2018-12-11 21:54:06 +08:00
|
|
|
switch (csr_num) {
|
2020-08-18 15:58:08 +08:00
|
|
|
switchcase_csr_write_16(CSR_PMPCFG0, val)
|
|
|
|
switchcase_csr_write_64(CSR_PMPADDR0, val)
|
2021-07-11 00:18:09 +08:00
|
|
|
switchcase_csr_write(CSR_MCYCLE, val)
|
|
|
|
switchcase_csr_write(CSR_MINSTRET, val)
|
|
|
|
switchcase_csr_write(CSR_MHPMCOUNTER3, val)
|
|
|
|
switchcase_csr_write_4(CSR_MHPMCOUNTER4, val)
|
|
|
|
switchcase_csr_write_8(CSR_MHPMCOUNTER8, val)
|
|
|
|
switchcase_csr_write_16(CSR_MHPMCOUNTER16, val)
|
|
|
|
#if __riscv_xlen == 32
|
|
|
|
switchcase_csr_write(CSR_MCYCLEH, val)
|
|
|
|
switchcase_csr_write(CSR_MINSTRETH, val)
|
|
|
|
switchcase_csr_write(CSR_MHPMCOUNTER3H, val)
|
|
|
|
switchcase_csr_write_4(CSR_MHPMCOUNTER4H, val)
|
|
|
|
switchcase_csr_write_8(CSR_MHPMCOUNTER8H, val)
|
|
|
|
switchcase_csr_write_16(CSR_MHPMCOUNTER16H, val)
|
2021-11-09 02:52:57 +08:00
|
|
|
switchcase_csr_write(CSR_MHPMEVENT3H, val)
|
|
|
|
switchcase_csr_write_4(CSR_MHPMEVENT4H, val)
|
|
|
|
switchcase_csr_write_8(CSR_MHPMEVENT8H, val)
|
|
|
|
switchcase_csr_write_16(CSR_MHPMEVENT16H, val)
|
2021-07-11 00:18:09 +08:00
|
|
|
#endif
|
|
|
|
switchcase_csr_write(CSR_MCOUNTINHIBIT, val)
|
|
|
|
switchcase_csr_write(CSR_MHPMEVENT3, val)
|
|
|
|
switchcase_csr_write_4(CSR_MHPMEVENT4, val)
|
|
|
|
switchcase_csr_write_8(CSR_MHPMEVENT8, val)
|
|
|
|
switchcase_csr_write_16(CSR_MHPMEVENT16, val)
|
|
|
|
|
2018-12-11 21:54:06 +08:00
|
|
|
default:
|
lib: sbi: Improve fatal error handling
BUG and BUG_ON are not informative and are rather lazy interfaces, only
telling the user that something went wrong in a given function, but not
what, requiring the user to find the sources corresponding to their
firmware (which may not be available) and figure out how that BUG(_ON)
was hit. Even SBI_ASSERT in its current form, which does include the
condition that triggered it in the output, isn't necessarily very
informative. In some cases, the error may be fixable by the user, but
they need to know the problem in order to have any hope of fixing it.
It's also a nuisance for developers, whose development trees may have
changed significantly since the release in question being used, and so
line numbers can make it harder for them to understand which error case
a user has hit.
This patch introduces a new sbi_panic function which is printf-like,
allowing detailed error messages to be printed to the console. BUG and
BUG_ON are removed, since the former is just a worse form of sbi_panic
and the latter is a worse version of SBI_ASSERT. Finally, SBI_ASSERT is
augmented to take a set of arguments to pass to sbi_panic on failure,
used like so (sbi_boot_print_hart's current error case, which currently
manually calls sbi_printf and sbi_hart_hang):
SBI_ASSERT(xlen >= 1, ("Error %d getting MISA XLEN\n", xlen));
The existing users of BUG are replaced with calls to sbi_panic along
with informative error messages. BUG_ON and SBI_ASSERT were unused (and,
in the case of SBI_ASSERT, remain unused).
Many existing users of sbi_hart_hang should be converted to use either
sbi_panic or SBI_ASSERT after this commit.
Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
2021-11-22 01:30:22 +08:00
|
|
|
sbi_panic("%s: Unknown CSR %#x", __func__, csr_num);
|
2018-12-11 21:54:06 +08:00
|
|
|
break;
|
|
|
|
};
|
2020-08-18 15:58:08 +08:00
|
|
|
|
|
|
|
#undef switchcase_csr_write_64
|
|
|
|
#undef switchcase_csr_write_32
|
|
|
|
#undef switchcase_csr_write_16
|
|
|
|
#undef switchcase_csr_write_8
|
|
|
|
#undef switchcase_csr_write_4
|
|
|
|
#undef switchcase_csr_write_2
|
|
|
|
#undef switchcase_csr_write
|
2018-12-11 21:54:06 +08:00
|
|
|
}
|
|
|
|
|
2020-02-18 11:56:33 +08:00
|
|
|
static unsigned long ctz(unsigned long x)
|
|
|
|
{
|
|
|
|
unsigned long ret = 0;
|
|
|
|
|
2021-09-15 14:50:52 +08:00
|
|
|
if (x == 0)
|
|
|
|
return 8 * sizeof(x);
|
|
|
|
|
2020-02-18 11:56:33 +08:00
|
|
|
while (!(x & 1UL)) {
|
|
|
|
ret++;
|
|
|
|
x = x >> 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2019-04-11 08:41:52 +08:00
|
|
|
int pmp_set(unsigned int n, unsigned long prot, unsigned long addr,
|
|
|
|
unsigned long log2len)
|
2018-12-11 21:54:06 +08:00
|
|
|
{
|
|
|
|
int pmpcfg_csr, pmpcfg_shift, pmpaddr_csr;
|
|
|
|
unsigned long cfgmask, pmpcfg;
|
|
|
|
unsigned long addrmask, pmpaddr;
|
|
|
|
|
|
|
|
/* check parameters */
|
2019-04-11 08:41:52 +08:00
|
|
|
if (n >= PMP_COUNT || log2len > __riscv_xlen || log2len < PMP_SHIFT)
|
2018-12-11 21:54:06 +08:00
|
|
|
return SBI_EINVAL;
|
|
|
|
|
2020-03-09 11:52:41 +08:00
|
|
|
/* calculate PMP register and offset */
|
2018-12-11 21:54:06 +08:00
|
|
|
#if __riscv_xlen == 32
|
2019-04-11 08:41:52 +08:00
|
|
|
pmpcfg_csr = CSR_PMPCFG0 + (n >> 2);
|
2018-12-11 21:54:06 +08:00
|
|
|
pmpcfg_shift = (n & 3) << 3;
|
|
|
|
#elif __riscv_xlen == 64
|
2019-04-11 08:41:52 +08:00
|
|
|
pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1;
|
2018-12-11 21:54:06 +08:00
|
|
|
pmpcfg_shift = (n & 7) << 3;
|
|
|
|
#else
|
2022-03-16 00:22:38 +08:00
|
|
|
# error "Unexpected __riscv_xlen"
|
2018-12-11 21:54:06 +08:00
|
|
|
#endif
|
|
|
|
pmpaddr_csr = CSR_PMPADDR0 + n;
|
|
|
|
|
|
|
|
/* encode PMP config */
|
2021-11-08 17:43:03 +08:00
|
|
|
prot &= ~PMP_A;
|
2018-12-11 21:54:06 +08:00
|
|
|
prot |= (log2len == PMP_SHIFT) ? PMP_A_NA4 : PMP_A_NAPOT;
|
2020-06-19 11:55:19 +08:00
|
|
|
cfgmask = ~(0xffUL << pmpcfg_shift);
|
2019-04-11 08:41:52 +08:00
|
|
|
pmpcfg = (csr_read_num(pmpcfg_csr) & cfgmask);
|
2018-12-11 21:54:06 +08:00
|
|
|
pmpcfg |= ((prot << pmpcfg_shift) & ~cfgmask);
|
|
|
|
|
|
|
|
/* encode PMP address */
|
|
|
|
if (log2len == PMP_SHIFT) {
|
|
|
|
pmpaddr = (addr >> PMP_SHIFT);
|
|
|
|
} else {
|
|
|
|
if (log2len == __riscv_xlen) {
|
|
|
|
pmpaddr = -1UL;
|
|
|
|
} else {
|
|
|
|
addrmask = (1UL << (log2len - PMP_SHIFT)) - 1;
|
2019-04-11 08:41:52 +08:00
|
|
|
pmpaddr = ((addr >> PMP_SHIFT) & ~addrmask);
|
2018-12-11 21:54:06 +08:00
|
|
|
pmpaddr |= (addrmask >> 1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* write csrs */
|
|
|
|
csr_write_num(pmpaddr_csr, pmpaddr);
|
|
|
|
csr_write_num(pmpcfg_csr, pmpcfg);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-04-11 08:41:52 +08:00
|
|
|
int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out,
|
2020-09-07 18:20:33 +08:00
|
|
|
unsigned long *log2len)
|
2018-12-11 21:54:06 +08:00
|
|
|
{
|
|
|
|
int pmpcfg_csr, pmpcfg_shift, pmpaddr_csr;
|
|
|
|
unsigned long cfgmask, pmpcfg, prot;
|
2020-09-07 18:20:33 +08:00
|
|
|
unsigned long t1, addr, len;
|
2018-12-11 21:54:06 +08:00
|
|
|
|
|
|
|
/* check parameters */
|
2020-09-07 18:20:33 +08:00
|
|
|
if (n >= PMP_COUNT || !prot_out || !addr_out || !log2len)
|
2018-12-11 21:54:06 +08:00
|
|
|
return SBI_EINVAL;
|
2020-09-07 18:20:33 +08:00
|
|
|
*prot_out = *addr_out = *log2len = 0;
|
2018-12-11 21:54:06 +08:00
|
|
|
|
|
|
|
/* calculate PMP register and offset */
|
|
|
|
#if __riscv_xlen == 32
|
2019-04-11 08:41:52 +08:00
|
|
|
pmpcfg_csr = CSR_PMPCFG0 + (n >> 2);
|
2018-12-11 21:54:06 +08:00
|
|
|
pmpcfg_shift = (n & 3) << 3;
|
|
|
|
#elif __riscv_xlen == 64
|
2019-04-11 08:41:52 +08:00
|
|
|
pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1;
|
2018-12-11 21:54:06 +08:00
|
|
|
pmpcfg_shift = (n & 7) << 3;
|
|
|
|
#else
|
2022-03-16 00:22:38 +08:00
|
|
|
# error "Unexpected __riscv_xlen"
|
2018-12-11 21:54:06 +08:00
|
|
|
#endif
|
|
|
|
pmpaddr_csr = CSR_PMPADDR0 + n;
|
|
|
|
|
|
|
|
/* decode PMP config */
|
2020-06-19 11:55:19 +08:00
|
|
|
cfgmask = (0xffUL << pmpcfg_shift);
|
2019-04-11 08:41:52 +08:00
|
|
|
pmpcfg = csr_read_num(pmpcfg_csr) & cfgmask;
|
|
|
|
prot = pmpcfg >> pmpcfg_shift;
|
2018-12-11 21:54:06 +08:00
|
|
|
|
|
|
|
/* decode PMP address */
|
|
|
|
if ((prot & PMP_A) == PMP_A_NAPOT) {
|
|
|
|
addr = csr_read_num(pmpaddr_csr);
|
|
|
|
if (addr == -1UL) {
|
2019-04-11 08:41:52 +08:00
|
|
|
addr = 0;
|
2020-09-07 18:20:33 +08:00
|
|
|
len = __riscv_xlen;
|
2018-12-11 21:54:06 +08:00
|
|
|
} else {
|
2020-02-18 11:56:33 +08:00
|
|
|
t1 = ctz(~addr);
|
2019-04-11 08:41:52 +08:00
|
|
|
addr = (addr & ~((1UL << t1) - 1)) << PMP_SHIFT;
|
2020-09-07 18:20:33 +08:00
|
|
|
len = (t1 + PMP_SHIFT + 1);
|
2018-12-11 21:54:06 +08:00
|
|
|
}
|
|
|
|
} else {
|
2019-04-11 08:41:52 +08:00
|
|
|
addr = csr_read_num(pmpaddr_csr) << PMP_SHIFT;
|
2020-09-07 18:20:33 +08:00
|
|
|
len = PMP_SHIFT;
|
2018-12-11 21:54:06 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* return details */
|
2019-04-11 08:41:52 +08:00
|
|
|
*prot_out = prot;
|
|
|
|
*addr_out = addr;
|
2020-09-07 18:20:33 +08:00
|
|
|
*log2len = len;
|
2018-12-11 21:54:06 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|