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refactor: remove not needed code

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Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
This commit is contained in:
Mateusz Jablonski
2024-05-21 15:20:58 +00:00
committed by Compute-Runtime-Automation
parent dafaaf5f7d
commit 2577f1123e
18 changed files with 75 additions and 139 deletions
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18
opencl/test/unit_test/offline_compiler/xe_hpg_core/dg2/offline_compiler_tests_dg2.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2022-2023 Intel Corporation
* Copyright (C) 2022-2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -8,19 +8,27 @@
#include "shared/source/helpers/constants.h"
#include "shared/source/xe_hpg_core/hw_cmds_dg2.h"
#include "shared/test/common/test_macros/header/per_product_test_definitions.h"
#include "shared/test/common/xe_hpg_core/dg2/product_configs_dg2.h"
#include "opencl/test/unit_test/offline_compiler/ocloc_fatbinary_tests.h"
#include "opencl/test/unit_test/offline_compiler/ocloc_product_config_tests.h"
#include "device_ids_configs_dg2.h"
#include "platforms.h"
namespace NEO {
inline constexpr AOT::PRODUCT_CONFIG productConfigs[] = {
AOT::DG2_G10_A0,
AOT::DG2_G10_A1,
AOT::DG2_G10_B0,
AOT::DG2_G10_C0,
AOT::DG2_G11_A0,
AOT::DG2_G11_B0,
AOT::DG2_G11_B1,
AOT::DG2_G12_A0};
INSTANTIATE_TEST_CASE_P(
OclocProductConfigDg2TestsValues,
OclocProductConfigTests,
::testing::Combine(
::testing::ValuesIn(AOT_DG2::productConfigs),
::testing::ValuesIn(productConfigs),
::testing::Values(IGFX_DG2)));
INSTANTIATE_TEST_CASE_P(

2
shared/offline_compiler/source/CMakeLists.txt
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@@ -81,7 +81,7 @@ set(CLOC_LIB_SRCS_LIB
${NEO_SHARED_DIRECTORY}/release_helper/release_helper_1270.cpp
${NEO_SHARED_DIRECTORY}/release_helper/release_helper_1271.cpp
${NEO_SHARED_DIRECTORY}/release_helper/release_helper_1274.cpp
${NEO_SHARED_DIRECTORY}/release_helper${BRANCH_DIR_SUFFIX}enable_release_helper_xe.cpp
${NEO_SHARED_DIRECTORY}/release_helper/enable_release_helper_xe.cpp
${NEO_SHARED_DIRECTORY}/release_helper/release_helper_common_xe_lpg.inl
${NEO_SHARED_DIRECTORY}/release_helper/definitions${BRANCH_DIR_SUFFIX}release_definitions.h
${NEO_SHARED_DIRECTORY}/sku_info/definitions${BRANCH_DIR_SUFFIX}sku_info.cpp

5
shared/source/helpers/definitions/device_ids_configs_base.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2022-2023 Intel Corporation
* Copyright (C) 2022-2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -8,9 +8,6 @@
#pragma once
#ifdef SUPPORT_XE_HPG_CORE
#ifdef SUPPORT_DG2
#include "device_ids_configs_dg2.h"
#endif
#ifdef SUPPORT_MTL
#include "shared/source/xe_hpg_core/xe_lpg/device_ids_configs_xe_lpg.h"
#endif

4
shared/source/release_helper/CMakeLists.txt
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@@ -1,5 +1,5 @@
#
# Copyright (C) 2023 Intel Corporation
# Copyright (C) 2023-2024 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
@@ -26,7 +26,7 @@ if(SUPPORT_XE_HPG_CORE OR SUPPORT_XE_HPC_CORE)
${CMAKE_CURRENT_SOURCE_DIR}/release_helper_1271.cpp
${CMAKE_CURRENT_SOURCE_DIR}/release_helper_1274.cpp
)
set_property(GLOBAL APPEND PROPERTY NEO_CORE_SRCS_LINK ${CMAKE_CURRENT_SOURCE_DIR}${BRANCH_DIR_SUFFIX}enable_release_helper_xe.cpp)
set_property(GLOBAL APPEND PROPERTY NEO_CORE_SRCS_LINK ${CMAKE_CURRENT_SOURCE_DIR}/enable_release_helper_xe.cpp)
endif()
set_property(GLOBAL APPEND PROPERTY NEO_CORE_RELEASE_HELPER ${NEO_CORE_RELEASE_HELPER})

38
shared/source/xe_hpg_core/definitions/compiler_product_helper_dg2.inl
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@@ -1,38 +0,0 @@
/*
* Copyright (C) 2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/xe_hpg_core/definitions/compiler_product_helper_dg2_base.inl"
namespace NEO {
template <>
uint32_t CompilerProductHelperHw<IGFX_DG2>::getProductConfigFromHwInfo(const HardwareInfo &hwInfo) const {
if (DG2::isG10(hwInfo)) {
switch (hwInfo.platform.usRevId) {
case 0x0:
return AOT::DG2_G10_A0;
case 0x1:
return AOT::DG2_G10_A1;
case 0x4:
return AOT::DG2_G10_B0;
case 0x8:
return AOT::DG2_G10_C0;
}
} else if (DG2::isG11(hwInfo)) {
switch (hwInfo.platform.usRevId) {
case 0x0:
return AOT::DG2_G11_A0;
case 0x4:
return AOT::DG2_G11_B0;
case 0x5:
return AOT::DG2_G11_B1;
}
} else if (DG2::isG12(hwInfo)) {
return AOT::DG2_G12_A0;
}
return getDefaultHwIpVersion();
}
} // namespace NEO

32
shared/source/xe_hpg_core/definitions/compiler_product_helper_dg2_base.inl
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@@ -1,32 +0,0 @@
/*
* Copyright (C) 2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/xe_hpg_core/hw_cmds_dg2.h"
#include "platforms.h"
namespace NEO {
template <>
uint64_t CompilerProductHelperHw<IGFX_DG2>::getHwInfoConfig(const HardwareInfo &hwInfo) const {
if (DG2::isG10(hwInfo)) {
return 0x800040010;
}
return 0x200040010;
}
template <>
uint32_t CompilerProductHelperHw<IGFX_DG2>::getDefaultHwIpVersion() const {
return AOT::DG2_G10_A0;
}
template <>
uint32_t CompilerProductHelperHw<IGFX_DG2>::matchRevisionIdWithProductConfig(HardwareIpVersion ipVersion, uint32_t revisionID) const {
HardwareIpVersion dg2Config = ipVersion;
dg2Config.revision = revisionID;
return dg2Config.value;
}
} // namespace NEO

8
shared/source/xe_hpg_core/definitions/hw_info_setup_dg2.inl
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@@ -1,8 +0,0 @@
/*
* Copyright (C) 2021-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
void DG2::adjustHardwareInfo(HardwareInfo *hwInfo) {}

10
shared/source/xe_hpg_core/dg2/definitions/device_ids_configs_dg2.h
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@@ -1,10 +0,0 @@
/*
* Copyright (C) 2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "shared/source/xe_hpg_core/dg2/definitions/device_ids_configs_dg2_base.h"

0
shared/source/xe_hpg_core/dg2/definitions/device_ids_configs_dg2_base.h → shared/source/xe_hpg_core/dg2/device_ids_configs_dg2.h
View File

52
shared/source/xe_hpg_core/enable_compiler_product_helper_dg2.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2022-2023 Intel Corporation
* Copyright (C) 2022-2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -13,9 +13,57 @@
#include "shared/source/helpers/compiler_product_helper_enable_subgroup_local_block_io.inl"
#include "shared/source/helpers/compiler_product_helper_tgllp_and_later.inl"
#include "shared/source/helpers/compiler_product_helper_xe_hp_and_later.inl"
#include "shared/source/xe_hpg_core/hw_cmds_dg2.h"
#include "compiler_product_helper_dg2.inl"
#include "platforms.h"
namespace NEO {
template <>
uint64_t CompilerProductHelperHw<IGFX_DG2>::getHwInfoConfig(const HardwareInfo &hwInfo) const {
if (DG2::isG10(hwInfo)) {
return 0x800040010;
}
return 0x200040010;
}
template <>
uint32_t CompilerProductHelperHw<IGFX_DG2>::getDefaultHwIpVersion() const {
return AOT::DG2_G10_A0;
}
template <>
uint32_t CompilerProductHelperHw<IGFX_DG2>::matchRevisionIdWithProductConfig(HardwareIpVersion ipVersion, uint32_t revisionID) const {
HardwareIpVersion dg2Config = ipVersion;
dg2Config.revision = revisionID;
return dg2Config.value;
}
template <>
uint32_t CompilerProductHelperHw<IGFX_DG2>::getProductConfigFromHwInfo(const HardwareInfo &hwInfo) const {
if (DG2::isG10(hwInfo)) {
switch (hwInfo.platform.usRevId) {
case 0x0:
return AOT::DG2_G10_A0;
case 0x1:
return AOT::DG2_G10_A1;
case 0x4:
return AOT::DG2_G10_B0;
case 0x8:
return AOT::DG2_G10_C0;
}
} else if (DG2::isG11(hwInfo)) {
switch (hwInfo.platform.usRevId) {
case 0x0:
return AOT::DG2_G11_A0;
case 0x4:
return AOT::DG2_G11_B0;
case 0x5:
return AOT::DG2_G11_B1;
}
} else if (DG2::isG12(hwInfo)) {
return AOT::DG2_G12_A0;
}
return getDefaultHwIpVersion();
}
static EnableCompilerProductHelper<IGFX_DG2> enableCompilerProductHelperDG2;
} // namespace NEO

5
shared/source/xe_hpg_core/hw_cmds_dg2.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021-2023 Intel Corporation
* Copyright (C) 2021-2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -7,7 +7,7 @@
#pragma once
#include "shared/source/helpers/hw_info.h"
#include "shared/source/xe_hpg_core/dg2/definitions/device_ids_configs_dg2_base.h"
#include "shared/source/xe_hpg_core/dg2/device_ids_configs_dg2.h"
#include "shared/source/xe_hpg_core/hw_cmds_xe_hpg_core_base.h"
#include <algorithm>
@@ -33,7 +33,6 @@ struct DG2 : public XeHpgCoreFamily {
static const RuntimeCapabilityTable capabilityTable;
static void (*setupHardwareInfo)(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, uint64_t hwInfoConfig, const ReleaseHelper *releaseHelper);
static void setupFeatureAndWorkaroundTable(HardwareInfo *hwInfo);
static void adjustHardwareInfo(HardwareInfo *hwInfo);
static void setupHardwareInfoBase(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, const ReleaseHelper *releaseHelper);
static bool isG10(const HardwareInfo &hwInfo) {

6
shared/source/xe_hpg_core/hw_info_dg2.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021-2023 Intel Corporation
* Copyright (C) 2021-2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -13,7 +13,6 @@
#include "shared/source/xe_hpg_core/hw_cmds_dg2.h"
#include "aubstream/engine_node.h"
#include "device_ids_configs_dg2.h"
namespace NEO {
@@ -139,7 +138,6 @@ void DG2::setupHardwareInfoBase(HardwareInfo *hwInfo, bool setupFeatureTableAndW
gtSysInfo->IsL3HashModeEnabled = false;
gtSysInfo->IsDynamicallyPopulated = false;
adjustHardwareInfo(hwInfo);
if (setupFeatureTableAndWorkaroundTable) {
setupFeatureAndWorkaroundTable(hwInfo);
}
@@ -181,7 +179,6 @@ void Dg2HwConfig::setupHardwareInfo(HardwareInfo *hwInfo, bool setupFeatureTable
gtSysInfo->SliceInfo[slice].Enabled = true;
}
adjustHardwareInfo(hwInfo);
if (setupFeatureTableAndWorkaroundTable) {
DG2::setupFeatureAndWorkaroundTable(hwInfo);
}
@@ -195,5 +192,4 @@ void setupDG2HardwareInfoImpl(HardwareInfo *hwInfo, bool setupFeatureTableAndWor
}
void (*DG2::setupHardwareInfo)(HardwareInfo *, bool, uint64_t, const ReleaseHelper *) = setupDG2HardwareInfoImpl;
#include "hw_info_setup_dg2.inl"
} // namespace NEO

1
shared/source/xe_hpg_core/linux/product_helper_dg2.cpp
View File

@@ -30,7 +30,6 @@ int ProductHelperHw<gfxProduct>::configureHardwareCustom(HardwareInfo *hwInfo, O
enableCompression(hwInfo);
}
DG2::adjustHardwareInfo(hwInfo);
enableBlitterOperationsSupport(hwInfo);
hwInfo->workaroundTable.flags.wa_15010089951 = true;

1
shared/source/xe_hpg_core/windows/product_helper_dg2.cpp
View File

@@ -31,7 +31,6 @@ int ProductHelperHw<gfxProduct>::configureHardwareCustom(HardwareInfo *hwInfo, O
if (allowCompression(*hwInfo)) {
enableCompression(hwInfo);
}
DG2::adjustHardwareInfo(hwInfo);
enableBlitterOperationsSupport(hwInfo);
hwInfo->workaroundTable.flags.wa_15010089951 = true;

2
shared/test/common/libult/CMakeLists.txt
View File

@@ -140,7 +140,7 @@ endif()
if(TESTS_XE_HPG_CORE OR TESTS_XE_HPC_CORE)
list(APPEND neo_libult_common_SRCS_LIB_ULT
${NEO_SHARED_TEST_DIRECTORY}/common/helpers/unit_test_helper_xe_hpg_and_xe_hpc.inl
${NEO_SHARED_DIRECTORY}/release_helper${BRANCH_DIR_SUFFIX}enable_release_helper_xe.cpp
${NEO_SHARED_DIRECTORY}/release_helper/enable_release_helper_xe.cpp
)
endif()

5
shared/test/common/xe_hpg_core/dg2/CMakeLists.txt
View File

@@ -1,5 +1,5 @@
#
# Copyright (C) 2021-2022 Intel Corporation
# Copyright (C) 2021-2024 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
@@ -7,9 +7,8 @@
if(TESTS_DG2)
target_sources(neo_libult_common PRIVATE
${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
${CMAKE_CURRENT_SOURCE_DIR}/product_configs_dg2.h
${CMAKE_CURRENT_SOURCE_DIR}/test_traits_dg2.h
)
add_subdirectories()
endif()
endif()

20
shared/test/common/xe_hpg_core/dg2/product_configs_dg2.h
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@@ -1,20 +0,0 @@
/*
* Copyright (C) 2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "platforms.h"
namespace AOT_DG2 {
inline constexpr AOT::PRODUCT_CONFIG productConfigs[] = {
AOT::DG2_G10_A0,
AOT::DG2_G10_A1,
AOT::DG2_G10_B0,
AOT::DG2_G10_C0,
AOT::DG2_G11_A0,
AOT::DG2_G11_B0,
AOT::DG2_G11_B1};
}

5
shared/test/unit_test/xe_hpg_core/dg2/device_factory_tests_dg2.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2023 Intel Corporation
* Copyright (C) 2023-2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -12,9 +12,8 @@
#include "shared/test/common/mocks/mock_execution_environment.h"
#include "shared/test/common/test_macros/header/per_product_test_definitions.h"
#include "shared/test/common/test_macros/test.h"
#include "shared/test/common/xe_hpg_core/dg2/product_configs_dg2.h"
#include "device_ids_configs_dg2.h"
#include "platforms.h"
using namespace NEO;