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https://github.com/intel/compute-runtime.git
synced 2026-01-01 04:23:00 +08:00
AUB patch to move physical addresses to a lower region
Ensured canonical addresses not to go beyond acceptable physical addresses. Change-Id: I4af3b7bd3d43ee86aabfdbddd0a21bc937986d43
This commit is contained in:
@@ -53,18 +53,18 @@ const uint64_t PageTableTraits<48>::physicalMemory = 0; // 1ull <<addressingBits
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const uint64_t PageTableTraits<48>::numPTEntries = BIT(PageTableTraits<48>::addressingBits - PageTableTraits<48>::NUM_OFFSET_BITS);
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const uint64_t PageTableTraits<48>::sizePT = BIT(PageTableTraits<48>::addressingBits - PageTableTraits<48>::NUM_OFFSET_BITS) * sizeof(uint64_t);
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const uint64_t PageTableTraits<48>::ptBaseAddress = BIT(38);
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const uint64_t PageTableTraits<48>::ptBaseAddress = BIT(37);
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const uint64_t PageTableTraits<48>::numPDEntries = BIT(PageTableTraits<48>::addressingBits - PageTableTraits<48>::NUM_OFFSET_BITS - PageTableTraits<48>::NUM_PTE_BITS);
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const uint64_t PageTableTraits<48>::sizePD = BIT(PageTableTraits<48>::addressingBits - PageTableTraits<48>::NUM_OFFSET_BITS - PageTableTraits<48>::NUM_PTE_BITS) * sizeof(uint64_t);
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const uint64_t PageTableTraits<48>::pdBaseAddress = BIT(37);
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const uint64_t PageTableTraits<48>::pdBaseAddress = BIT(36);
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const uint64_t PageTableTraits<48>::numPDPEntries = BIT(PageTableTraits<48>::addressingBits - PageTableTraits<48>::NUM_OFFSET_BITS - PageTableTraits<48>::NUM_PTE_BITS - PageTableTraits<48>::NUM_PDE_BITS);
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const uint64_t PageTableTraits<48>::sizePDP = BIT(PageTableTraits<48>::addressingBits - PageTableTraits<48>::NUM_OFFSET_BITS - PageTableTraits<48>::NUM_PTE_BITS - PageTableTraits<48>::NUM_PDE_BITS) * sizeof(uint64_t);
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const uint64_t PageTableTraits<48>::pdpBaseAddress = BIT(36);
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const uint64_t PageTableTraits<48>::pdpBaseAddress = BIT(35);
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const uint64_t PageTableTraits<48>::numPML4Entries = BIT(NUM_PML4_BITS);
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const uint64_t PageTableTraits<48>::sizePML4 = BIT(NUM_PML4_BITS) * sizeof(uint64_t);
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const uint64_t PageTableTraits<48>::pml4BaseAddress = BIT(35);
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const uint64_t PageTableTraits<48>::pml4BaseAddress = BIT(34);
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// clang-format on
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void LrcaHelper::setRingTail(void *pLRCIn, uint32_t ringTail) const {
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@@ -29,8 +29,12 @@ using OCLRT::AUBCommandStreamReceiver;
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using OCLRT::AUBCommandStreamReceiverHw;
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using OCLRT::EngineType;
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namespace Os {
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extern const char *fileSeparator;
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std::string getAubFileName(const OCLRT::Device *pDevice, const std::string baseName) {
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const auto pGtSystemInfo = pDevice->getHardwareInfo().pSysInfo;
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std::stringstream strfilename;
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strfilename << pDevice->getProductAbbrev() << "_" << pGtSystemInfo->SliceCount << "x" << pGtSystemInfo->SubSliceCount << "x" << pGtSystemInfo->MaxEuPerSubSlice << "_" << baseName;
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return strfilename.str();
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}
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typedef Test<DeviceFixture> AubMemDumpTests;
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@@ -33,13 +33,7 @@ namespace Os {
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extern const char *fileSeparator;
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}
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static std::string getAubFileName(const OCLRT::Device *pDevice, const std::string baseName) {
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const auto pGtSystemInfo = pDevice->getHardwareInfo().pSysInfo;
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std::stringstream strfilename;
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strfilename << pDevice->getProductAbbrev() << "_" << pGtSystemInfo->SliceCount << "x" << pGtSystemInfo->SubSliceCount << "x" << pGtSystemInfo->MaxEuPerSubSlice << "_" << baseName;
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return strfilename.str();
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}
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extern std::string getAubFileName(const OCLRT::Device *pDevice, const std::string baseName);
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template <typename FamilyType>
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void setupAUB(const OCLRT::Device *pDevice, OCLRT::EngineType engineType) {
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@@ -23,6 +23,7 @@ cmake_minimum_required(VERSION 3.2.0 FATAL_ERROR)
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project(igdrcl_aub_tests)
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if(TESTS_GEN9)
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add_subdirectory(batch_buffer)
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add_subdirectory(execution_model)
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add_subdirectory(skl)
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endif(TESTS_GEN9)
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25
unit_tests/aub_tests/gen9/batch_buffer/CMakeLists.txt
Normal file
25
unit_tests/aub_tests/gen9/batch_buffer/CMakeLists.txt
Normal file
@@ -0,0 +1,25 @@
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# Copyright (c) 2018, Intel Corporation
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#
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# Permission is hereby granted, free of charge, to any person obtaining a
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# copy of this software and associated documentation files (the "Software"),
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# to deal in the Software without restriction, including without limitation
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# the rights to use, copy, modify, merge, publish, distribute, sublicense,
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# and/or sell copies of the Software, and to permit persons to whom the
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# Software is furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included
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# in all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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# OTHER DEALINGS IN THE SOFTWARE.
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target_sources(igdrcl_aub_tests PUBLIC
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${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
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${CMAKE_CURRENT_SOURCE_DIR}/aub_batch_buffer_tests.h
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${CMAKE_CURRENT_SOURCE_DIR}/aub_batch_buffer_tests.cpp
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)
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@@ -0,0 +1,32 @@
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/*
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* Copyright (c) 2018, Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "aub_batch_buffer_tests.h"
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#include "unit_tests/fixtures/device_fixture.h"
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typedef Test<DeviceFixture> AubBatchBufferTests;
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static constexpr auto gpuBatchBufferAddr = 0x800400001000ull; // 48-bit GPU address
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GEN9TEST_F(AubBatchBufferTests, givenSimpleRCSWithBatchBufferWhenItHasMSBSetInGpuAddressThenAUBShouldBeSetupSuccessfully) {
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setupAUBWithBatchBuffer<FamilyType>(pDevice, OCLRT::EngineType::ENGINE_RCS, gpuBatchBufferAddr);
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}
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168
unit_tests/aub_tests/gen9/batch_buffer/aub_batch_buffer_tests.h
Normal file
168
unit_tests/aub_tests/gen9/batch_buffer/aub_batch_buffer_tests.h
Normal file
@@ -0,0 +1,168 @@
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/*
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* Copyright (c) 2018, Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#pragma once
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#include "unit_tests/aub_tests/command_stream/aub_mem_dump_tests.h"
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template <typename FamilyType>
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void setupAUBWithBatchBuffer(const OCLRT::Device *pDevice, OCLRT::EngineType engineType, uint64_t gpuBatchBufferAddr) {
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typedef typename OCLRT::AUBFamilyMapper<FamilyType>::AUB AUB;
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const auto &csTraits = OCLRT::AUBCommandStreamReceiverHw<FamilyType>::getCsTraits(engineType);
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auto mmioBase = csTraits.mmioBase;
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uint64_t physAddress = 0x10000;
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OCLRT::AUBCommandStreamReceiver::AubFileStream aubFile;
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std::string filePath(OCLRT::folderAUB);
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filePath.append(Os::fileSeparator);
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std::string baseName("simple");
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baseName.append(csTraits.name);
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baseName.append("WithBatchBuffer");
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baseName.append(".aub");
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filePath.append(getAubFileName(pDevice, baseName));
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aubFile.fileHandle.open(filePath.c_str(), std::ofstream::binary);
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// Header
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aubFile.init(AubMemDump::SteppingValues::A, AUB::Traits::device);
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aubFile.writeMMIO(mmioBase + 0x229c, 0xffff8280);
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const size_t sizeHWSP = 0x1000;
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const size_t alignHWSP = 0x1000;
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auto pGlobalHWStatusPage = alignedMalloc(sizeHWSP, alignHWSP);
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uint32_t ggttGlobalHardwareStatusPage = (uint32_t)((uintptr_t)pGlobalHWStatusPage);
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AUB::reserveAddressGGTT(aubFile, ggttGlobalHardwareStatusPage, sizeHWSP, physAddress);
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physAddress += sizeHWSP;
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aubFile.writeMMIO(mmioBase + 0x2080, ggttGlobalHardwareStatusPage);
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using MI_NOOP = typename FamilyType::MI_NOOP;
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using MI_BATCH_BUFFER_START = typename FamilyType::MI_BATCH_BUFFER_START;
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using MI_BATCH_BUFFER_END = typename FamilyType::MI_BATCH_BUFFER_END;
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// create a user mode batch buffer
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auto physBatchBuffer = physAddress;
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const auto sizeBatchBuffer = 0x1000;
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auto gpuBatchBuffer = static_cast<uintptr_t>(gpuBatchBufferAddr);
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physAddress += sizeBatchBuffer;
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AUB::reserveAddressPPGTT(aubFile, gpuBatchBuffer, sizeBatchBuffer, physBatchBuffer);
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uint8_t batchBuffer[sizeBatchBuffer];
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auto noop = MI_NOOP::sInit();
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uint32_t noopId = 0xbaadd;
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{
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auto pBatchBuffer = (void *)batchBuffer;
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*(MI_NOOP *)pBatchBuffer = noop;
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pBatchBuffer = ptrOffset(pBatchBuffer, sizeof(MI_NOOP));
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*(MI_NOOP *)pBatchBuffer = noop;
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pBatchBuffer = ptrOffset(pBatchBuffer, sizeof(MI_NOOP));
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*(MI_NOOP *)pBatchBuffer = noop;
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pBatchBuffer = ptrOffset(pBatchBuffer, sizeof(MI_NOOP));
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noop.TheStructure.Common.IdentificationNumberRegisterWriteEnable = true;
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noop.TheStructure.Common.IdentificationNumber = noopId++;
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*(MI_NOOP *)pBatchBuffer = noop;
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pBatchBuffer = ptrOffset(pBatchBuffer, sizeof(MI_NOOP));
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*(MI_BATCH_BUFFER_END *)pBatchBuffer = MI_BATCH_BUFFER_END::sInit();
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pBatchBuffer = ptrOffset(pBatchBuffer, sizeof(MI_BATCH_BUFFER_END));
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auto sizeBufferUsed = ptrDiff(pBatchBuffer, batchBuffer);
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AUB::addMemoryWrite(aubFile, physBatchBuffer, batchBuffer, sizeBufferUsed, AubMemDump::AddressSpaceValues::TraceNonlocal, AubMemDump::DataTypeHintValues::TraceBatchBuffer);
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}
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const size_t sizeRing = 0x4 * 0x1000;
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const size_t alignRing = 0x1000;
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size_t sizeCommands = 0;
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auto pRing = alignedMalloc(sizeRing, alignRing);
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auto ggttRing = (uint32_t)(uintptr_t)pRing;
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auto physRing = physAddress;
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physAddress += sizeRing;
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auto rRing = AUB::reserveAddressGGTT(aubFile, ggttRing, sizeRing, physRing);
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ASSERT_NE(static_cast<uint64_t>(-1), rRing);
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EXPECT_EQ(rRing, physRing);
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auto cur = (uint32_t *)pRing;
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auto bbs = MI_BATCH_BUFFER_START::sInit();
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bbs.setBatchBufferStartAddressGraphicsaddress472(gpuBatchBuffer);
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bbs.setAddressSpaceIndicator(MI_BATCH_BUFFER_START::ADDRESS_SPACE_INDICATOR_PPGTT);
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*(MI_BATCH_BUFFER_START *)cur = bbs;
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cur = ptrOffset(cur, sizeof(MI_BATCH_BUFFER_START));
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noop.TheStructure.Common.IdentificationNumberRegisterWriteEnable = true;
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noop.TheStructure.Common.IdentificationNumber = noopId;
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*cur++ = noop.TheStructure.RawData[0];
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sizeCommands = ptrDiff(cur, pRing);
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AUB::addMemoryWrite(aubFile, physRing, pRing, sizeCommands, AubMemDump::AddressSpaceValues::TraceNonlocal, csTraits.aubHintCommandBuffer);
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auto sizeLRCA = csTraits.sizeLRCA;
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auto pLRCABase = alignedMalloc(csTraits.sizeLRCA, csTraits.alignLRCA);
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csTraits.initialize(pLRCABase);
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csTraits.setRingHead(pLRCABase, 0x0000);
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csTraits.setRingTail(pLRCABase, static_cast<uint32_t>(sizeCommands));
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csTraits.setRingBase(pLRCABase, ggttRing);
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auto ringCtrl = static_cast<uint32_t>((sizeRing - 0x1000) | 1);
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csTraits.setRingCtrl(pLRCABase, ringCtrl);
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auto ggttLRCA = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(pLRCABase));
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auto physLRCA = physAddress;
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physAddress += sizeLRCA;
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AUB::reserveAddressGGTT(aubFile, ggttLRCA, sizeLRCA, physLRCA);
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AUB::addMemoryWrite(aubFile, physLRCA, pLRCABase, sizeLRCA, AubMemDump::AddressSpaceValues::TraceNonlocal, csTraits.aubHintLRCA);
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typename AUB::MiContextDescriptorReg contextDescriptor = {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}};
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contextDescriptor.sData.Valid = true;
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contextDescriptor.sData.ForcePageDirRestore = false;
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contextDescriptor.sData.ForceRestore = false;
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contextDescriptor.sData.Legacy = true;
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contextDescriptor.sData.FaultSupport = 0;
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contextDescriptor.sData.PrivilegeAccessOrPPGTT = true;
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contextDescriptor.sData.ADor64bitSupport = AUB::Traits::addressingBits > 32;
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contextDescriptor.sData.LogicalRingCtxAddress = (uintptr_t)pLRCABase / 4096;
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contextDescriptor.sData.ContextID = 0;
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// Submit our exec-list
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aubFile.writeMMIO(mmioBase + 0x2230, 0);
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aubFile.writeMMIO(mmioBase + 0x2230, 0);
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aubFile.writeMMIO(mmioBase + 0x2230, contextDescriptor.ulData[1]);
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aubFile.writeMMIO(mmioBase + 0x2230, contextDescriptor.ulData[0]);
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// Poll until HW complete
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using AubMemDump::CmdServicesMemTraceRegisterPoll;
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aubFile.registerPoll(
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mmioBase + 0x2234, //EXECLIST_STATUS
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0x100,
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0x100,
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false,
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CmdServicesMemTraceRegisterPoll::TimeoutActionValues::Abort);
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alignedFree(pRing);
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alignedFree(pLRCABase);
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alignedFree(pGlobalHWStatusPage);
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aubFile.fileHandle.close();
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}
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