mirror of
https://github.com/intel/compute-runtime.git
synced 2025-12-18 13:54:58 +08:00
fix: unify hw configs for ADLP/ADLN/DG2
move them to common place Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
This commit is contained in:
committed by
Compute-Runtime-Automation
parent
be9d1f0589
commit
30734fa844
@@ -1,11 +1,11 @@
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#
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# Copyright (C) 2021 Intel Corporation
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# Copyright (C) 2021-2023 Intel Corporation
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#
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# SPDX-License-Identifier: MIT
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#
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set(IGDRCL_SRCS_linux_dll_tests_gen12_adlp
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${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
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${CMAKE_CURRENT_SOURCE_DIR}${BRANCH_DIR_SUFFIX}device_id_tests_adlp.cpp
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${CMAKE_CURRENT_SOURCE_DIR}/device_id_tests_adlp.cpp
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)
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target_sources(igdrcl_linux_dll_tests PRIVATE ${IGDRCL_SRCS_linux_dll_tests_gen12_adlp})
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@@ -1,9 +0,0 @@
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#
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# Copyright (C) 2021-2022 Intel Corporation
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#
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# SPDX-License-Identifier: MIT
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#
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if(UNIX)
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add_subdirectories()
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endif()
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@@ -1,11 +0,0 @@
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#
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# Copyright (C) 2021 Intel Corporation
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#
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# SPDX-License-Identifier: MIT
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#
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set(IGDRCL_SRCS_linux_dll_tests_xe_hpg_core_dg2
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${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
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${CMAKE_CURRENT_SOURCE_DIR}/${BRANCH_DIR_SUFFIX}/device_id_tests_dg2.cpp
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)
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target_sources(igdrcl_linux_dll_tests PRIVATE ${IGDRCL_SRCS_linux_dll_tests_xe_hpg_core_dg2})
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@@ -1,47 +0,0 @@
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/*
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* Copyright (C) 2021-2022 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#include "shared/test/common/fixtures/linux/device_id_fixture.h"
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using namespace NEO;
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TEST_F(DeviceIdTests, GivenDg2SupportedDeviceIdThenDeviceDescriptorTableExists) {
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std::array<DeviceDescriptor, 30> expectedDescriptors = {{
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{0x4F80, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x4F81, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x4F82, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x4F83, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x4F84, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x4F85, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x4F86, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x4F87, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x4F88, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x5690, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x5691, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x5692, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x5693, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x5694, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x5695, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x5696, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x5697, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x56A3, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x56A4, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x56B0, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x56B1, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x56B2, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x56B3, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x56A0, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x56A1, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x56A2, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x56A5, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x56A6, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x56C0, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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{0x56C1, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
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}};
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testImpl(expectedDescriptors);
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}
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@@ -27,66 +27,4 @@ DEVICE(0x7DD5, MtlHwConfig)
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DEVICE(0x7D45, MtlHwConfig)
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DEVICE(0x7D60, MtlHwConfig)
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#endif
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#ifdef SUPPORT_DG2
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DEVICE(0x4F80, Dg2HwConfig)
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DEVICE(0x4F81, Dg2HwConfig)
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DEVICE(0x4F82, Dg2HwConfig)
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DEVICE(0x4F83, Dg2HwConfig)
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DEVICE(0x4F84, Dg2HwConfig)
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DEVICE(0x4F85, Dg2HwConfig)
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DEVICE(0x4F86, Dg2HwConfig)
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DEVICE(0x4F87, Dg2HwConfig)
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DEVICE(0x4F88, Dg2HwConfig)
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NAMEDDEVICE(0x5690, Dg2HwConfig, "Intel(R) Arc(TM) A770M Graphics")
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NAMEDDEVICE(0x5691, Dg2HwConfig, "Intel(R) Arc(TM) A730M Graphics")
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NAMEDDEVICE(0x5692, Dg2HwConfig, "Intel(R) Arc(TM) A550M Graphics")
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NAMEDDEVICE(0x5693, Dg2HwConfig, "Intel(R) Arc(TM) A370M Graphics")
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NAMEDDEVICE(0x5694, Dg2HwConfig, "Intel(R) Arc(TM) A350M Graphics")
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DEVICE(0x5695, Dg2HwConfig)
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DEVICE(0x5696, Dg2HwConfig)
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DEVICE(0x5697, Dg2HwConfig)
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DEVICE(0x56A3, Dg2HwConfig)
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DEVICE(0x56A4, Dg2HwConfig)
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NAMEDDEVICE(0x56B0, Dg2HwConfig, "Intel(R) Arc(TM) Pro A30M Graphics")
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NAMEDDEVICE(0x56B1, Dg2HwConfig, "Intel(R) Arc(TM) Pro A40/A50 Graphics")
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DEVICE(0x56B2, Dg2HwConfig)
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DEVICE(0x56B3, Dg2HwConfig)
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NAMEDDEVICE(0x56A0, Dg2HwConfig, "Intel(R) Arc(TM) A770 Graphics")
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NAMEDDEVICE(0x56A1, Dg2HwConfig, "Intel(R) Arc(TM) A750 Graphics")
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NAMEDDEVICE(0x56A2, Dg2HwConfig, "Intel(R) Arc(TM) A580 Graphics")
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NAMEDDEVICE(0x56A5, Dg2HwConfig, "Intel(R) Arc(TM) A380 Graphics")
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NAMEDDEVICE(0x56A6, Dg2HwConfig, "Intel(R) Arc(TM) A310 Graphics")
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NAMEDDEVICE(0x56C0, Dg2HwConfig, "Intel(R) Data Center GPU Flex 170")
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NAMEDDEVICE(0x56C1, Dg2HwConfig, "Intel(R) Data Center GPU Flex 140")
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#endif
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#endif
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#ifdef SUPPORT_GEN12LP
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#ifdef SUPPORT_ADLP
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DEVICE(0x46A0, AdlpHwConfig)
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DEVICE(0x46B0, AdlpHwConfig)
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DEVICE(0x46A1, AdlpHwConfig)
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DEVICE(0x46A2, AdlpHwConfig)
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DEVICE(0x46A3, AdlpHwConfig)
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DEVICE(0x46A6, AdlpHwConfig)
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DEVICE(0x46A8, AdlpHwConfig)
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DEVICE(0x46AA, AdlpHwConfig)
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DEVICE(0x462A, AdlpHwConfig)
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DEVICE(0x4626, AdlpHwConfig)
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DEVICE(0x4628, AdlpHwConfig)
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DEVICE(0x46B1, AdlpHwConfig)
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DEVICE(0x46B2, AdlpHwConfig)
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DEVICE(0x46B3, AdlpHwConfig)
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DEVICE(0x46C0, AdlpHwConfig)
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DEVICE(0x46C1, AdlpHwConfig)
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DEVICE(0x46C2, AdlpHwConfig)
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DEVICE(0x46C3, AdlpHwConfig)
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// RPL-P
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DEVICE(0xA7A0, AdlpHwConfig)
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DEVICE(0xA720, AdlpHwConfig)
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DEVICE(0xA7A8, AdlpHwConfig)
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DEVICE(0xA7A1, AdlpHwConfig)
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DEVICE(0xA721, AdlpHwConfig)
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DEVICE(0xA7A9, AdlpHwConfig)
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#endif
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#endif
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@@ -5,6 +5,41 @@
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*
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*/
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#ifdef SUPPORT_XE_HPG_CORE
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#ifdef SUPPORT_DG2
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DEVICE(0x4F80, Dg2HwConfig)
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DEVICE(0x4F81, Dg2HwConfig)
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DEVICE(0x4F82, Dg2HwConfig)
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DEVICE(0x4F83, Dg2HwConfig)
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DEVICE(0x4F84, Dg2HwConfig)
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DEVICE(0x4F85, Dg2HwConfig)
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DEVICE(0x4F86, Dg2HwConfig)
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DEVICE(0x4F87, Dg2HwConfig)
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DEVICE(0x4F88, Dg2HwConfig)
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NAMEDDEVICE(0x5690, Dg2HwConfig, "Intel(R) Arc(TM) A770M Graphics")
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NAMEDDEVICE(0x5691, Dg2HwConfig, "Intel(R) Arc(TM) A730M Graphics")
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NAMEDDEVICE(0x5692, Dg2HwConfig, "Intel(R) Arc(TM) A550M Graphics")
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NAMEDDEVICE(0x5693, Dg2HwConfig, "Intel(R) Arc(TM) A370M Graphics")
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NAMEDDEVICE(0x5694, Dg2HwConfig, "Intel(R) Arc(TM) A350M Graphics")
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DEVICE(0x5695, Dg2HwConfig)
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DEVICE(0x5696, Dg2HwConfig)
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DEVICE(0x5697, Dg2HwConfig)
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DEVICE(0x56A3, Dg2HwConfig)
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DEVICE(0x56A4, Dg2HwConfig)
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NAMEDDEVICE(0x56B0, Dg2HwConfig, "Intel(R) Arc(TM) Pro A30M Graphics")
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NAMEDDEVICE(0x56B1, Dg2HwConfig, "Intel(R) Arc(TM) Pro A40/A50 Graphics")
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DEVICE(0x56B2, Dg2HwConfig)
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DEVICE(0x56B3, Dg2HwConfig)
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NAMEDDEVICE(0x56A0, Dg2HwConfig, "Intel(R) Arc(TM) A770 Graphics")
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NAMEDDEVICE(0x56A1, Dg2HwConfig, "Intel(R) Arc(TM) A750 Graphics")
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NAMEDDEVICE(0x56A2, Dg2HwConfig, "Intel(R) Arc(TM) A580 Graphics")
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NAMEDDEVICE(0x56A5, Dg2HwConfig, "Intel(R) Arc(TM) A380 Graphics")
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NAMEDDEVICE(0x56A6, Dg2HwConfig, "Intel(R) Arc(TM) A310 Graphics")
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NAMEDDEVICE(0x56C0, Dg2HwConfig, "Intel(R) Data Center GPU Flex 170")
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NAMEDDEVICE(0x56C1, Dg2HwConfig, "Intel(R) Data Center GPU Flex 140")
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#endif
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#endif
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#ifdef SUPPORT_XE_HP_CORE
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#ifdef SUPPORT_XE_HP_SDV
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DEVICE(0x0201, XehpSdvHwConfig)
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@@ -78,6 +113,33 @@ NAMEDDEVICE(0x46D1, AdlnHwConfig, "Intel(R) UHD Graphics")
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NAMEDDEVICE(0x46D2, AdlnHwConfig, "Intel(R) UHD Graphics")
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#endif
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#ifdef SUPPORT_ADLP
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DEVICE(0x46A0, AdlpHwConfig)
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DEVICE(0x46B0, AdlpHwConfig)
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DEVICE(0x46A1, AdlpHwConfig)
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DEVICE(0x46A2, AdlpHwConfig)
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DEVICE(0x46A3, AdlpHwConfig)
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DEVICE(0x46A6, AdlpHwConfig)
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DEVICE(0x46A8, AdlpHwConfig)
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DEVICE(0x46AA, AdlpHwConfig)
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DEVICE(0x462A, AdlpHwConfig)
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DEVICE(0x4626, AdlpHwConfig)
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DEVICE(0x4628, AdlpHwConfig)
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DEVICE(0x46B1, AdlpHwConfig)
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DEVICE(0x46B2, AdlpHwConfig)
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DEVICE(0x46B3, AdlpHwConfig)
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DEVICE(0x46C0, AdlpHwConfig)
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DEVICE(0x46C1, AdlpHwConfig)
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DEVICE(0x46C2, AdlpHwConfig)
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DEVICE(0x46C3, AdlpHwConfig)
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// RPL-P
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DEVICE(0xA7A0, AdlpHwConfig)
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DEVICE(0xA720, AdlpHwConfig)
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DEVICE(0xA7A8, AdlpHwConfig)
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DEVICE(0xA7A1, AdlpHwConfig)
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DEVICE(0xA721, AdlpHwConfig)
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DEVICE(0xA7A9, AdlpHwConfig)
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#endif
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#endif
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#ifdef SUPPORT_GEN11
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@@ -1,6 +0,0 @@
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/*
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* Copyright (C) 2022 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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@@ -1,6 +0,0 @@
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/*
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* Copyright (C) 2021 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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@@ -1,14 +0,0 @@
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/*
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* Copyright (C) 2022-2023 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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const HardwareInfo ADLN::hwInfo = AdlnHwConfig::hwInfo;
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void setupADLNHardwareInfoImpl(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, uint64_t hwInfoConfig, const CompilerProductHelper &compilerProductHelper) {
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AdlnHwConfig::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable, compilerProductHelper);
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}
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void (*ADLN::setupHardwareInfo)(HardwareInfo *, bool, uint64_t, const CompilerProductHelper &) = setupADLNHardwareInfoImpl;
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@@ -1,14 +0,0 @@
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/*
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* Copyright (C) 2021-2023 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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const HardwareInfo ADLP::hwInfo = AdlpHwConfig::hwInfo;
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void setupADLPHardwareInfoImpl(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, uint64_t hwInfoConfig, const CompilerProductHelper &compilerProductHelper) {
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AdlpHwConfig::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable, compilerProductHelper);
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}
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void (*ADLP::setupHardwareInfo)(HardwareInfo *, bool, uint64_t, const CompilerProductHelper &) = setupADLPHardwareInfoImpl;
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@@ -34,5 +34,4 @@ class AdlnHwConfig : public ADLN {
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static GT_SYSTEM_INFO gtSystemInfo;
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};
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#include "hw_cmds_adln.inl"
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} // namespace NEO
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@@ -39,5 +39,4 @@ class AdlpHwConfig : public ADLP {
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private:
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static GT_SYSTEM_INFO gtSystemInfo;
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};
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#include "hw_cmds_adlp.inl"
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} // namespace NEO
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@@ -151,5 +151,11 @@ void AdlnHwConfig::setupHardwareInfo(HardwareInfo *hwInfo, bool setupFeatureTabl
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gtSysInfo->CCSInfo.Instances.CCSEnableMask = 0b1;
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};
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#include "hw_info_setup_adln.inl"
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const HardwareInfo ADLN::hwInfo = AdlnHwConfig::hwInfo;
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void setupADLNHardwareInfoImpl(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, uint64_t hwInfoConfig, const CompilerProductHelper &compilerProductHelper) {
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AdlnHwConfig::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable, compilerProductHelper);
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}
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void (*ADLN::setupHardwareInfo)(HardwareInfo *, bool, uint64_t, const CompilerProductHelper &) = setupADLNHardwareInfoImpl;
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} // namespace NEO
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@@ -153,16 +153,22 @@ void AdlpHwConfig::setupHardwareInfo(HardwareInfo *hwInfo, bool setupFeatureTabl
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gtSysInfo->MaxSlicesSupported = ADLP::maxSlicesSupported;
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gtSysInfo->MaxSubSlicesSupported = ADLP::maxSubslicesSupported;
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gtSysInfo->L3CacheSizeInKb = 1;
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gtSysInfo->L3BankCount = 1;
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gtSysInfo->CCSInfo.IsValid = true;
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gtSysInfo->CCSInfo.NumberOfCCSEnabled = 1;
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}
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gtSysInfo->L3CacheSizeInKb = 1;
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if (setupFeatureTableAndWorkaroundTable) {
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setupFeatureAndWorkaroundTable(hwInfo);
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}
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};
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#include "hw_info_setup_adlp.inl"
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const HardwareInfo ADLP::hwInfo = AdlpHwConfig::hwInfo;
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void setupADLPHardwareInfoImpl(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, uint64_t hwInfoConfig, const CompilerProductHelper &compilerProductHelper) {
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AdlpHwConfig::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable, compilerProductHelper);
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}
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void (*ADLP::setupHardwareInfo)(HardwareInfo *, bool, uint64_t, const CompilerProductHelper &) = setupADLPHardwareInfoImpl;
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} // namespace NEO
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@@ -1,6 +0,0 @@
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/*
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* Copyright (C) 2021 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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@@ -5,13 +5,4 @@
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*
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*/
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const HardwareInfo DG2::hwInfo = Dg2HwConfig::hwInfo;
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void DG2::adjustHardwareInfo(HardwareInfo *hwInfo) {}
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void setupDG2HardwareInfoImpl(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, uint64_t hwInfoConfig, const CompilerProductHelper &compilerProductHelper) {
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DG2::setupHardwareInfoBase(hwInfo, setupFeatureTableAndWorkaroundTable, compilerProductHelper);
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Dg2HwConfig::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable, compilerProductHelper);
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}
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void (*DG2::setupHardwareInfo)(HardwareInfo *, bool, uint64_t, const CompilerProductHelper &) = setupDG2HardwareInfoImpl;
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@@ -61,6 +61,4 @@ class Dg2HwConfig : public DG2 {
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static GT_SYSTEM_INFO gtSystemInfo;
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};
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#include "hw_cmds_dg2.inl"
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} // namespace NEO
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||||
|
||||
@@ -186,5 +186,13 @@ void Dg2HwConfig::setupHardwareInfo(HardwareInfo *hwInfo, bool setupFeatureTable
|
||||
}
|
||||
};
|
||||
|
||||
const HardwareInfo DG2::hwInfo = Dg2HwConfig::hwInfo;
|
||||
|
||||
void setupDG2HardwareInfoImpl(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, uint64_t hwInfoConfig, const CompilerProductHelper &compilerProductHelper) {
|
||||
DG2::setupHardwareInfoBase(hwInfo, setupFeatureTableAndWorkaroundTable, compilerProductHelper);
|
||||
Dg2HwConfig::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable, compilerProductHelper);
|
||||
}
|
||||
|
||||
void (*DG2::setupHardwareInfo)(HardwareInfo *, bool, uint64_t, const CompilerProductHelper &) = setupDG2HardwareInfoImpl;
|
||||
#include "hw_info_setup_dg2.inl"
|
||||
} // namespace NEO
|
||||
|
||||
Reference in New Issue
Block a user