fix: unify hw configs for ADLP/ADLN/DG2

move them to common place

Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
This commit is contained in:
Mateusz Jablonski
2023-08-03 18:56:31 +00:00
committed by Compute-Runtime-Automation
parent be9d1f0589
commit 30734fa844
18 changed files with 87 additions and 193 deletions

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@@ -1,11 +1,11 @@
#
# Copyright (C) 2021 Intel Corporation
# Copyright (C) 2021-2023 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
set(IGDRCL_SRCS_linux_dll_tests_gen12_adlp
${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
${CMAKE_CURRENT_SOURCE_DIR}${BRANCH_DIR_SUFFIX}device_id_tests_adlp.cpp
${CMAKE_CURRENT_SOURCE_DIR}/device_id_tests_adlp.cpp
)
target_sources(igdrcl_linux_dll_tests PRIVATE ${IGDRCL_SRCS_linux_dll_tests_gen12_adlp})

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@@ -1,9 +0,0 @@
#
# Copyright (C) 2021-2022 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
if(UNIX)
add_subdirectories()
endif()

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@@ -1,11 +0,0 @@
#
# Copyright (C) 2021 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
set(IGDRCL_SRCS_linux_dll_tests_xe_hpg_core_dg2
${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
${CMAKE_CURRENT_SOURCE_DIR}/${BRANCH_DIR_SUFFIX}/device_id_tests_dg2.cpp
)
target_sources(igdrcl_linux_dll_tests PRIVATE ${IGDRCL_SRCS_linux_dll_tests_xe_hpg_core_dg2})

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@@ -1,47 +0,0 @@
/*
* Copyright (C) 2021-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/test/common/fixtures/linux/device_id_fixture.h"
using namespace NEO;
TEST_F(DeviceIdTests, GivenDg2SupportedDeviceIdThenDeviceDescriptorTableExists) {
std::array<DeviceDescriptor, 30> expectedDescriptors = {{
{0x4F80, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x4F81, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x4F82, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x4F83, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x4F84, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x4F85, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x4F86, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x4F87, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x4F88, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x5690, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x5691, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x5692, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x5693, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x5694, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x5695, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x5696, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x5697, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x56A3, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x56A4, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x56B0, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x56B1, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x56B2, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x56B3, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x56A0, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x56A1, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x56A2, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x56A5, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x56A6, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x56C0, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
{0x56C1, &Dg2HwConfig::hwInfo, &Dg2HwConfig::setupHardwareInfo},
}};
testImpl(expectedDescriptors);
}

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@@ -27,66 +27,4 @@ DEVICE(0x7DD5, MtlHwConfig)
DEVICE(0x7D45, MtlHwConfig)
DEVICE(0x7D60, MtlHwConfig)
#endif
#ifdef SUPPORT_DG2
DEVICE(0x4F80, Dg2HwConfig)
DEVICE(0x4F81, Dg2HwConfig)
DEVICE(0x4F82, Dg2HwConfig)
DEVICE(0x4F83, Dg2HwConfig)
DEVICE(0x4F84, Dg2HwConfig)
DEVICE(0x4F85, Dg2HwConfig)
DEVICE(0x4F86, Dg2HwConfig)
DEVICE(0x4F87, Dg2HwConfig)
DEVICE(0x4F88, Dg2HwConfig)
NAMEDDEVICE(0x5690, Dg2HwConfig, "Intel(R) Arc(TM) A770M Graphics")
NAMEDDEVICE(0x5691, Dg2HwConfig, "Intel(R) Arc(TM) A730M Graphics")
NAMEDDEVICE(0x5692, Dg2HwConfig, "Intel(R) Arc(TM) A550M Graphics")
NAMEDDEVICE(0x5693, Dg2HwConfig, "Intel(R) Arc(TM) A370M Graphics")
NAMEDDEVICE(0x5694, Dg2HwConfig, "Intel(R) Arc(TM) A350M Graphics")
DEVICE(0x5695, Dg2HwConfig)
DEVICE(0x5696, Dg2HwConfig)
DEVICE(0x5697, Dg2HwConfig)
DEVICE(0x56A3, Dg2HwConfig)
DEVICE(0x56A4, Dg2HwConfig)
NAMEDDEVICE(0x56B0, Dg2HwConfig, "Intel(R) Arc(TM) Pro A30M Graphics")
NAMEDDEVICE(0x56B1, Dg2HwConfig, "Intel(R) Arc(TM) Pro A40/A50 Graphics")
DEVICE(0x56B2, Dg2HwConfig)
DEVICE(0x56B3, Dg2HwConfig)
NAMEDDEVICE(0x56A0, Dg2HwConfig, "Intel(R) Arc(TM) A770 Graphics")
NAMEDDEVICE(0x56A1, Dg2HwConfig, "Intel(R) Arc(TM) A750 Graphics")
NAMEDDEVICE(0x56A2, Dg2HwConfig, "Intel(R) Arc(TM) A580 Graphics")
NAMEDDEVICE(0x56A5, Dg2HwConfig, "Intel(R) Arc(TM) A380 Graphics")
NAMEDDEVICE(0x56A6, Dg2HwConfig, "Intel(R) Arc(TM) A310 Graphics")
NAMEDDEVICE(0x56C0, Dg2HwConfig, "Intel(R) Data Center GPU Flex 170")
NAMEDDEVICE(0x56C1, Dg2HwConfig, "Intel(R) Data Center GPU Flex 140")
#endif
#endif
#ifdef SUPPORT_GEN12LP
#ifdef SUPPORT_ADLP
DEVICE(0x46A0, AdlpHwConfig)
DEVICE(0x46B0, AdlpHwConfig)
DEVICE(0x46A1, AdlpHwConfig)
DEVICE(0x46A2, AdlpHwConfig)
DEVICE(0x46A3, AdlpHwConfig)
DEVICE(0x46A6, AdlpHwConfig)
DEVICE(0x46A8, AdlpHwConfig)
DEVICE(0x46AA, AdlpHwConfig)
DEVICE(0x462A, AdlpHwConfig)
DEVICE(0x4626, AdlpHwConfig)
DEVICE(0x4628, AdlpHwConfig)
DEVICE(0x46B1, AdlpHwConfig)
DEVICE(0x46B2, AdlpHwConfig)
DEVICE(0x46B3, AdlpHwConfig)
DEVICE(0x46C0, AdlpHwConfig)
DEVICE(0x46C1, AdlpHwConfig)
DEVICE(0x46C2, AdlpHwConfig)
DEVICE(0x46C3, AdlpHwConfig)
// RPL-P
DEVICE(0xA7A0, AdlpHwConfig)
DEVICE(0xA720, AdlpHwConfig)
DEVICE(0xA7A8, AdlpHwConfig)
DEVICE(0xA7A1, AdlpHwConfig)
DEVICE(0xA721, AdlpHwConfig)
DEVICE(0xA7A9, AdlpHwConfig)
#endif
#endif

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@@ -5,6 +5,41 @@
*
*/
#ifdef SUPPORT_XE_HPG_CORE
#ifdef SUPPORT_DG2
DEVICE(0x4F80, Dg2HwConfig)
DEVICE(0x4F81, Dg2HwConfig)
DEVICE(0x4F82, Dg2HwConfig)
DEVICE(0x4F83, Dg2HwConfig)
DEVICE(0x4F84, Dg2HwConfig)
DEVICE(0x4F85, Dg2HwConfig)
DEVICE(0x4F86, Dg2HwConfig)
DEVICE(0x4F87, Dg2HwConfig)
DEVICE(0x4F88, Dg2HwConfig)
NAMEDDEVICE(0x5690, Dg2HwConfig, "Intel(R) Arc(TM) A770M Graphics")
NAMEDDEVICE(0x5691, Dg2HwConfig, "Intel(R) Arc(TM) A730M Graphics")
NAMEDDEVICE(0x5692, Dg2HwConfig, "Intel(R) Arc(TM) A550M Graphics")
NAMEDDEVICE(0x5693, Dg2HwConfig, "Intel(R) Arc(TM) A370M Graphics")
NAMEDDEVICE(0x5694, Dg2HwConfig, "Intel(R) Arc(TM) A350M Graphics")
DEVICE(0x5695, Dg2HwConfig)
DEVICE(0x5696, Dg2HwConfig)
DEVICE(0x5697, Dg2HwConfig)
DEVICE(0x56A3, Dg2HwConfig)
DEVICE(0x56A4, Dg2HwConfig)
NAMEDDEVICE(0x56B0, Dg2HwConfig, "Intel(R) Arc(TM) Pro A30M Graphics")
NAMEDDEVICE(0x56B1, Dg2HwConfig, "Intel(R) Arc(TM) Pro A40/A50 Graphics")
DEVICE(0x56B2, Dg2HwConfig)
DEVICE(0x56B3, Dg2HwConfig)
NAMEDDEVICE(0x56A0, Dg2HwConfig, "Intel(R) Arc(TM) A770 Graphics")
NAMEDDEVICE(0x56A1, Dg2HwConfig, "Intel(R) Arc(TM) A750 Graphics")
NAMEDDEVICE(0x56A2, Dg2HwConfig, "Intel(R) Arc(TM) A580 Graphics")
NAMEDDEVICE(0x56A5, Dg2HwConfig, "Intel(R) Arc(TM) A380 Graphics")
NAMEDDEVICE(0x56A6, Dg2HwConfig, "Intel(R) Arc(TM) A310 Graphics")
NAMEDDEVICE(0x56C0, Dg2HwConfig, "Intel(R) Data Center GPU Flex 170")
NAMEDDEVICE(0x56C1, Dg2HwConfig, "Intel(R) Data Center GPU Flex 140")
#endif
#endif
#ifdef SUPPORT_XE_HP_CORE
#ifdef SUPPORT_XE_HP_SDV
DEVICE(0x0201, XehpSdvHwConfig)
@@ -78,6 +113,33 @@ NAMEDDEVICE(0x46D1, AdlnHwConfig, "Intel(R) UHD Graphics")
NAMEDDEVICE(0x46D2, AdlnHwConfig, "Intel(R) UHD Graphics")
#endif
#ifdef SUPPORT_ADLP
DEVICE(0x46A0, AdlpHwConfig)
DEVICE(0x46B0, AdlpHwConfig)
DEVICE(0x46A1, AdlpHwConfig)
DEVICE(0x46A2, AdlpHwConfig)
DEVICE(0x46A3, AdlpHwConfig)
DEVICE(0x46A6, AdlpHwConfig)
DEVICE(0x46A8, AdlpHwConfig)
DEVICE(0x46AA, AdlpHwConfig)
DEVICE(0x462A, AdlpHwConfig)
DEVICE(0x4626, AdlpHwConfig)
DEVICE(0x4628, AdlpHwConfig)
DEVICE(0x46B1, AdlpHwConfig)
DEVICE(0x46B2, AdlpHwConfig)
DEVICE(0x46B3, AdlpHwConfig)
DEVICE(0x46C0, AdlpHwConfig)
DEVICE(0x46C1, AdlpHwConfig)
DEVICE(0x46C2, AdlpHwConfig)
DEVICE(0x46C3, AdlpHwConfig)
// RPL-P
DEVICE(0xA7A0, AdlpHwConfig)
DEVICE(0xA720, AdlpHwConfig)
DEVICE(0xA7A8, AdlpHwConfig)
DEVICE(0xA7A1, AdlpHwConfig)
DEVICE(0xA721, AdlpHwConfig)
DEVICE(0xA7A9, AdlpHwConfig)
#endif
#endif
#ifdef SUPPORT_GEN11

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@@ -1,6 +0,0 @@
/*
* Copyright (C) 2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/

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@@ -1,6 +0,0 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/

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@@ -1,14 +0,0 @@
/*
* Copyright (C) 2022-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
const HardwareInfo ADLN::hwInfo = AdlnHwConfig::hwInfo;
void setupADLNHardwareInfoImpl(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, uint64_t hwInfoConfig, const CompilerProductHelper &compilerProductHelper) {
AdlnHwConfig::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable, compilerProductHelper);
}
void (*ADLN::setupHardwareInfo)(HardwareInfo *, bool, uint64_t, const CompilerProductHelper &) = setupADLNHardwareInfoImpl;

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@@ -1,14 +0,0 @@
/*
* Copyright (C) 2021-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
const HardwareInfo ADLP::hwInfo = AdlpHwConfig::hwInfo;
void setupADLPHardwareInfoImpl(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, uint64_t hwInfoConfig, const CompilerProductHelper &compilerProductHelper) {
AdlpHwConfig::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable, compilerProductHelper);
}
void (*ADLP::setupHardwareInfo)(HardwareInfo *, bool, uint64_t, const CompilerProductHelper &) = setupADLPHardwareInfoImpl;

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@@ -34,5 +34,4 @@ class AdlnHwConfig : public ADLN {
static GT_SYSTEM_INFO gtSystemInfo;
};
#include "hw_cmds_adln.inl"
} // namespace NEO

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@@ -39,5 +39,4 @@ class AdlpHwConfig : public ADLP {
private:
static GT_SYSTEM_INFO gtSystemInfo;
};
#include "hw_cmds_adlp.inl"
} // namespace NEO

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@@ -151,5 +151,11 @@ void AdlnHwConfig::setupHardwareInfo(HardwareInfo *hwInfo, bool setupFeatureTabl
gtSysInfo->CCSInfo.Instances.CCSEnableMask = 0b1;
};
#include "hw_info_setup_adln.inl"
const HardwareInfo ADLN::hwInfo = AdlnHwConfig::hwInfo;
void setupADLNHardwareInfoImpl(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, uint64_t hwInfoConfig, const CompilerProductHelper &compilerProductHelper) {
AdlnHwConfig::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable, compilerProductHelper);
}
void (*ADLN::setupHardwareInfo)(HardwareInfo *, bool, uint64_t, const CompilerProductHelper &) = setupADLNHardwareInfoImpl;
} // namespace NEO

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@@ -153,16 +153,22 @@ void AdlpHwConfig::setupHardwareInfo(HardwareInfo *hwInfo, bool setupFeatureTabl
gtSysInfo->MaxSlicesSupported = ADLP::maxSlicesSupported;
gtSysInfo->MaxSubSlicesSupported = ADLP::maxSubslicesSupported;
gtSysInfo->L3CacheSizeInKb = 1;
gtSysInfo->L3BankCount = 1;
gtSysInfo->CCSInfo.IsValid = true;
gtSysInfo->CCSInfo.NumberOfCCSEnabled = 1;
}
gtSysInfo->L3CacheSizeInKb = 1;
if (setupFeatureTableAndWorkaroundTable) {
setupFeatureAndWorkaroundTable(hwInfo);
}
};
#include "hw_info_setup_adlp.inl"
const HardwareInfo ADLP::hwInfo = AdlpHwConfig::hwInfo;
void setupADLPHardwareInfoImpl(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, uint64_t hwInfoConfig, const CompilerProductHelper &compilerProductHelper) {
AdlpHwConfig::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable, compilerProductHelper);
}
void (*ADLP::setupHardwareInfo)(HardwareInfo *, bool, uint64_t, const CompilerProductHelper &) = setupADLPHardwareInfoImpl;
} // namespace NEO

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@@ -1,6 +0,0 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/

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@@ -5,13 +5,4 @@
*
*/
const HardwareInfo DG2::hwInfo = Dg2HwConfig::hwInfo;
void DG2::adjustHardwareInfo(HardwareInfo *hwInfo) {}
void setupDG2HardwareInfoImpl(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, uint64_t hwInfoConfig, const CompilerProductHelper &compilerProductHelper) {
DG2::setupHardwareInfoBase(hwInfo, setupFeatureTableAndWorkaroundTable, compilerProductHelper);
Dg2HwConfig::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable, compilerProductHelper);
}
void (*DG2::setupHardwareInfo)(HardwareInfo *, bool, uint64_t, const CompilerProductHelper &) = setupDG2HardwareInfoImpl;

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@@ -61,6 +61,4 @@ class Dg2HwConfig : public DG2 {
static GT_SYSTEM_INFO gtSystemInfo;
};
#include "hw_cmds_dg2.inl"
} // namespace NEO

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@@ -186,5 +186,13 @@ void Dg2HwConfig::setupHardwareInfo(HardwareInfo *hwInfo, bool setupFeatureTable
}
};
const HardwareInfo DG2::hwInfo = Dg2HwConfig::hwInfo;
void setupDG2HardwareInfoImpl(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, uint64_t hwInfoConfig, const CompilerProductHelper &compilerProductHelper) {
DG2::setupHardwareInfoBase(hwInfo, setupFeatureTableAndWorkaroundTable, compilerProductHelper);
Dg2HwConfig::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable, compilerProductHelper);
}
void (*DG2::setupHardwareInfo)(HardwareInfo *, bool, uint64_t, const CompilerProductHelper &) = setupDG2HardwareInfoImpl;
#include "hw_info_setup_dg2.inl"
} // namespace NEO