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performance(ocl): limit flushes on resolve via pc

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When resolving dependencies via pipecontrol skip hdc and untyped data
port cache flushes. Leave only command streamer stall.

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
This commit is contained in:
Dominik Dabek
2024-08-29 15:50:57 +00:00
committed by Compute-Runtime-Automation
parent 1a8149e91c
commit 4552960e1f
2 changed files with 7 additions and 6 deletions
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4
opencl/source/command_queue/enqueue_common.h
View File

@@ -245,8 +245,8 @@ cl_int CommandQueueHw<GfxFamily>::enqueueHandler(Surface **surfacesForResidency,
DEBUG_BREAK_IF(relaxedOrderingForGpgpuAllowed(1)); // IOQ has >=1 dependencies
PipeControlArgs args;
args.csStallOnly = true;
args.hdcPipelineFlush = true;
args.unTypedDataPortCacheFlush = true;
args.hdcPipelineFlush = false;
args.unTypedDataPortCacheFlush = false;
MemorySynchronizationCommands<GfxFamily>::addSingleBarrier(commandStream, args);
}

9
opencl/test/unit_test/helpers/timestamp_packet_1_tests.cpp
View File

@@ -1743,13 +1743,14 @@ HWTEST2_F(TimestampPacketTests, givenTimestampPacketWriteEnabledAndDependenciesR
PIPE_CONTROL *pipeControlCmd = genCmdCast<PIPE_CONTROL *>(*it);
MI_BATCH_BUFFER_END *miBatchBufferEnd = genCmdCast<MI_BATCH_BUFFER_END *>(*it);
if (pipeControlCmd != nullptr) {
EXPECT_TRUE(pipeControlCmd->getHdcPipelineFlush());
EXPECT_TRUE(pipeControlCmd->getUnTypedDataPortCacheFlush());
EXPECT_TRUE(pipeControlCmd->getCommandStreamerStallEnable());
if (currentEnqueue == 1) {
++pipeControlCountFirstEnqueue;
} else if (currentEnqueue == 2) {
++pipeControlCountSecondEnqueue;
if (++pipeControlCountSecondEnqueue == 1) {
EXPECT_FALSE(pipeControlCmd->getHdcPipelineFlush());
EXPECT_FALSE(pipeControlCmd->getUnTypedDataPortCacheFlush());
EXPECT_TRUE(pipeControlCmd->getCommandStreamerStallEnable());
}
}
} else if (semaphoreWaitCmd != nullptr) {
++semaphoreWaitCount;