build: update upstream kernel headers to v6.13

Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
This commit is contained in:
Mateusz Jablonski
2025-02-03 14:46:57 +00:00
committed by Compute-Runtime-Automation
parent 733855e9d9
commit 4679f663be
4 changed files with 39 additions and 2 deletions

View File

@@ -1,2 +1,2 @@
git_revision: v6.12
git_revision: v6.13
git_url: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/

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@@ -1018,6 +1018,13 @@ struct drm_crtc_queue_sequence {
__u64 user_data; /* user data passed to event */
};
#define DRM_CLIENT_NAME_MAX_LEN 64
struct drm_set_client_name {
__u64 name_len;
__u64 name;
};
#if defined(__cplusplus)
}
#endif
@@ -1282,6 +1289,16 @@ extern "C" {
*/
#define DRM_IOCTL_MODE_CLOSEFB DRM_IOWR(0xD0, struct drm_mode_closefb)
/**
* DRM_IOCTL_SET_CLIENT_NAME - Attach a name to a drm_file
*
* Having a name allows for easier tracking and debugging.
* The length of the name (without null ending char) must be
* <= DRM_CLIENT_NAME_MAX_LEN.
* The call will fail if the name contains whitespaces or non-printable chars.
*/
#define DRM_IOCTL_SET_CLIENT_NAME DRM_IOWR(0xD1, struct drm_set_client_name)
/*
* Device specific ioctls should only be in their respective headers
* The device specific ioctl range is from 0x40 to 0x9f.

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@@ -1516,6 +1516,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
* 64K_D_2D on GFX12 is identical to 64K_D on GFX11.
*/
#define AMD_FMT_MOD_TILE_GFX9_64K_D 10
#define AMD_FMT_MOD_TILE_GFX9_4K_D_X 22
#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
#define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26
#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27

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@@ -512,7 +512,9 @@ struct drm_xe_query_gt_list {
* containing the following in mask:
* ``DSS_COMPUTE ff ff ff ff 00 00 00 00``
* means 32 DSS are available for compute.
* - %DRM_XE_TOPO_L3_BANK - To query the mask of enabled L3 banks
* - %DRM_XE_TOPO_L3_BANK - To query the mask of enabled L3 banks. This type
* may be omitted if the driver is unable to query the mask from the
* hardware.
* - %DRM_XE_TOPO_EU_PER_DSS - To query the mask of Execution Units (EU)
* available per Dual Sub Slices (DSS). For example a query response
* containing the following in mask:
@@ -1483,6 +1485,7 @@ struct drm_xe_oa_unit {
/** @capabilities: OA capabilities bit-mask */
__u64 capabilities;
#define DRM_XE_OA_CAPS_BASE (1 << 0)
#define DRM_XE_OA_CAPS_SYNCS (1 << 1)
/** @oa_timestamp_freq: OA timestamp freq */
__u64 oa_timestamp_freq;
@@ -1632,6 +1635,22 @@ enum drm_xe_oa_property_id {
* to be disabled for the stream exec queue.
*/
DRM_XE_OA_PROPERTY_NO_PREEMPT,
/**
* @DRM_XE_OA_PROPERTY_NUM_SYNCS: Number of syncs in the sync array
* specified in @DRM_XE_OA_PROPERTY_SYNCS
*/
DRM_XE_OA_PROPERTY_NUM_SYNCS,
/**
* @DRM_XE_OA_PROPERTY_SYNCS: Pointer to struct @drm_xe_sync array
* with array size specified via @DRM_XE_OA_PROPERTY_NUM_SYNCS. OA
* configuration will wait till input fences signal. Output fences
* will signal after the new OA configuration takes effect. For
* @DRM_XE_SYNC_TYPE_USER_FENCE, @addr is a user pointer, similar
* to the VM bind case.
*/
DRM_XE_OA_PROPERTY_SYNCS,
};
/**