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Add support for Gen11 platform

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Related-To: NEO-2388

Change-Id: I4da92efe7f875f409cd62519a31ed4509b55bda7
Signed-off-by: Jacek Danecki <jacek.danecki@intel.com>
This commit is contained in:
Jacek Danecki
2019-01-10 15:36:57 +01:00
parent 024c54a909
commit 4b2bb188b7
106 changed files with 10023 additions and 11 deletions
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2
Jenkinsfile vendored
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@@ -1,5 +1,5 @@
#!groovy
dependenciesRevision='0dea8bf00d710a5d2da5d04eb5ae595d0df4ce47-1217'
strategy='EQUAL'
allowedCD=274
allowedCD=272
allowedF=4

2
manifests/manifest.yml
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@@ -17,7 +17,7 @@ components:
branch: infra
clean_on_sync: true
dest_dir: infra
revision: 42eaed9a955b168dff2cc81d01b8da3e49bb9997
revision: 0a274a1f06e662b95bd38555efc7188b8842768b
type: git
internal:
branch: master

31
platforms.cmake
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@@ -1,5 +1,5 @@
#
# Copyright (C) 2018 Intel Corporation
# Copyright (C) 2018-2019 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
@@ -11,6 +11,7 @@ set(ALL_GEN_TYPES "")
list(APPEND ALL_GEN_TYPES "GEN8")
list(APPEND ALL_GEN_TYPES "GEN9")
list(APPEND ALL_GEN_TYPES "GEN10")
list(APPEND ALL_GEN_TYPES "GEN11")
set(ALL_GEN_TYPES_REVERSED ${ALL_GEN_TYPES})
list(REVERSE ALL_GEN_TYPES_REVERSED)
@@ -161,6 +162,7 @@ endmacro()
SET_FLAGS_FOR("GEN8" "BDW")
SET_FLAGS_FOR("GEN9" "SKL" "KBL" "BXT" "GLK" "CFL")
SET_FLAGS_FOR("GEN10" "CNL")
SET_FLAGS_FOR("GEN11" "ICLLP" "LKF")
# Init lists
INIT_LIST("FAMILY_NAME" "TESTED")
@@ -257,6 +259,33 @@ if(SUPPORT_GEN10)
endif()
endif()
if(SUPPORT_GEN11)
if(TESTS_GEN11)
ADD_ITEM_FOR_GEN("FAMILY_NAME" "TESTED" "GEN11" "ICLFamily")
endif()
if(SUPPORT_ICLLP)
ADD_PLATFORM_FOR_GEN("SUPPORTED" "GEN11" "ICLLP" "LP")
ADD_PLATFORM_FOR_GEN("SUPPORTED_2_0" "GEN11" "ICLLP" "LP")
if(TESTS_ICLLP)
ADD_ITEM_FOR_GEN("PLATFORMS" "TESTED" "GEN11" "ICLLP")
ADD_ITEM_FOR_GEN("PLATFORMS" "TESTED_APPVERIFIER" "GEN11" "ICLLP")
ADD_ITEM_FOR_GEN("CONFIGURATIONS" "AUB_TESTS" "GEN11" "icllp/1/8/8")
ADD_ITEM_FOR_GEN("CONFIGURATIONS" "MT_TESTS" "GEN11" "icllp/1/8/8")
ADD_ITEM_FOR_GEN("CONFIGURATIONS" "UNIT_TESTS" "GEN11" "icllp/1/8/8")
endif()
endif()
if(SUPPORT_LKF)
ADD_PLATFORM_FOR_GEN("SUPPORTED" "GEN11" "LKF" "LP")
if(TESTS_LKF)
ADD_ITEM_FOR_GEN("PLATFORMS" "TESTED" "GEN11" "LKF")
ADD_ITEM_FOR_GEN("CONFIGURATIONS" "UNIT_TESTS" "GEN11" "lkf/1/8/8")
endif()
endif()
endif()
# Get platform lists, flag definition and set default platforms
GET_AVAILABLE_PLATFORMS("SUPPORTED" "SUPPORT" ALL_AVAILABLE_SUPPORTED_PLATFORMS)
GET_AVAILABLE_PLATFORMS("TESTED" "TESTS" ALL_AVAILABLE_TESTED_PLATFORMS)

4
runtime/aub_mem_dump/aub_services.h
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@@ -96,7 +96,9 @@ struct CmdServicesMemTraceVersion {
Cln = 1,
Kbl = 16,
Bdw = 11,
Cfl = 24
Icllp = 19,
Cfl = 24,
Lkf = 25
};
};
struct RecordingMethodValues {

92
runtime/builtin_kernels_simulation/gen11/scheduler_simulation.cpp Normal file
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@@ -0,0 +1,92 @@
/*
* Copyright (C) 2017-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/builtin_kernels_simulation/scheduler_simulation.h"
#include "runtime/builtin_kernels_simulation/opencl_c.h"
#include "runtime/builtin_kernels_simulation/scheduler_simulation.inl"
#include "runtime/execution_model/device_enqueue.h"
#include "runtime/gen11/hw_cmds.h"
#include "runtime/memory_manager/graphics_allocation.h"
#include "CL/cl.h"
using namespace NEO;
using namespace BuiltinKernelsSimulation;
namespace Gen11SchedulerSimulation {
#define SCHEDULER_EMULATION
uint GetNextPowerof2(uint number);
float __intel__getProfilingTimerResolution() {
return static_cast<float>(DEFAULT_GEN11_PLATFORM::hwInfo.capabilityTable.defaultProfilingTimerResolution);
}
#include "runtime/gen11/device_enqueue.h"
#include "runtime/gen11/scheduler_definitions.h"
#include "runtime/gen11/scheduler_igdrcl_built_in.inl"
#include "runtime/scheduler/scheduler.cl"
} // namespace Gen11SchedulerSimulation
namespace BuiltinKernelsSimulation {
template <>
void SchedulerSimulation<ICLFamily>::startScheduler(uint32_t index,
GraphicsAllocation *queue,
GraphicsAllocation *commandsStack,
GraphicsAllocation *eventsPool,
GraphicsAllocation *secondaryBatchBuffer,
GraphicsAllocation *dsh,
GraphicsAllocation *reflectionSurface,
GraphicsAllocation *queueStorageBuffer,
GraphicsAllocation *ssh,
GraphicsAllocation *debugQueue) {
threadIDToLocalIDmap.insert(std::make_pair(std::this_thread::get_id(), index));
while (!conditionReady) {
}
Gen11SchedulerSimulation::SchedulerParallel20((IGIL_CommandQueue *)queue->getUnderlyingBuffer(),
(uint *)commandsStack->getUnderlyingBuffer(),
(IGIL_EventPool *)eventsPool->getUnderlyingBuffer(),
(uint *)secondaryBatchBuffer->getUnderlyingBuffer(),
(char *)dsh->getUnderlyingBuffer(),
(IGIL_KernelDataHeader *)reflectionSurface->getUnderlyingBuffer(),
(uint *)queueStorageBuffer->getUnderlyingBuffer(),
(char *)ssh->getUnderlyingBuffer(),
debugQueue != nullptr ? (DebugDataBuffer *)debugQueue->getUnderlyingBuffer() : nullptr);
}
template <>
void SchedulerSimulation<ICLFamily>::patchGpGpuWalker(uint secondLevelBatchOffset,
__global uint *secondaryBatchBuffer,
uint interfaceDescriptorOffset,
uint simdSize,
uint totalLocalWorkSize,
uint3 dimSize,
uint3 startPoint,
uint numberOfHwThreadsPerWg,
uint indirectPayloadSize,
uint ioHoffset) {
Gen11SchedulerSimulation::patchGpGpuWalker(secondLevelBatchOffset,
secondaryBatchBuffer,
interfaceDescriptorOffset,
simdSize,
totalLocalWorkSize,
dimSize,
startPoint,
numberOfHwThreadsPerWg,
indirectPayloadSize,
ioHoffset);
}
template class SchedulerSimulation<ICLFamily>;
} // namespace BuiltinKernelsSimulation

21
runtime/dll/linux/devices/devices_base.inl
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@@ -6,6 +6,27 @@
*/
// clang-format off
#ifdef SUPPORT_GEN11
#ifdef SUPPORT_ICLLP
// GT1
DEVICE( IICL_LP_1x1x8_ULT_DEVICE_A0_ID, ICLLP_1x1x8, GTTYPE_GT1 )
DEVICE( IICL_LP_1x4x8_ULT_DEVICE_F0_ID, ICLLP_1x4x8, GTTYPE_GT1 )
DEVICE( IICL_LP_1x4x8_ULX_DEVICE_F0_ID, ICLLP_1x4x8, GTTYPE_GT1 )
DEVICE( IICL_LP_GT1_MOB_DEVICE_F0_ID, ICLLP_1x4x8, GTTYPE_GT1 )
DEVICE( IICL_LP_1x6x8_ULX_DEVICE_F0_ID, ICLLP_1x6x8, GTTYPE_GT1 )
DEVICE( IICL_LP_1x6x8_ULT_DEVICE_F0_ID, ICLLP_1x6x8, GTTYPE_GT1 )
// GT2
DEVICE( IICL_LP_1x8x8_SUPERSKU_DEVICE_F0_ID, ICLLP_1x8x8, GTTYPE_GT2 )
DEVICE( IICL_LP_1x8x8_ULT_DEVICE_F0_ID, ICLLP_1x8x8, GTTYPE_GT2 )
DEVICE( IICL_LP_1x8x8_ULX_DEVICE_F0_ID, ICLLP_1x8x8, GTTYPE_GT2 )
#endif
#ifdef SUPPORT_LKF
DEVICE( ILKF_1x8x8_DESK_DEVICE_F0_ID, LKF_1x8x8, GTTYPE_GT1 )
#endif
#endif
#ifdef SUPPORT_GEN10
DEVICE( ICNL_5x8_DESK_DEVICE_F0_ID, CNL_2x5x8, GTTYPE_GT2 )
DEVICE( ICNL_5x8_DESKTOP_DEVICE_F0_ID, CNL_2x5x8, GTTYPE_GT2 )

4
runtime/gen10/enable_family_full_gen10.cpp
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@@ -22,10 +22,6 @@
namespace NEO {
#ifdef HAVE_INSTRUMENTATION
static_assert(std::is_same<SInstrQueryPerfCountersLayout, SInstrQueryPerfCountersLayout_Gen10>::value, "SInstrQueryPerfCountersLayout_Gen10 mismatch");
#endif
extern HwHelper *hwHelperFactory[IGFX_MAX_CORE];
typedef CNLFamily Family;

30
runtime/gen11/aub_command_stream_receiver_gen11.cpp Normal file
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@@ -0,0 +1,30 @@
/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/command_stream/aub_command_stream_receiver_hw.h"
#include "runtime/command_stream/aub_command_stream_receiver_hw.inl"
#include "runtime/helpers/array_count.h"
#include "runtime/helpers/base_object.h"
namespace NEO {
typedef ICLFamily Family;
static auto gfxCore = IGFX_GEN11_CORE;
template <>
constexpr uint32_t AUBCommandStreamReceiverHw<Family>::getMaskAndValueForPollForCompletion() {
return 0x00008000;
}
template <>
void populateFactoryTable<AUBCommandStreamReceiverHw<Family>>() {
extern AubCommandStreamReceiverCreateFunc aubCommandStreamReceiverFactory[IGFX_MAX_CORE];
UNRECOVERABLE_IF(!isInRange(gfxCore, aubCommandStreamReceiverFactory));
aubCommandStreamReceiverFactory[gfxCore] = AUBCommandStreamReceiverHw<Family>::create;
}
template class AUBCommandStreamReceiverHw<Family>;
} // namespace NEO

30
runtime/gen11/aub_mapper.h Normal file
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@@ -0,0 +1,30 @@
/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "runtime/gen_common/aub_mapper_base.h"
#include "runtime/memory_manager/memory_constants.h"
#include "engine_node.h"
namespace NEO {
struct ICLFamily;
template <>
struct AUBFamilyMapper<ICLFamily> {
enum { device = AubMemDump::DeviceValues::Icllp };
using AubTraits = AubMemDump::Traits<device, MemoryConstants::GfxAddressBits>;
static const AubMemDump::LrcaHelper *const csTraits[aub_stream::NUM_ENGINES];
static const MMIOList globalMMIO;
static const MMIOList *perEngineMMIO[aub_stream::NUM_ENGINES];
typedef AubMemDump::AubDump<AubTraits> AUB;
};
} // namespace NEO

98
runtime/gen11/aub_mem_dump_gen11.cpp Normal file
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@@ -0,0 +1,98 @@
/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/aub_mem_dump/aub_alloc_dump.inl"
#include "runtime/aub_mem_dump/aub_mem_dump.inl"
#include "runtime/helpers/completion_stamp.h"
#include "runtime/helpers/hw_helper.h"
#include "aub_mapper.h"
#include "config.h"
namespace AubMemDump {
enum {
device = DeviceValues::Icllp
};
// Instantiate these common template implementations.
template struct AubDump<Traits<device, 32>>;
template struct AubDump<Traits<device, 48>>;
template struct AubPageTableHelper32<Traits<device, 32>>;
template struct AubPageTableHelper64<Traits<device, 48>>;
} // namespace AubMemDump
namespace NEO {
using Family = ICLFamily;
static const AubMemDump::LrcaHelperRcs rcs(0x002000);
static const AubMemDump::LrcaHelperBcs bcs(0x022000);
static const AubMemDump::LrcaHelperVcs vcs(0x1c0000);
static const AubMemDump::LrcaHelperVecs vecs(0x1c8000);
const AubMemDump::LrcaHelper *const AUBFamilyMapper<Family>::csTraits[aub_stream::NUM_ENGINES] = {
&rcs,
&bcs,
&vcs,
&vecs};
const MMIOList AUBFamilyMapper<Family>::globalMMIO;
static const MMIOList mmioListRCS = {
MMIOPair(0x000020d8, 0x00020000),
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x229c), 0xffff8280),
MMIOPair(0x0000C800, 0x00000009),
MMIOPair(0x0000C804, 0x00000038),
MMIOPair(0x0000C808, 0x0000003B),
MMIOPair(0x0000C80C, 0x00000039),
MMIOPair(0x0000C810, 0x00000037),
MMIOPair(0x0000C814, 0x00000039),
MMIOPair(0x0000C818, 0x00000037),
MMIOPair(0x0000C81C, 0x0000001B),
MMIOPair(0x0000C820, 0x00060037),
MMIOPair(0x0000C824, 0x00000032),
MMIOPair(0x0000C828, 0x00000033),
MMIOPair(0x0000C82C, 0x0000003B),
MMIOPair(0x0000C8C0, 0x00000037),
MMIOPair(0x0000E18C, 0x00200020),
};
static const MMIOList mmioListBCS = {
MMIOPair(AubMemDump::computeRegisterOffset(bcs.mmioBase, 0x229c), 0xffff8280),
};
static const MMIOList mmioListVCS = {
MMIOPair(AubMemDump::computeRegisterOffset(vcs.mmioBase, 0x229c), 0xffff8280),
};
static const MMIOList mmioListVECS = {
MMIOPair(AubMemDump::computeRegisterOffset(vecs.mmioBase, 0x229c), 0xffff8280),
};
const MMIOList *AUBFamilyMapper<Family>::perEngineMMIO[aub_stream::NUM_ENGINES] = {
&mmioListRCS,
&mmioListBCS,
&mmioListVCS,
&mmioListVECS};
} // namespace NEO
namespace AubAllocDump {
using namespace NEO;
template uint32_t getImageSurfaceTypeFromGmmResourceType<Family>(GMM_RESOURCE_TYPE gmmResourceType);
template void dumpBufferInBinFormat<Family>(GraphicsAllocation &gfxAllocation, AubMemDump::AubFileStream *stream, uint32_t context);
template void dumpImageInBmpFormat<Family>(GraphicsAllocation &gfxAllocation, AubMemDump::AubFileStream *stream, uint32_t context);
template void dumpBufferInTreFormat<Family>(GraphicsAllocation &gfxAllocation, AubMemDump::AubFileStream *stream, uint32_t context);
template void dumpImageInTreFormat<Family>(GraphicsAllocation &gfxAllocation, AubMemDump::AubFileStream *stream, uint32_t context);
template void dumpAllocation<Family>(DumpFormat dumpFormat, GraphicsAllocation &gfxAllocation, AubMemDump::AubFileStream *stream, uint32_t context);
} // namespace AubAllocDump

18
runtime/gen11/buffer_gen11.cpp Normal file
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@@ -0,0 +1,18 @@
/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/mem_obj/buffer.inl"
#include "hw_cmds.h"
namespace NEO {
typedef ICLFamily Family;
static auto gfxCore = IGFX_GEN11_CORE;
#include "runtime/mem_obj/buffer_factory_init.inl"
} // namespace NEO

25
runtime/gen11/command_queue_gen11.cpp Normal file
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@@ -0,0 +1,25 @@
/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/command_queue/command_queue_hw.h"
#include "runtime/command_queue/command_queue_hw.inl"
#include "runtime/command_queue/enqueue_resource_barrier.h"
#include "runtime/memory_manager/svm_memory_manager.h"
namespace NEO {
typedef ICLFamily Family;
static auto gfxCore = IGFX_GEN11_CORE;
template class CommandQueueHw<Family>;
template <>
void populateFactoryTable<CommandQueueHw<Family>>() {
extern CommandQueueCreateFunc commandQueueFactory[IGFX_MAX_CORE];
commandQueueFactory[gfxCore] = CommandQueueHw<Family>::create;
}
} // namespace NEO

177
runtime/gen11/command_stream_receiver_hw_gen11.cpp Normal file
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@@ -0,0 +1,177 @@
/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/command_stream/command_stream_receiver_hw.inl"
#include "runtime/command_stream/device_command_stream.h"
#include "runtime/gen11/reg_configs.h"
#include "runtime/os_interface/debug_settings_manager.h"
namespace NEO {
typedef ICLFamily Family;
static auto gfxCore = IGFX_GEN11_CORE;
template <>
size_t CommandStreamReceiverHw<Family>::getCmdSizeForComputeMode() {
if (csrSizeRequestFlags.coherencyRequestChanged) {
return sizeof(typename Family::MI_LOAD_REGISTER_IMM);
}
return 0;
}
template <>
void CommandStreamReceiverHw<Family>::programComputeMode(LinearStream &stream, DispatchFlags &dispatchFlags) {
if (csrSizeRequestFlags.coherencyRequestChanged) {
LriHelper<Family>::program(&stream, gen11HdcModeRegister::address,
DwordBuilder::build(gen11HdcModeRegister::forceNonCoherentEnableBit, true, !dispatchFlags.requiresCoherency));
this->lastSentCoherencyRequest = static_cast<int8_t>(dispatchFlags.requiresCoherency);
}
}
template <>
void CommandStreamReceiverHw<Family>::programMediaSampler(LinearStream &stream, DispatchFlags &dispatchFlags) {
using PWR_CLK_STATE_REGISTER = Family::PWR_CLK_STATE_REGISTER;
if (peekHwInfo().pPlatform->eProductFamily == IGFX_ICELAKE_LP) {
if (dispatchFlags.mediaSamplerRequired) {
if (!lastVmeSubslicesConfig) {
auto pc = addPipeControlCmd(stream);
pc->setDcFlushEnable(true);
pc->setRenderTargetCacheFlushEnable(true);
pc->setInstructionCacheInvalidateEnable(true);
pc->setTextureCacheInvalidationEnable(true);
pc->setPipeControlFlushEnable(true);
pc->setVfCacheInvalidationEnable(true);
pc->setConstantCacheInvalidationEnable(true);
pc->setStateCacheInvalidationEnable(true);
uint32_t numSubslices = peekHwInfo().pSysInfo->SubSliceCount;
uint32_t numSubslicesWithVme = numSubslices / 2; // 1 VME unit per DSS
uint32_t numSlicesForPowerGating = 1; // power gating supported only if #Slices = 1
PWR_CLK_STATE_REGISTER reg = Family::cmdInitPwrClkStateRegister;
reg.TheStructure.Common.EUmin = peekHwInfo().pSysInfo->MaxEuPerSubSlice;
reg.TheStructure.Common.EUmax = peekHwInfo().pSysInfo->MaxEuPerSubSlice;
reg.TheStructure.Common.SSCountEn = 1; // Enable SScount
reg.TheStructure.Common.SScount = numSubslicesWithVme;
reg.TheStructure.Common.EnableSliceCountRequest = 1; // Enable SliceCountRequest
reg.TheStructure.Common.SliceCountRequest = numSlicesForPowerGating;
LriHelper<Family>::program(&stream, PWR_CLK_STATE_REGISTER::REG_ADDRESS, reg.TheStructure.RawData[0]);
addPipeControlCmd(stream);
lastVmeSubslicesConfig = true;
}
} else {
if (lastVmeSubslicesConfig) {
auto pc = addPipeControlCmd(stream);
pc->setDcFlushEnable(true);
pc->setRenderTargetCacheFlushEnable(true);
pc->setInstructionCacheInvalidateEnable(true);
pc->setTextureCacheInvalidationEnable(true);
pc->setPipeControlFlushEnable(true);
pc->setVfCacheInvalidationEnable(true);
pc->setConstantCacheInvalidationEnable(true);
pc->setStateCacheInvalidationEnable(true);
pc->setGenericMediaStateClear(true);
addPipeControlCmd(stream);
// In Gen11-LP, software programs this register as if GT consists of
// 2 slices with 4 subslices in each slice. Hardware maps this to the
// LP 1 slice/8-subslice physical layout
uint32_t numSubslices = peekHwInfo().pSysInfo->SubSliceCount;
uint32_t numSubslicesMapped = numSubslices / 2;
uint32_t numSlicesMapped = peekHwInfo().pSysInfo->SliceCount * 2;
PWR_CLK_STATE_REGISTER reg = Family::cmdInitPwrClkStateRegister;
reg.TheStructure.Common.EUmin = peekHwInfo().pSysInfo->MaxEuPerSubSlice;
reg.TheStructure.Common.EUmax = peekHwInfo().pSysInfo->MaxEuPerSubSlice;
reg.TheStructure.Common.SSCountEn = 1; // Enable SScount
reg.TheStructure.Common.SScount = numSubslicesMapped;
reg.TheStructure.Common.EnableSliceCountRequest = 1; // Enable SliceCountRequest
reg.TheStructure.Common.SliceCountRequest = numSlicesMapped;
LriHelper<Family>::program(&stream, PWR_CLK_STATE_REGISTER::REG_ADDRESS, reg.TheStructure.RawData[0]);
addPipeControlCmd(stream);
}
}
}
}
template <>
bool CommandStreamReceiverHw<Family>::detectInitProgrammingFlagsRequired(const DispatchFlags &dispatchFlags) const {
bool flag = DebugManager.flags.ForceCsrReprogramming.get();
if (peekHwInfo().pPlatform->eProductFamily == IGFX_ICELAKE_LP) {
if (!dispatchFlags.mediaSamplerRequired) {
if (lastVmeSubslicesConfig) {
flag = true;
}
}
}
return flag;
}
template <>
size_t CommandStreamReceiverHw<Family>::getCmdSizeForMediaSampler(bool mediaSamplerRequired) const {
typedef typename Family::MI_LOAD_REGISTER_IMM MI_LOAD_REGISTER_IMM;
typedef typename Family::PIPE_CONTROL PIPE_CONTROL;
if (peekHwInfo().pPlatform->eProductFamily == IGFX_ICELAKE_LP) {
if (mediaSamplerRequired) {
if (!lastVmeSubslicesConfig) {
return sizeof(MI_LOAD_REGISTER_IMM) + 2 * sizeof(PIPE_CONTROL);
}
} else {
if (lastVmeSubslicesConfig) {
return sizeof(MI_LOAD_REGISTER_IMM) + 3 * sizeof(PIPE_CONTROL);
}
}
}
return 0;
}
template <>
void populateFactoryTable<CommandStreamReceiverHw<Family>>() {
extern CommandStreamReceiverCreateFunc commandStreamReceiverFactory[IGFX_MAX_CORE];
commandStreamReceiverFactory[gfxCore] = DeviceCommandStreamReceiver<Family>::create;
}
// Explicitly instantiate CommandStreamReceiverHw for this device family
template class CommandStreamReceiverHw<Family>;
const Family::GPGPU_WALKER Family::cmdInitGpgpuWalker = Family::GPGPU_WALKER::sInit();
const Family::INTERFACE_DESCRIPTOR_DATA Family::cmdInitInterfaceDescriptorData = Family::INTERFACE_DESCRIPTOR_DATA::sInit();
const Family::MEDIA_INTERFACE_DESCRIPTOR_LOAD Family::cmdInitMediaInterfaceDescriptorLoad = Family::MEDIA_INTERFACE_DESCRIPTOR_LOAD::sInit();
const Family::MEDIA_STATE_FLUSH Family::cmdInitMediaStateFlush = Family::MEDIA_STATE_FLUSH::sInit();
const Family::MI_BATCH_BUFFER_START Family::cmdInitBatchBufferStart = Family::MI_BATCH_BUFFER_START::sInit();
const Family::MI_BATCH_BUFFER_END Family::cmdInitBatchBufferEnd = Family::MI_BATCH_BUFFER_END::sInit();
const Family::PIPE_CONTROL Family::cmdInitPipeControl = Family::PIPE_CONTROL::sInit();
const Family::MI_SEMAPHORE_WAIT Family::cmdInitMiSemaphoreWait = Family::MI_SEMAPHORE_WAIT::sInit();
const Family::RENDER_SURFACE_STATE Family::cmdInitRenderSurfaceState = Family::RENDER_SURFACE_STATE::sInit();
const Family::PWR_CLK_STATE_REGISTER Family::cmdInitPwrClkStateRegister = Family::PWR_CLK_STATE_REGISTER::sInit();
const Family::MI_LOAD_REGISTER_IMM Family::cmdInitLoadRegisterImm = Family::MI_LOAD_REGISTER_IMM::sInit();
const Family::MI_LOAD_REGISTER_REG Family::cmdInitLoadRegisterReg = Family::MI_LOAD_REGISTER_REG::sInit();
const Family::MI_LOAD_REGISTER_MEM Family::cmdInitLoadRegisterMem = Family::MI_LOAD_REGISTER_MEM::sInit();
const Family::MI_STORE_DATA_IMM Family::cmdInitStoreDataImm = Family::MI_STORE_DATA_IMM::sInit();
const Family::MI_STORE_REGISTER_MEM Family::cmdInitStoreRegisterMem = Family::MI_STORE_REGISTER_MEM::sInit();
const Family::MI_NOOP Family::cmdInitNoop = Family::MI_NOOP::sInit();
const Family::MI_REPORT_PERF_COUNT Family::cmdInitReportPerfCount = Family::MI_REPORT_PERF_COUNT::sInit();
const Family::MI_ATOMIC Family::cmdInitAtomic = Family::MI_ATOMIC::sInit();
const Family::PIPELINE_SELECT Family::cmdInitPipelineSelect = Family::PIPELINE_SELECT::sInit();
const Family::MI_ARB_CHECK Family::cmdInitArbCheck = Family::MI_ARB_CHECK::sInit();
const Family::MEDIA_VFE_STATE Family::cmdInitMediaVfeState = Family::MEDIA_VFE_STATE::sInit();
const Family::STATE_BASE_ADDRESS Family::cmdInitStateBaseAddress = Family::STATE_BASE_ADDRESS::sInit();
const Family::MEDIA_SURFACE_STATE Family::cmdInitMediaSurfaceState = Family::MEDIA_SURFACE_STATE::sInit();
const Family::SAMPLER_STATE Family::cmdInitSamplerState = Family::SAMPLER_STATE::sInit();
const Family::GPGPU_CSR_BASE_ADDRESS Family::cmdInitGpgpuCsrBaseAddress = Family::GPGPU_CSR_BASE_ADDRESS::sInit();
const Family::STATE_SIP Family::cmdInitStateSip = Family::STATE_SIP::sInit();
const Family::BINDING_TABLE_STATE Family::cmdInitBindingTableState = Family::BINDING_TABLE_STATE::sInit();
const Family::MI_USER_INTERRUPT Family::cmdInitUserInterrupt = Family::MI_USER_INTERRUPT::sInit();
const Family::XY_SRC_COPY_BLT Family::cmdInitXyCopyBlt = Family::XY_SRC_COPY_BLT::sInit();
const Family::MI_FLUSH_DW Family::cmdInitMiFlushDw = Family::MI_FLUSH_DW::sInit();
} // namespace NEO

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/command_stream/command_stream_receiver_simulated_common_hw.inl"
namespace NEO {
typedef ICLFamily Family;
template <>
void CommandStreamReceiverSimulatedCommonHw<Family>::submitLRCA(const MiContextDescriptorReg &contextDescriptor) {
auto mmioBase = getCsTraits(osContext->getEngineType()).mmioBase;
stream->writeMMIO(AubMemDump::computeRegisterOffset(mmioBase, 0x2510), contextDescriptor.ulData[0]);
stream->writeMMIO(AubMemDump::computeRegisterOffset(mmioBase, 0x2514), contextDescriptor.ulData[1]);
// Load our new exec list
stream->writeMMIO(AubMemDump::computeRegisterOffset(mmioBase, 0x2550), 1);
}
template class CommandStreamReceiverSimulatedCommonHw<Family>;
} // namespace NEO

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "../execution_model/device_enqueue.h"
// Uncomment this macro to build "empty" schedulers
//#define WA_DISABLE_SCHEDULERS 1
#define OCLRT_GPGPU_WALKER_CMD_DEVICE_CMD_G11 (15 * sizeof(uint))
#define OCLRT_PIPE_CONTROL_CMD_DEVICE_CMD_G11 (6 * sizeof(uint))
#define OCLRT_PIPE_CONTROL_CMD_DEVICE_CMD_G11_DWORD_OFFSET (6)
#define OCLRT_GPGPU_WALKER_CMD_DEVICE_CMD_G11_DWORD_OFFSET (15)
#define SLB_SPACE_FOR_EACH_ENQUEUE_UNALIGNED_GEN11 (OCLRT_SIZEOF_MEDIA_STATE_FLUSH + OCLRT_SIZEOF_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DEVICE_CMD + OCLRT_PIPE_CONTROL_CMD_DEVICE_CMD_G11 + OCLRT_GPGPU_WALKER_CMD_DEVICE_CMD_G11 + OCLRT_SIZEOF_MEDIA_STATE_FLUSH + OCLRT_PIPE_CONTROL_CMD_DEVICE_CMD_G11)
#define SLB_SIZE_ALIGNEMENT_WA_GEN11 52
#define SECOND_LEVEL_BUFFER_SPACE_FOR_EACH_ENQUEUE_GEN11 (SLB_SPACE_FOR_EACH_ENQUEUE_UNALIGNED_GEN11 + SLB_SIZE_ALIGNEMENT_WA_GEN11 + CS_PREFETCH_SIZE)
#define SECOND_LEVEL_BUFFER_NUMBER_OF_ENQUEUES_GEN11 (128)

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/device_queue/device_queue_hw.h"
#include "runtime/device_queue/device_queue_hw.inl"
#include "runtime/device_queue/device_queue_hw_profiling.inl"
#include "runtime/gen11/device_enqueue.h"
#include "runtime/gen11/hw_cmds.h"
namespace NEO {
typedef ICLFamily Family;
static auto gfxCore = IGFX_GEN11_CORE;
template <>
void populateFactoryTable<DeviceQueueHw<Family>>() {
extern DeviceQueueCreateFunc deviceQueueFactory[IGFX_MAX_CORE];
deviceQueueFactory[gfxCore] = DeviceQueueHw<Family>::create;
}
static const size_t csPrefetchSizeAlignementWa = SLB_SIZE_ALIGNEMENT_WA_GEN11;
template <>
size_t DeviceQueueHw<Family>::getCSPrefetchSize() {
return 8 * MemoryConstants::cacheLineSize + csPrefetchSizeAlignementWa;
}
template <>
size_t DeviceQueueHw<Family>::getWaCommandsSize() { return 0; }
template <>
void DeviceQueueHw<Family>::addArbCheckCmdWa() {}
template <>
void DeviceQueueHw<Family>::addMiAtomicCmdWa(uint64_t atomicOpPlaceholder) {}
template <>
void DeviceQueueHw<Family>::addLriCmdWa(bool setArbCheck) {}
template <>
void DeviceQueueHw<Family>::addPipeControlCmdWa(bool isNoopCmd) {}
template class DeviceQueueHw<Family>;
} // namespace NEO

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runtime/gen11/enable_family_full_gen11.cpp Normal file
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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/command_queue/command_queue_hw.h"
#include "runtime/command_stream/aub_command_stream_receiver_hw.h"
#include "runtime/command_stream/command_stream_receiver_hw.h"
#include "runtime/command_stream/tbx_command_stream_receiver_hw.h"
#include "runtime/device_queue/device_queue_hw.h"
#include "hw_cmds.h"
#ifdef HAVE_INSTRUMENTATION
#include "runtime/event/perf_counter.h"
#endif
#include "runtime/helpers/hw_helper.h"
#include "runtime/mem_obj/buffer.h"
#include "runtime/mem_obj/image.h"
#include "runtime/sampler/sampler.h"
namespace NEO {
extern HwHelper *hwHelperFactory[IGFX_MAX_CORE];
typedef ICLFamily Family;
static auto gfxFamily = IGFX_GEN11_CORE;
struct EnableGen11 {
EnableGen11() {
populateFactoryTable<AUBCommandStreamReceiverHw<Family>>();
populateFactoryTable<TbxCommandStreamReceiverHw<Family>>();
populateFactoryTable<CommandQueueHw<Family>>();
populateFactoryTable<DeviceQueueHw<Family>>();
populateFactoryTable<CommandStreamReceiverHw<Family>>();
populateFactoryTable<BufferHw<Family>>();
populateFactoryTable<ImageHw<Family>>();
populateFactoryTable<SamplerHw<Family>>();
hwHelperFactory[gfxFamily] = &HwHelperHw<Family>::get();
}
};
static EnableGen11 enable;
} // namespace NEO

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/helpers/enable_product.inl"
#include "runtime/os_interface/hw_info_config.h"
#include "hw_cmds.h"
namespace NEO {
#ifdef SUPPORT_ICLLP
static EnableGfxProductHw<IGFX_ICELAKE_LP> enableGfxProductHwICLLP;
#endif
#ifdef SUPPORT_LKF
static EnableGfxProductHw<IGFX_LAKEFIELD> enableGfxProductHwLKF;
#endif
} // namespace NEO

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/os_interface/hw_info_config.h"
#include "hw_cmds.h"
namespace NEO {
#ifdef SUPPORT_ICLLP
static EnableProductHwInfoConfig<IGFX_ICELAKE_LP> enableICLLP;
#endif
#ifdef SUPPORT_LKF
static EnableProductHwInfoConfig<IGFX_LAKEFIELD> enableLKF;
#endif
} // namespace NEO

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/command_stream/experimental_command_buffer.h"
#include "runtime/command_stream/experimental_command_buffer.inl"
#include "runtime/helpers/hw_helper.h"
namespace NEO {
typedef ICLFamily GfxFamily;
template void ExperimentalCommandBuffer::injectBufferStart<GfxFamily>(LinearStream &parentStream, size_t cmdBufferOffset);
template size_t ExperimentalCommandBuffer::getRequiredInjectionSize<GfxFamily>() noexcept;
template size_t ExperimentalCommandBuffer::programExperimentalCommandBuffer<GfxFamily>();
template size_t ExperimentalCommandBuffer::getTotalExperimentalSize<GfxFamily>() noexcept;
template void ExperimentalCommandBuffer::addTimeStampPipeControl<GfxFamily>();
template size_t ExperimentalCommandBuffer::getTimeStampPipeControlSize<GfxFamily>() noexcept;
template void ExperimentalCommandBuffer::addExperimentalCommands<GfxFamily>();
template size_t ExperimentalCommandBuffer::getExperimentalCommandsSize<GfxFamily>() noexcept;
} // namespace NEO

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runtime/gen11/gpgpu_walker_gen11.cpp Normal file
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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/command_queue/gpgpu_walker.h"
#include "runtime/command_queue/gpgpu_walker.inl"
#include "runtime/command_queue/gpgpu_walker_base.inl"
#include "runtime/command_queue/hardware_interface.h"
#include "runtime/command_queue/hardware_interface.inl"
#include "runtime/command_queue/hardware_interface_base.inl"
#include "runtime/gen11/hw_info.h"
namespace NEO {
template class HardwareInterface<ICLFamily>;
template class GpgpuWalkerHelper<ICLFamily>;
template struct EnqueueOperation<ICLFamily>;
} // namespace NEO

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runtime/gen11/gtpin_setup_gen11.cpp Normal file
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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/gtpin/gtpin_hw_helper.h"
#include "runtime/gtpin/gtpin_hw_helper.inl"
#include "ocl_igc_shared/gtpin/gtpin_ocl_interface.h"
namespace NEO {
extern GTPinHwHelper *gtpinHwHelperFactory[IGFX_MAX_CORE];
typedef ICLFamily Family;
static const auto gfxFamily = IGFX_GEN11_CORE;
template <>
uint32_t GTPinHwHelperHw<Family>::getGenVersion() {
return gtpin::GTPIN_GEN_11;
}
template class GTPinHwHelperHw<Family>;
struct GTPinEnableGen11 {
GTPinEnableGen11() {
gtpinHwHelperFactory[gfxFamily] = &GTPinHwHelperHw<Family>::get();
}
};
static GTPinEnableGen11 gtpinEnable;
} // namespace NEO

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#ifdef SUPPORT_ICLLP
#include "hw_cmds_icllp.h"
#endif
#ifdef SUPPORT_LKF
#include "hw_cmds_lkf.h"
#endif

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "runtime/commands/bxml_generator_glue.h"
#include "runtime/helpers/debug_helpers.h"
#include "hw_info.h"
#include "igfxfmid.h"
#include <cstddef>
template <class T>
struct CmdParse;
namespace NEO {
struct GEN11 {
#include "runtime/gen11/hw_cmds_generated.h"
#include "runtime/gen11/hw_cmds_generated_patched.h"
};
struct ICLFamily : public GEN11 {
using PARSE = CmdParse<ICLFamily>;
using GfxFamily = ICLFamily;
using WALKER_TYPE = GPGPU_WALKER;
using XY_COPY_BLT = typename GfxFamily::XY_SRC_COPY_BLT;
using MI_STORE_REGISTER_MEM_CMD = typename GfxFamily::MI_STORE_REGISTER_MEM;
static const GPGPU_WALKER cmdInitGpgpuWalker;
static const INTERFACE_DESCRIPTOR_DATA cmdInitInterfaceDescriptorData;
static const MEDIA_INTERFACE_DESCRIPTOR_LOAD cmdInitMediaInterfaceDescriptorLoad;
static const MEDIA_STATE_FLUSH cmdInitMediaStateFlush;
static const MI_BATCH_BUFFER_END cmdInitBatchBufferEnd;
static const MI_BATCH_BUFFER_START cmdInitBatchBufferStart;
static const PIPE_CONTROL cmdInitPipeControl;
static const MI_SEMAPHORE_WAIT cmdInitMiSemaphoreWait;
static const RENDER_SURFACE_STATE cmdInitRenderSurfaceState;
static const PWR_CLK_STATE_REGISTER cmdInitPwrClkStateRegister;
static const MI_LOAD_REGISTER_IMM cmdInitLoadRegisterImm;
static const MI_LOAD_REGISTER_REG cmdInitLoadRegisterReg;
static const MI_LOAD_REGISTER_MEM cmdInitLoadRegisterMem;
static const MI_STORE_DATA_IMM cmdInitStoreDataImm;
static const MI_STORE_REGISTER_MEM cmdInitStoreRegisterMem;
static const MI_NOOP cmdInitNoop;
static const MI_REPORT_PERF_COUNT cmdInitReportPerfCount;
static const MI_ATOMIC cmdInitAtomic;
static const PIPELINE_SELECT cmdInitPipelineSelect;
static const MI_ARB_CHECK cmdInitArbCheck;
static const MEDIA_VFE_STATE cmdInitMediaVfeState;
static const STATE_BASE_ADDRESS cmdInitStateBaseAddress;
static const MEDIA_SURFACE_STATE cmdInitMediaSurfaceState;
static const SAMPLER_STATE cmdInitSamplerState;
static const GPGPU_CSR_BASE_ADDRESS cmdInitGpgpuCsrBaseAddress;
static const STATE_SIP cmdInitStateSip;
static const BINDING_TABLE_STATE cmdInitBindingTableState;
static const MI_USER_INTERRUPT cmdInitUserInterrupt;
static const XY_SRC_COPY_BLT cmdInitXyCopyBlt;
static const MI_FLUSH_DW cmdInitMiFlushDw;
static constexpr bool supportsCmdSet(GFXCORE_FAMILY cmdSetBaseFamily) {
return cmdSetBaseFamily == IGFX_GEN8_CORE;
}
};
} // namespace NEO

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#pragma pack(1)
typedef struct tagMI_BATCH_BUFFER_START {
union tagTheStructure {
struct tagCommon {
uint32_t DwordLength : BITFIELD_RANGE(0, 7);
uint32_t AddressSpaceIndicator : BITFIELD_RANGE(8, 8);
uint32_t Reserved_9 : BITFIELD_RANGE(9, 9);
uint32_t ResourceStreamerEnable : BITFIELD_RANGE(10, 10);
uint32_t Reserved_11 : BITFIELD_RANGE(11, 14);
uint32_t PredicationEnable : BITFIELD_RANGE(15, 15);
uint32_t Reserved_16 : BITFIELD_RANGE(16, 19);
uint32_t PoshEnable : BITFIELD_RANGE(20, 20);
uint32_t PoshStart : BITFIELD_RANGE(21, 21);
uint32_t SecondLevelBatchBuffer : BITFIELD_RANGE(22, 22);
uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28);
uint32_t CommandType : BITFIELD_RANGE(29, 31);
uint64_t Reserved_32 : BITFIELD_RANGE(0, 1);
uint64_t BatchBufferStartAddress_Graphicsaddress39_2 : BITFIELD_RANGE(2, 47);
uint64_t BatchBufferStartAddress_Reserved : BITFIELD_RANGE(48, 63);
} Common;
uint32_t RawData[3];
} TheStructure;
typedef enum tagDWORD_LENGTH {
DWORD_LENGTH_EXCLUDES_DWORD_0_1 = 0x1,
} DWORD_LENGTH;
typedef enum tagADDRESS_SPACE_INDICATOR {
ADDRESS_SPACE_INDICATOR_GGTT = 0x0,
ADDRESS_SPACE_INDICATOR_PPGTT = 0x1,
} ADDRESS_SPACE_INDICATOR;
typedef enum tagSECOND_LEVEL_BATCH_BUFFER {
SECOND_LEVEL_BATCH_BUFFER_FIRST_LEVEL_BATCH = 0x0,
SECOND_LEVEL_BATCH_BUFFER_SECOND_LEVEL_BATCH = 0x1,
} SECOND_LEVEL_BATCH_BUFFER;
typedef enum tagMI_COMMAND_OPCODE {
MI_COMMAND_OPCODE_MI_BATCH_BUFFER_START = 0x31,
} MI_COMMAND_OPCODE;
typedef enum tagCOMMAND_TYPE {
COMMAND_TYPE_MI_COMMAND = 0x0,
} COMMAND_TYPE;
inline void init(void) {
memset(&TheStructure, 0, sizeof(TheStructure));
TheStructure.Common.DwordLength = DWORD_LENGTH_EXCLUDES_DWORD_0_1;
TheStructure.Common.AddressSpaceIndicator = ADDRESS_SPACE_INDICATOR_GGTT;
TheStructure.Common.SecondLevelBatchBuffer = SECOND_LEVEL_BATCH_BUFFER_FIRST_LEVEL_BATCH;
TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE_MI_BATCH_BUFFER_START;
TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND;
}
static tagMI_BATCH_BUFFER_START sInit(void) {
MI_BATCH_BUFFER_START state;
state.init();
return state;
}
inline uint32_t &getRawData(const uint32_t index) {
DEBUG_BREAK_IF(index >= 3);
return TheStructure.RawData[index];
}
inline void setAddressSpaceIndicator(const ADDRESS_SPACE_INDICATOR value) {
TheStructure.Common.AddressSpaceIndicator = value;
}
inline ADDRESS_SPACE_INDICATOR getAddressSpaceIndicator(void) const {
return static_cast<ADDRESS_SPACE_INDICATOR>(TheStructure.Common.AddressSpaceIndicator);
}
inline void setResourceStreamerEnable(const bool value) {
TheStructure.Common.ResourceStreamerEnable = value;
}
inline bool getResourceStreamerEnable(void) const {
return (TheStructure.Common.ResourceStreamerEnable);
}
inline void setPredicationEnable(const uint32_t value) {
TheStructure.Common.PredicationEnable = value;
}
inline uint32_t getPredicationEnable(void) const {
return (TheStructure.Common.PredicationEnable);
}
inline void setPoshEnable(const uint32_t value) {
TheStructure.Common.PoshEnable = value;
}
inline uint32_t getPoshEnable(void) const {
return (TheStructure.Common.PoshEnable);
}
inline void setPoshStart(const uint32_t value) {
TheStructure.Common.PoshStart = value;
}
inline uint32_t getPoshStart(void) const {
return (TheStructure.Common.PoshStart);
}
inline void setSecondLevelBatchBuffer(const SECOND_LEVEL_BATCH_BUFFER value) {
TheStructure.Common.SecondLevelBatchBuffer = value;
}
inline SECOND_LEVEL_BATCH_BUFFER getSecondLevelBatchBuffer(void) const {
return static_cast<SECOND_LEVEL_BATCH_BUFFER>(TheStructure.Common.SecondLevelBatchBuffer);
}
typedef enum tagBATCHBUFFERSTARTADDRESS_GRAPHICSADDRESS39_2 {
BATCHBUFFERSTARTADDRESS_GRAPHICSADDRESS39_2_BIT_SHIFT = 0x2,
BATCHBUFFERSTARTADDRESS_GRAPHICSADDRESS39_2_ALIGN_SIZE = 0x4,
} BATCHBUFFERSTARTADDRESS_GRAPHICSADDRESS39_2;
inline void setBatchBufferStartAddressGraphicsaddress392(const uint64_t value) {
TheStructure.Common.BatchBufferStartAddress_Graphicsaddress39_2 = value >> BATCHBUFFERSTARTADDRESS_GRAPHICSADDRESS39_2_BIT_SHIFT;
}
inline uint64_t getBatchBufferStartAddressGraphicsaddress392(void) const {
return (TheStructure.Common.BatchBufferStartAddress_Graphicsaddress39_2 << BATCHBUFFERSTARTADDRESS_GRAPHICSADDRESS39_2_BIT_SHIFT);
}
inline void setBatchBufferStartAddressGraphicsaddress472(const uint64_t value) {
setBatchBufferStartAddressGraphicsaddress392(value);
}
inline uint64_t getBatchBufferStartAddressGraphicsaddress472(void) const {
return getBatchBufferStartAddressGraphicsaddress392();
}
typedef enum tagBATCHBUFFERSTARTADDRESS_RESERVED {
BATCHBUFFERSTARTADDRESS_RESERVED_BIT_SHIFT = 0x2,
BATCHBUFFERSTARTADDRESS_RESERVED_ALIGN_SIZE = 0x4,
} BATCHBUFFERSTARTADDRESS_RESERVED;
inline void setBatchBufferStartAddressReserved(const uint64_t value) {
TheStructure.Common.BatchBufferStartAddress_Reserved = value >> BATCHBUFFERSTARTADDRESS_RESERVED_BIT_SHIFT;
}
inline uint64_t getBatchBufferStartAddressReserved(void) const {
return (TheStructure.Common.BatchBufferStartAddress_Reserved << BATCHBUFFERSTARTADDRESS_RESERVED_BIT_SHIFT);
}
} MI_BATCH_BUFFER_START;
STATIC_ASSERT(12 == sizeof(MI_BATCH_BUFFER_START));
typedef struct tagMEDIA_SURFACE_STATE {
union tagTheStructure {
struct tagCommon {
uint32_t Reserved_0 : BITFIELD_RANGE(0, 29);
uint32_t Rotation : BITFIELD_RANGE(30, 31);
uint32_t Cr_VCb_UPixelOffsetVDirection : BITFIELD_RANGE(0, 1);
uint32_t PictureStructure : BITFIELD_RANGE(2, 3);
uint32_t Width : BITFIELD_RANGE(4, 17);
uint32_t Height : BITFIELD_RANGE(18, 31);
uint32_t TileMode : BITFIELD_RANGE(0, 1);
uint32_t HalfPitchForChroma : BITFIELD_RANGE(2, 2);
uint32_t SurfacePitch : BITFIELD_RANGE(3, 20);
uint32_t AddressControl : BITFIELD_RANGE(21, 21);
uint32_t MemoryCompressionEnable : BITFIELD_RANGE(22, 22);
uint32_t MemoryCompressionMode : BITFIELD_RANGE(23, 23);
uint32_t Cr_VCb_UPixelOffsetVDirectionMsb : BITFIELD_RANGE(24, 24);
uint32_t Cr_VCb_UPixelOffsetUDirection : BITFIELD_RANGE(25, 25);
uint32_t InterleaveChroma : BITFIELD_RANGE(26, 26);
uint32_t SurfaceFormat : BITFIELD_RANGE(27, 31);
uint32_t YOffsetForU_Cb : BITFIELD_RANGE(0, 13);
uint32_t Reserved_110 : BITFIELD_RANGE(14, 15);
uint32_t XOffsetForU_Cb : BITFIELD_RANGE(16, 29);
uint32_t Reserved_126 : BITFIELD_RANGE(30, 31);
uint32_t Reserved_128;
uint32_t SurfaceMemoryObjectControlState_Reserved : BITFIELD_RANGE(0, 0);
uint32_t SurfaceMemoryObjectControlState_IndexToMocsTables : BITFIELD_RANGE(1, 6);
uint32_t Reserved_167 : BITFIELD_RANGE(7, 17);
uint32_t TiledResourceMode : BITFIELD_RANGE(18, 19);
uint32_t Depth : BITFIELD_RANGE(20, 23);
uint32_t Reserved_184 : BITFIELD_RANGE(24, 29);
uint32_t VerticalLineStrideOffset : BITFIELD_RANGE(30, 30);
uint32_t VerticalLineStride : BITFIELD_RANGE(31, 31);
uint32_t SurfaceBaseAddressLow;
uint32_t SurfaceBaseAddressHigh : BITFIELD_RANGE(0, 15);
uint32_t Reserved_240 : BITFIELD_RANGE(16, 31);
} Common;
struct tagSurfaceFormatIsNotOneOfPlanarFormats {
uint32_t Reserved_0;
uint32_t Reserved_32;
uint32_t Reserved_64;
uint32_t Reserved_96;
uint32_t Reserved_128;
uint32_t Reserved_160;
uint32_t Reserved_192;
uint32_t Reserved_224;
} SurfaceFormatIsNotOneOfPlanarFormats;
struct tagSurfaceFormatIsOneOfPlanarFormats {
uint32_t Reserved_0 : BITFIELD_RANGE(0, 15);
uint32_t YOffset : BITFIELD_RANGE(16, 19);
uint32_t XOffset : BITFIELD_RANGE(20, 26);
uint32_t Reserved_27 : BITFIELD_RANGE(27, 31);
uint32_t Reserved_32;
uint32_t Reserved_64;
uint32_t Reserved_96;
uint32_t Reserved_128;
uint32_t Reserved_160;
uint32_t Reserved_192;
uint32_t Reserved_224;
} SurfaceFormatIsOneOfPlanarFormats;
struct tag_SurfaceFormatIsOneOfPlanarAnd_InterleaveChromaIs0 {
uint32_t Reserved_0;
uint32_t Reserved_32;
uint32_t Reserved_64;
uint32_t Reserved_96;
uint32_t YOffsetForV_Cr : BITFIELD_RANGE(0, 14);
uint32_t Reserved_143 : BITFIELD_RANGE(15, 15);
uint32_t XOffsetForV_Cr : BITFIELD_RANGE(16, 29);
uint32_t Reserved_158 : BITFIELD_RANGE(30, 31);
uint32_t Reserved_160;
uint32_t Reserved_192;
uint32_t Reserved_224;
} _SurfaceFormatIsOneOfPlanarAnd_InterleaveChromaIs0;
uint32_t RawData[8];
} TheStructure;
typedef enum tagROTATION {
ROTATION_NO_ROTATION_OR_0_DEGREE = 0x0,
ROTATION_90_DEGREE_ROTATION = 0x1,
ROTATION_180_DEGREE_ROTATION = 0x2,
ROTATION_270_DEGREE_ROTATION = 0x3,
} ROTATION;
typedef enum tagPICTURE_STRUCTURE {
PICTURE_STRUCTURE_FRAME_PICTURE = 0x0,
PICTURE_STRUCTURE_TOP_FIELD_PICTURE = 0x1,
PICTURE_STRUCTURE_BOTTOM_FIELD_PICTURE = 0x2,
PICTURE_STRUCTURE_INVALID_NOT_ALLOWED = 0x3,
} PICTURE_STRUCTURE;
typedef enum tagTILE_MODE {
TILE_MODE_TILEMODE_LINEAR = 0x0,
TILE_MODE_TILEMODE_XMAJOR = 0x2,
TILE_MODE_TILEMODE_YMAJOR = 0x3,
} TILE_MODE;
typedef enum tagADDRESS_CONTROL {
ADDRESS_CONTROL_CLAMP = 0x0,
ADDRESS_CONTROL_MIRROR = 0x1,
} ADDRESS_CONTROL;
typedef enum tagMEMORY_COMPRESSION_MODE {
MEMORY_COMPRESSION_MODE_HORIZONTAL_COMPRESSION_MODE = 0x0,
MEMORY_COMPRESSION_MODE_VERTICAL_COMPRESSION_MODE = 0x1,
} MEMORY_COMPRESSION_MODE;
typedef enum tagSURFACE_FORMAT {
SURFACE_FORMAT_YCRCB_NORMAL = 0x0,
SURFACE_FORMAT_YCRCB_SWAPUVY = 0x1,
SURFACE_FORMAT_YCRCB_SWAPUV = 0x2,
SURFACE_FORMAT_YCRCB_SWAPY = 0x3,
SURFACE_FORMAT_PLANAR_420_8 = 0x4,
SURFACE_FORMAT_Y8_UNORM_VA = 0x5,
SURFACE_FORMAT_Y16_SNORM = 0x6,
SURFACE_FORMAT_Y16_UNORM_VA = 0x7,
SURFACE_FORMAT_R10G10B10A2_UNORM = 0x8,
SURFACE_FORMAT_R8G8B8A8_UNORM = 0x9,
SURFACE_FORMAT_R8B8_UNORM_CRCB = 0xa,
SURFACE_FORMAT_R8_UNORM_CR_CB = 0xb,
SURFACE_FORMAT_Y8_UNORM = 0xc,
SURFACE_FORMAT_A8Y8U8V8_UNORM = 0xd,
SURFACE_FORMAT_B8G8R8A8_UNORM = 0xe,
SURFACE_FORMAT_R16G16B16A16 = 0xf,
SURFACE_FORMAT_Y1_UNORM = 0x10,
SURFACE_FORMAT_Y32_UNORM = 0x11,
SURFACE_FORMAT_PLANAR_422_8 = 0x12,
SURFACE_FORMAT_FM_STRBUF_Y1 = 0x13,
SURFACE_FORMAT_FM_STRBUF_Y8 = 0x14,
SURFACE_FORMAT_FM_STRBUF_Y16 = 0x15,
SURFACE_FORMAT_FM_STRBUF_Y32 = 0x16,
SURFACE_FORMAT_PLANAR_420_16 = 0x17,
SURFACE_FORMAT_R16B16_UNORM_CRCB = 0x18,
SURFACE_FORMAT_R16_UNORM_CR_CB = 0x19,
SURFACE_FORMAT_Y16_UNORM = 0x1a,
} SURFACE_FORMAT;
typedef enum tagSURFACE_MEMORY_OBJECT_CONTROL_STATE {
SURFACE_MEMORY_OBJECT_CONTROL_STATE_DEFAULTVAUEDESC = 0x0,
} SURFACE_MEMORY_OBJECT_CONTROL_STATE;
typedef enum tagTILED_RESOURCE_MODE {
TILED_RESOURCE_MODE_TRMODE_NONE = 0x0,
TILED_RESOURCE_MODE_TRMODE_TILEYF = 0x1,
TILED_RESOURCE_MODE_TRMODE_TILEYS = 0x2,
} TILED_RESOURCE_MODE;
typedef enum tagPATCH_CONSTANTS {
SURFACEBASEADDRESS_BYTEOFFSET = 0x18,
SURFACEBASEADDRESS_INDEX = 0x6,
SURFACEBASEADDRESSHIGH_BYTEOFFSET = 0x1c,
SURFACEBASEADDRESSHIGH_INDEX = 0x7,
} PATCH_CONSTANTS;
inline void init(void) {
memset(&TheStructure, 0, sizeof(TheStructure));
TheStructure.Common.Rotation = ROTATION_NO_ROTATION_OR_0_DEGREE;
TheStructure.Common.PictureStructure = PICTURE_STRUCTURE_FRAME_PICTURE;
TheStructure.Common.TileMode = TILE_MODE_TILEMODE_LINEAR;
TheStructure.Common.AddressControl = ADDRESS_CONTROL_CLAMP;
TheStructure.Common.MemoryCompressionMode = MEMORY_COMPRESSION_MODE_HORIZONTAL_COMPRESSION_MODE;
TheStructure.Common.SurfaceFormat = SURFACE_FORMAT_YCRCB_NORMAL;
TheStructure.Common.TiledResourceMode = TILED_RESOURCE_MODE_TRMODE_NONE;
}
static tagMEDIA_SURFACE_STATE sInit(void) {
MEDIA_SURFACE_STATE state;
state.init();
return state;
}
inline uint32_t &getRawData(const uint32_t index) {
DEBUG_BREAK_IF(index >= 8);
return TheStructure.RawData[index];
}
inline void setRotation(const ROTATION value) {
TheStructure.Common.Rotation = value;
}
inline ROTATION getRotation(void) const {
return static_cast<ROTATION>(TheStructure.Common.Rotation);
}
inline void setCrVCbUPixelOffsetVDirection(const uint32_t value) {
TheStructure.Common.Cr_VCb_UPixelOffsetVDirection = value;
}
inline uint32_t getCrVCbUPixelOffsetVDirection(void) const {
return (TheStructure.Common.Cr_VCb_UPixelOffsetVDirection);
}
inline void setPictureStructure(const PICTURE_STRUCTURE value) {
TheStructure.Common.PictureStructure = value;
}
inline PICTURE_STRUCTURE getPictureStructure(void) const {
return static_cast<PICTURE_STRUCTURE>(TheStructure.Common.PictureStructure);
}
inline void setWidth(const uint32_t value) {
TheStructure.Common.Width = value - 1;
}
inline uint32_t getWidth(void) const {
return (TheStructure.Common.Width + 1);
}
inline void setHeight(const uint32_t value) {
TheStructure.Common.Height = value - 1;
}
inline uint32_t getHeight(void) const {
return (TheStructure.Common.Height + 1);
}
inline void setTileMode(const TILE_MODE value) {
TheStructure.Common.TileMode = value;
}
inline TILE_MODE getTileMode(void) const {
return static_cast<TILE_MODE>(TheStructure.Common.TileMode);
}
inline void setHalfPitchForChroma(const bool value) {
TheStructure.Common.HalfPitchForChroma = value;
}
inline bool getHalfPitchForChroma(void) const {
return (TheStructure.Common.HalfPitchForChroma);
}
inline void setSurfacePitch(const uint32_t value) {
TheStructure.Common.SurfacePitch = value - 1;
}
inline uint32_t getSurfacePitch(void) const {
return (TheStructure.Common.SurfacePitch + 1);
}
inline void setAddressControl(const ADDRESS_CONTROL value) {
TheStructure.Common.AddressControl = value;
}
inline ADDRESS_CONTROL getAddressControl(void) const {
return static_cast<ADDRESS_CONTROL>(TheStructure.Common.AddressControl);
}
inline void setMemoryCompressionEnable(const bool value) {
TheStructure.Common.MemoryCompressionEnable = value;
}
inline bool getMemoryCompressionEnable(void) const {
return (TheStructure.Common.MemoryCompressionEnable);
}
inline void setMemoryCompressionMode(const MEMORY_COMPRESSION_MODE value) {
TheStructure.Common.MemoryCompressionMode = value;
}
inline MEMORY_COMPRESSION_MODE getMemoryCompressionMode(void) const {
return static_cast<MEMORY_COMPRESSION_MODE>(TheStructure.Common.MemoryCompressionMode);
}
inline void setCrVCbUPixelOffsetVDirectionMsb(const uint32_t value) {
TheStructure.Common.Cr_VCb_UPixelOffsetVDirectionMsb = value;
}
inline uint32_t getCrVCbUPixelOffsetVDirectionMsb(void) const {
return (TheStructure.Common.Cr_VCb_UPixelOffsetVDirectionMsb);
}
inline void setCrVCbUPixelOffsetUDirection(const uint32_t value) {
TheStructure.Common.Cr_VCb_UPixelOffsetUDirection = value;
}
inline uint32_t getCrVCbUPixelOffsetUDirection(void) const {
return (TheStructure.Common.Cr_VCb_UPixelOffsetUDirection);
}
inline void setInterleaveChroma(const bool value) {
TheStructure.Common.InterleaveChroma = value;
}
inline bool getInterleaveChroma(void) const {
return (TheStructure.Common.InterleaveChroma);
}
inline void setSurfaceFormat(const SURFACE_FORMAT value) {
TheStructure.Common.SurfaceFormat = value;
}
inline SURFACE_FORMAT getSurfaceFormat(void) const {
return static_cast<SURFACE_FORMAT>(TheStructure.Common.SurfaceFormat);
}
inline void setYOffsetForUCb(const uint32_t value) {
TheStructure.Common.YOffsetForU_Cb = value;
}
inline uint32_t getYOffsetForUCb(void) const {
return (TheStructure.Common.YOffsetForU_Cb);
}
inline void setXOffsetForUCb(const uint32_t value) {
TheStructure.Common.XOffsetForU_Cb = value;
}
inline uint32_t getXOffsetForUCb(void) const {
return (TheStructure.Common.XOffsetForU_Cb);
}
inline void setSurfaceMemoryObjectControlStateReserved(const uint32_t value) {
TheStructure.Common.SurfaceMemoryObjectControlState_Reserved = value;
}
inline uint32_t getSurfaceMemoryObjectControlStateReserved(void) const {
return (TheStructure.Common.SurfaceMemoryObjectControlState_Reserved);
}
inline void setSurfaceMemoryObjectControlStateIndexToMocsTables(const uint32_t value) {
TheStructure.Common.SurfaceMemoryObjectControlState_IndexToMocsTables = value >> 1;
}
inline uint32_t getSurfaceMemoryObjectControlStateIndexToMocsTables(void) const {
return (TheStructure.Common.SurfaceMemoryObjectControlState_IndexToMocsTables << 1);
}
inline void setTiledResourceMode(const TILED_RESOURCE_MODE value) {
TheStructure.Common.TiledResourceMode = value;
}
inline TILED_RESOURCE_MODE getTiledResourceMode(void) const {
return static_cast<TILED_RESOURCE_MODE>(TheStructure.Common.TiledResourceMode);
}
inline void setDepth(const uint32_t value) {
TheStructure.Common.Depth = value;
}
inline uint32_t getDepth(void) const {
return (TheStructure.Common.Depth);
}
inline void setVerticalLineStrideOffset(const uint32_t value) {
TheStructure.Common.VerticalLineStrideOffset = value;
}
inline uint32_t getVerticalLineStrideOffset(void) const {
return (TheStructure.Common.VerticalLineStrideOffset);
}
inline void setVerticalLineStride(const uint32_t value) {
TheStructure.Common.VerticalLineStride = value;
}
inline uint32_t getVerticalLineStride(void) const {
return (TheStructure.Common.VerticalLineStride);
}
inline void setSurfaceBaseAddress(const uint64_t value) {
TheStructure.Common.SurfaceBaseAddressLow = static_cast<uint32_t>(value & 0xffffffff);
TheStructure.Common.SurfaceBaseAddressHigh = (value >> 32) & 0xffffffff;
}
inline uint64_t getSurfaceBaseAddress(void) const {
return (TheStructure.Common.SurfaceBaseAddressLow |
static_cast<uint64_t>(TheStructure.Common.SurfaceBaseAddressHigh) << 32);
}
inline void setSurfaceBaseAddressHigh(const uint32_t value) {
TheStructure.Common.SurfaceBaseAddressHigh = value;
}
inline uint32_t getSurfaceBaseAddressHigh(void) const {
return (TheStructure.Common.SurfaceBaseAddressHigh);
}
typedef enum tagYOFFSET {
YOFFSET_BIT_SHIFT = 0x2,
YOFFSET_ALIGN_SIZE = 0x4,
} YOFFSET;
inline void setYOffset(const uint32_t value) {
TheStructure.SurfaceFormatIsOneOfPlanarFormats.YOffset = value >> YOFFSET_BIT_SHIFT;
}
inline uint32_t getYOffset(void) const {
return (TheStructure.SurfaceFormatIsOneOfPlanarFormats.YOffset << YOFFSET_BIT_SHIFT);
}
typedef enum tagXOFFSET {
XOFFSET_BIT_SHIFT = 0x2,
XOFFSET_ALIGN_SIZE = 0x4,
} XOFFSET;
inline void setXOffset(const uint32_t value) {
TheStructure.SurfaceFormatIsOneOfPlanarFormats.XOffset = value >> XOFFSET_BIT_SHIFT;
}
inline uint32_t getXOffset(void) const {
return (TheStructure.SurfaceFormatIsOneOfPlanarFormats.XOffset << XOFFSET_BIT_SHIFT);
}
inline void setYOffsetForVCr(const uint32_t value) {
TheStructure._SurfaceFormatIsOneOfPlanarAnd_InterleaveChromaIs0.YOffsetForV_Cr = value;
}
inline uint32_t getYOffsetForVCr(void) const {
return (TheStructure._SurfaceFormatIsOneOfPlanarAnd_InterleaveChromaIs0.YOffsetForV_Cr);
}
inline void setXOffsetForVCr(const uint32_t value) {
TheStructure._SurfaceFormatIsOneOfPlanarAnd_InterleaveChromaIs0.XOffsetForV_Cr = value;
}
inline uint32_t getXOffsetForVCr(void) const {
return (TheStructure._SurfaceFormatIsOneOfPlanarAnd_InterleaveChromaIs0.XOffsetForV_Cr);
}
} MEDIA_SURFACE_STATE;
STATIC_ASSERT(32 == sizeof(MEDIA_SURFACE_STATE));
typedef struct tagMI_MATH {
union _DW0 {
struct _BitField {
uint32_t DwordLength : BITFIELD_RANGE(0, 5);
uint32_t Reserved : BITFIELD_RANGE(6, 22);
uint32_t InstructionOpcode : BITFIELD_RANGE(23, 28);
uint32_t InstructionType : BITFIELD_RANGE(29, 31);
} BitField;
uint32_t Value;
} DW0;
typedef enum tagMI_COMMAND_OPCODE {
MI_COMMAND_OPCODE_MI_MATH = 0x1A,
} MI_COMMAND_OPCODE;
typedef enum tagCOMMAND_TYPE {
COMMAND_TYPE_MI_COMMAND = 0x0,
} COMMAND_TYPE;
} MI_MATH;
typedef struct tagMI_MATH_ALU_INST_INLINE {
union _DW0 {
struct _BitField {
uint32_t Operand2 : BITFIELD_RANGE(0, 9);
uint32_t Operand1 : BITFIELD_RANGE(10, 19);
uint32_t ALUOpcode : BITFIELD_RANGE(20, 31);
} BitField;
uint32_t Value;
} DW0;
} MI_MATH_ALU_INST_INLINE;
typedef struct tagMI_SEMAPHORE_WAIT {
union tagTheStructure {
struct tagCommon {
uint32_t DwordLength : BITFIELD_RANGE(0, 7);
uint32_t Reserved_8 : BITFIELD_RANGE(8, 11);
uint32_t CompareOperation : BITFIELD_RANGE(12, 14);
uint32_t WaitMode : BITFIELD_RANGE(15, 15);
uint32_t RegisterPollMode : BITFIELD_RANGE(16, 16);
uint32_t Reserved_17 : BITFIELD_RANGE(17, 21);
uint32_t MemoryType : BITFIELD_RANGE(22, 22);
uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28);
uint32_t CommandType : BITFIELD_RANGE(29, 31);
uint32_t SemaphoreDataDword;
uint64_t Reserved_64 : BITFIELD_RANGE(0, 1);
uint64_t SemaphoreAddress_Graphicsaddress : BITFIELD_RANGE(2, 63);
} Common;
uint32_t RawData[4];
} TheStructure;
typedef enum tagDWORD_LENGTH {
DWORD_LENGTH_EXCLUDES_DWORD_0_1 = 0x2,
} DWORD_LENGTH;
typedef enum tagCOMPARE_OPERATION {
COMPARE_OPERATION_SAD_GREATER_THAN_SDD = 0x0,
COMPARE_OPERATION_SAD_GREATER_THAN_OR_EQUAL_SDD = 0x1,
COMPARE_OPERATION_SAD_LESS_THAN_SDD = 0x2,
COMPARE_OPERATION_SAD_LESS_THAN_OR_EQUAL_SDD = 0x3,
COMPARE_OPERATION_SAD_EQUAL_SDD = 0x4,
COMPARE_OPERATION_SAD_NOT_EQUAL_SDD = 0x5,
} COMPARE_OPERATION;
typedef enum tagWAIT_MODE {
WAIT_MODE_SIGNAL_MODE = 0x0,
WAIT_MODE_POLLING_MODE = 0x1,
} WAIT_MODE;
typedef enum tagREGISTER_POLL_MODE {
REGISTER_POLL_MODE_MEMORY_POLL = 0x0,
REGISTER_POLL_MODE_REGISTER_POLL = 0x1,
} REGISTER_POLL_MODE;
typedef enum tagMEMORY_TYPE {
MEMORY_TYPE_PER_PROCESS_GRAPHICS_ADDRESS = 0x0,
MEMORY_TYPE_GLOBAL_GRAPHICS_ADDRESS = 0x1,
} MEMORY_TYPE;
typedef enum tagMI_COMMAND_OPCODE {
MI_COMMAND_OPCODE_MI_SEMAPHORE_WAIT = 0x1c,
} MI_COMMAND_OPCODE;
typedef enum tagCOMMAND_TYPE {
COMMAND_TYPE_MI_COMMAND = 0x0,
} COMMAND_TYPE;
inline void init(void) {
memset(&TheStructure, 0, sizeof(TheStructure));
TheStructure.Common.DwordLength = DWORD_LENGTH_EXCLUDES_DWORD_0_1;
TheStructure.Common.CompareOperation = COMPARE_OPERATION_SAD_GREATER_THAN_SDD;
TheStructure.Common.WaitMode = WAIT_MODE_SIGNAL_MODE;
TheStructure.Common.RegisterPollMode = REGISTER_POLL_MODE_MEMORY_POLL;
TheStructure.Common.MemoryType = MEMORY_TYPE_PER_PROCESS_GRAPHICS_ADDRESS;
TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE_MI_SEMAPHORE_WAIT;
TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND;
}
static tagMI_SEMAPHORE_WAIT sInit(void) {
MI_SEMAPHORE_WAIT state;
state.init();
return state;
}
inline uint32_t &getRawData(const uint32_t index) {
DEBUG_BREAK_IF(index >= 4);
return TheStructure.RawData[index];
}
inline void setCompareOperation(const COMPARE_OPERATION value) {
TheStructure.Common.CompareOperation = value;
}
inline COMPARE_OPERATION getCompareOperation(void) const {
return static_cast<COMPARE_OPERATION>(TheStructure.Common.CompareOperation);
}
inline void setWaitMode(const WAIT_MODE value) {
TheStructure.Common.WaitMode = value;
}
inline WAIT_MODE getWaitMode(void) const {
return static_cast<WAIT_MODE>(TheStructure.Common.WaitMode);
}
inline void setRegisterPollMode(const REGISTER_POLL_MODE value) {
TheStructure.Common.RegisterPollMode = value;
}
inline REGISTER_POLL_MODE getRegisterPollMode(void) const {
return static_cast<REGISTER_POLL_MODE>(TheStructure.Common.RegisterPollMode);
}
inline void setMemoryType(const MEMORY_TYPE value) {
TheStructure.Common.MemoryType = value;
}
inline MEMORY_TYPE getMemoryType(void) const {
return static_cast<MEMORY_TYPE>(TheStructure.Common.MemoryType);
}
inline void setSemaphoreDataDword(const uint32_t value) {
TheStructure.Common.SemaphoreDataDword = value;
}
inline uint32_t getSemaphoreDataDword(void) const {
return (TheStructure.Common.SemaphoreDataDword);
}
typedef enum tagSEMAPHOREADDRESS_GRAPHICSADDRESS {
SEMAPHOREADDRESS_GRAPHICSADDRESS_BIT_SHIFT = 0x2,
SEMAPHOREADDRESS_GRAPHICSADDRESS_ALIGN_SIZE = 0x4,
} SEMAPHOREADDRESS_GRAPHICSADDRESS39_2;
inline void setSemaphoreGraphicsAddress(const uint64_t value) {
TheStructure.Common.SemaphoreAddress_Graphicsaddress = value >> SEMAPHOREADDRESS_GRAPHICSADDRESS_BIT_SHIFT;
}
inline uint64_t getSemaphoreGraphicsAddress(void) const {
return (TheStructure.Common.SemaphoreAddress_Graphicsaddress << SEMAPHOREADDRESS_GRAPHICSADDRESS_BIT_SHIFT);
}
typedef enum tagSEMAPHOREADDRESS_RESERVED {
SEMAPHOREADDRESS_RESERVED_BIT_SHIFT = 0x2,
SEMAPHOREADDRESS_RESERVED_ALIGN_SIZE = 0x4,
} SEMAPHOREADDRESS_RESERVED;
} MI_SEMAPHORE_WAIT;
STATIC_ASSERT(16 == sizeof(MI_SEMAPHORE_WAIT));
typedef struct tagMI_STORE_DATA_IMM {
union tagTheStructure {
struct tagCommon {
uint32_t DwordLength : BITFIELD_RANGE(0, 9);
uint32_t Reserved_10 : BITFIELD_RANGE(10, 20);
uint32_t StoreQword : BITFIELD_RANGE(21, 21);
uint32_t UseGlobalGtt : BITFIELD_RANGE(22, 22);
uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28);
uint32_t CommandType : BITFIELD_RANGE(29, 31);
uint64_t CoreModeEnable : BITFIELD_RANGE(0, 0);
uint64_t Reserved_33 : BITFIELD_RANGE(1, 1);
uint64_t Address_Graphicsaddress39_2 : BITFIELD_RANGE(2, 39);
uint64_t Address_Reserved : BITFIELD_RANGE(40, 63);
uint32_t DataDword0;
uint32_t DataDword1;
} Common;
uint32_t RawData[5];
} TheStructure;
typedef enum tagDWORD_LENGTH {
DWORD_LENGTH_STORE_DWORD = 0x2,
DWORD_LENGTH_STORE_QWORD = 0x3,
} DWORD_LENGTH;
typedef enum tagMI_COMMAND_OPCODE {
MI_COMMAND_OPCODE_MI_STORE_DATA_IMM = 0x20,
} MI_COMMAND_OPCODE;
typedef enum tagCOMMAND_TYPE {
COMMAND_TYPE_MI_COMMAND = 0x0,
} COMMAND_TYPE;
inline void init(void) {
memset(&TheStructure, 0, sizeof(TheStructure));
TheStructure.Common.DwordLength = DWORD_LENGTH_STORE_DWORD;
TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE_MI_STORE_DATA_IMM;
TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND;
}
static tagMI_STORE_DATA_IMM sInit(void) {
MI_STORE_DATA_IMM state;
state.init();
return state;
}
inline uint32_t &getRawData(const uint32_t index) {
DEBUG_BREAK_IF(index >= 5);
return TheStructure.RawData[index];
}
inline void setDwordLength(const DWORD_LENGTH value) {
TheStructure.Common.DwordLength = value;
}
inline DWORD_LENGTH getDwordLength(void) const {
return static_cast<DWORD_LENGTH>(TheStructure.Common.DwordLength);
}
inline void setStoreQword(const bool value) {
TheStructure.Common.StoreQword = value;
}
inline bool getStoreQword(void) const {
return (TheStructure.Common.StoreQword);
}
inline void setUseGlobalGtt(const bool value) {
TheStructure.Common.UseGlobalGtt = value;
}
inline bool getUseGlobalGtt(void) const {
return (TheStructure.Common.UseGlobalGtt);
}
inline void setCoreModeEnable(const uint64_t value) {
TheStructure.Common.CoreModeEnable = value;
}
inline uint64_t getCoreModeEnable(void) const {
return (TheStructure.Common.CoreModeEnable);
}
typedef enum tagADDRESS_GRAPHICSADDRESS39_2 {
ADDRESS_GRAPHICSADDRESS39_2_BIT_SHIFT = 0x2,
ADDRESS_GRAPHICSADDRESS39_2_ALIGN_SIZE = 0x4,
} ADDRESS_GRAPHICSADDRESS39_2;
inline void setAddress(const uint64_t value) {
TheStructure.Common.Address_Graphicsaddress39_2 = value >> ADDRESS_GRAPHICSADDRESS39_2_BIT_SHIFT;
}
inline uint64_t getAddress(void) const {
return (TheStructure.Common.Address_Graphicsaddress39_2 << ADDRESS_GRAPHICSADDRESS39_2_BIT_SHIFT);
}
typedef enum tagADDRESS_RESERVED {
ADDRESS_RESERVED_BIT_SHIFT = 0x2,
ADDRESS_RESERVED_ALIGN_SIZE = 0x4,
} ADDRESS_RESERVED;
inline void setAddressReserved(const uint64_t value) {
TheStructure.Common.Address_Reserved = value >> ADDRESS_RESERVED_BIT_SHIFT;
}
inline uint64_t getAddressReserved(void) const {
return (TheStructure.Common.Address_Reserved << ADDRESS_RESERVED_BIT_SHIFT);
}
inline void setDataDword0(const uint32_t value) {
TheStructure.Common.DataDword0 = value;
}
inline uint32_t getDataDword0(void) const {
return (TheStructure.Common.DataDword0);
}
inline void setDataDword1(const uint32_t value) {
TheStructure.Common.DataDword1 = value;
}
inline uint32_t getDataDword1(void) const {
return (TheStructure.Common.DataDword1);
}
} MI_STORE_DATA_IMM;
STATIC_ASSERT(20 == sizeof(MI_STORE_DATA_IMM));
typedef struct tagPWR_CLK_STATE_REGISTER {
typedef enum tagADDRESS {
REG_ADDRESS = 0x20C8
} ADDRESS;
union tagTheStructure {
struct tagCommon {
uint32_t EUmin : BITFIELD_RANGE(0, 3);
uint32_t EUmax : BITFIELD_RANGE(4, 7);
uint32_t SScount : BITFIELD_RANGE(8, 10);
uint32_t SSCountEn : BITFIELD_RANGE(11, 11);
uint32_t SliceCountRequest : BITFIELD_RANGE(12, 17);
uint32_t EnableSliceCountRequest : BITFIELD_RANGE(18, 18);
uint32_t Reserved : BITFIELD_RANGE(19, 30);
uint32_t EnablePwrClockGating : BITFIELD_RANGE(31, 31);
} Common;
uint32_t RawData[1];
} TheStructure;
inline void init(void) {
TheStructure.RawData[0] = 0;
TheStructure.Common.EnablePwrClockGating = 1;
TheStructure.Common.EUmin = 8;
TheStructure.Common.EUmax = 8;
}
static tagPWR_CLK_STATE_REGISTER sInit(void) {
PWR_CLK_STATE_REGISTER state;
state.init();
return state;
}
} PWR_CLK_STATE_REGISTER;
STATIC_ASSERT(4 == sizeof(PWR_CLK_STATE_REGISTER));
typedef struct tagASYNC_SLICE_COUNT_SELECT_REGISTER {
typedef enum tagADDRESS {
REG_ADDRESS = 0xA204
} ADDRESS;
union tagTheStructure {
struct tagCommon {
uint32_t AsyncSliceCount : BITFIELD_RANGE(0, 3);
uint32_t AsyncEuCount : BITFIELD_RANGE(4, 7);
uint32_t AsyncSubSliceCount : BITFIELD_RANGE(8, 10);
uint32_t Reserved : BITFIELD_RANGE(11, 31);
} Common;
uint32_t RawData[1];
} TheStructure;
inline void init(void) {
TheStructure.RawData[0] = 0;
TheStructure.Common.AsyncSliceCount = 2;
TheStructure.Common.AsyncSubSliceCount = 4;
TheStructure.Common.AsyncEuCount = 8;
}
static tagASYNC_SLICE_COUNT_SELECT_REGISTER sInit(void) {
ASYNC_SLICE_COUNT_SELECT_REGISTER state;
state.init();
return state;
}
} ASYNC_SLICE_COUNT_SELECT_REGISTER;
STATIC_ASSERT(4 == sizeof(ASYNC_SLICE_COUNT_SELECT_REGISTER));
#pragma pack()

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runtime/gen11/hw_cmds_icllp.h Normal file
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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "runtime/gen11/hw_cmds_base.h"
namespace NEO {
struct ICLLP : public ICLFamily {
static const PLATFORM platform;
static const HardwareInfo hwInfo;
static const uint32_t threadsPerEu = 7;
static const uint32_t maxEuPerSubslice = 8;
static const uint32_t maxSlicesSupported = 1;
static const uint32_t maxSubslicesSupported = 8;
static const RuntimeCapabilityTable capabilityTable;
static void (*setupHardwareInfo)(GT_SYSTEM_INFO *gtSysInfo, FeatureTable *featureTable, bool setupFeatureTable, const std::string &hwInfoConfig);
};
class ICLLP_1x8x8 : public ICLLP {
public:
static void setupHardwareInfo(GT_SYSTEM_INFO *gtSysInfo, FeatureTable *featureTable, bool setupFeatureTable);
static const HardwareInfo hwInfo;
private:
static GT_SYSTEM_INFO gtSystemInfo;
};
class ICLLP_1x4x8 : public ICLLP {
public:
static void setupHardwareInfo(GT_SYSTEM_INFO *gtSysInfo, FeatureTable *featureTable, bool setupFeatureTable);
static const HardwareInfo hwInfo;
private:
static GT_SYSTEM_INFO gtSystemInfo;
};
class ICLLP_1x6x8 : public ICLLP {
public:
static void setupHardwareInfo(GT_SYSTEM_INFO *gtSysInfo, FeatureTable *featureTable, bool setupFeatureTable);
static const HardwareInfo hwInfo;
private:
static GT_SYSTEM_INFO gtSystemInfo;
};
class ICLLP_1x1x8 : public ICLLP {
public:
static void setupHardwareInfo(GT_SYSTEM_INFO *gtSysInfo, FeatureTable *featureTable, bool setupFeatureTable);
static const HardwareInfo hwInfo;
private:
static GT_SYSTEM_INFO gtSystemInfo;
};
} // namespace NEO

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "runtime/gen11/hw_cmds_base.h"
namespace NEO {
struct LKF : public ICLFamily {
static const PLATFORM platform;
static const HardwareInfo hwInfo;
static const uint32_t threadsPerEu = 7;
static const uint32_t maxEuPerSubslice = 8;
static const uint32_t maxSlicesSupported = 1;
static const uint32_t maxSubslicesSupported = 8;
static const RuntimeCapabilityTable capabilityTable;
static void (*setupHardwareInfo)(GT_SYSTEM_INFO *gtSysInfo, FeatureTable *featureTable, bool setupFeatureTable, const std::string &hwInfoConfig);
};
class LKF_1x8x8 : public LKF {
public:
static void setupHardwareInfo(GT_SYSTEM_INFO *gtSysInfo, FeatureTable *featureTable, bool setupFeatureTable);
static const HardwareInfo hwInfo;
private:
static GT_SYSTEM_INFO gtSystemInfo;
};
} // namespace NEO

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/aub/aub_helper.h"
#include "runtime/aub/aub_helper.inl"
#include "runtime/helpers/flat_batch_buffer_helper_hw.inl"
#include "runtime/helpers/hw_helper.h"
#include "runtime/helpers/hw_helper_common.inl"
namespace NEO {
typedef ICLFamily Family;
template <>
uint32_t HwHelperHw<Family>::getComputeUnitsUsedForScratch(const HardwareInfo *pHwInfo) const {
return pHwInfo->pSysInfo->MaxSubSlicesSupported * pHwInfo->pSysInfo->MaxEuPerSubSlice * 8;
}
template class AubHelperHw<Family>;
template class HwHelperHw<Family>;
template class FlatBatchBufferHelperHw<Family>;
template struct PipeControlHelper<Family>;
} // namespace NEO

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#ifdef SUPPORT_ICLLP
#include "hw_info_icllp.h"
#endif
#ifdef SUPPORT_LKF
#include "hw_info_lkf.h"
#endif

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#ifdef SUPPORT_ICLLP
#include "hw_info_icllp.inl"
#endif
#ifdef SUPPORT_LKF
#include "hw_info_lkf.inl"
#endif
namespace NEO {
const char *GfxFamilyMapper<IGFX_GEN11_CORE>::name = "Gen11";
} // namespace NEO

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "runtime/helpers/hw_info.h"
namespace NEO {
struct ICLFamily;
template <>
struct GfxFamilyMapper<IGFX_GEN11_CORE> {
typedef ICLFamily GfxFamily;
static const char *name;
};
} // namespace NEO

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "hw_info_gen11.h"
namespace NEO {
struct ICLLP;
template <>
struct HwMapper<IGFX_ICELAKE_LP> {
enum { gfxFamily = IGFX_GEN11_CORE };
static const char *abbreviation;
typedef GfxFamilyMapper<static_cast<GFXCORE_FAMILY>(gfxFamily)>::GfxFamily GfxFamily;
typedef ICLLP GfxProduct;
};
} // namespace NEO

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/aub_mem_dump/aub_services.h"
#include "runtime/memory_manager/memory_constants.h"
#include "engine_node.h"
#include "hw_cmds.h"
#include "hw_info_icllp.h"
namespace NEO {
const char *HwMapper<IGFX_ICELAKE_LP>::abbreviation = "icllp";
bool isSimulationICLLP(unsigned short deviceId) {
switch (deviceId) {
case IICL_LP_GT1_MOB_DEVICE_F0_ID:
return true;
}
return false;
};
const PLATFORM ICLLP::platform = {
IGFX_ICELAKE_LP,
PCH_UNKNOWN,
IGFX_GEN11_CORE,
IGFX_GEN11_CORE,
PLATFORM_NONE, // default init
0, // usDeviceID
0, // usRevId. 0 sets the stepping to A0
0, // usDeviceID_PCH
0, // usRevId_PCH
GTTYPE_UNDEFINED};
const RuntimeCapabilityTable ICLLP::capabilityTable{
{0, 0, 0, false, false, false}, // kmdNotifyProperties
{true, false}, // whitelistedRegisters
MemoryConstants::max48BitAddress, // gpuAddressSpace
83.333, // defaultProfilingTimerResolution
MemoryConstants::pageSize, // requiredPreemptionSurfaceSize
&isSimulationICLLP, // isSimulation
PreemptionMode::MidThread, // defaultPreemptionMode
aub_stream::ENGINE_RCS, // defaultEngineType
0, // maxRenderFrequency
21, // clVersionSupport
CmdServicesMemTraceVersion::DeviceValues::Icllp, // aubDeviceId
1, // extraQuantityThreadsPerEU
64, // slmSize
false, // ftrSupportsFP64
false, // ftrSupports64BitMath
true, // ftrSvm
true, // ftrSupportsCoherency
true, // ftrSupportsVmeAvcTextureSampler
true, // ftrSupportsVmeAvcPreemption
false, // ftrRenderCompressedBuffers
false, // ftrRenderCompressedImages
false, // ftr64KBpages
true, // instrumentationEnabled
true, // forceStatelessCompilationFor32Bit
false, // isCore
true, // sourceLevelDebuggerSupported
true, // supportsVme
false // supportCacheFlushAfterWalker
};
const HardwareInfo ICLLP_1x8x8::hwInfo = {
&ICLLP::platform,
&emptySkuTable,
&emptyWaTable,
&ICLLP_1x8x8::gtSystemInfo,
ICLLP::capabilityTable,
};
GT_SYSTEM_INFO ICLLP_1x8x8::gtSystemInfo = {0};
void ICLLP_1x8x8::setupHardwareInfo(GT_SYSTEM_INFO *gtSysInfo, FeatureTable *featureTable, bool setupFeatureTable) {
gtSysInfo->EUCount = 63;
gtSysInfo->ThreadCount = 63 * ICLLP::threadsPerEu;
gtSysInfo->SliceCount = 1;
gtSysInfo->SubSliceCount = 8;
gtSysInfo->L3CacheSizeInKb = 3072;
gtSysInfo->L3BankCount = 8;
gtSysInfo->MaxFillRate = 16;
gtSysInfo->TotalVsThreads = 336;
gtSysInfo->TotalHsThreads = 336;
gtSysInfo->TotalDsThreads = 336;
gtSysInfo->TotalGsThreads = 336;
gtSysInfo->TotalPsThreadsWindowerRange = 64;
gtSysInfo->CsrSizeInMb = 8;
gtSysInfo->MaxEuPerSubSlice = ICLLP::maxEuPerSubslice;
gtSysInfo->MaxSlicesSupported = ICLLP::maxSlicesSupported;
gtSysInfo->MaxSubSlicesSupported = ICLLP::maxSubslicesSupported;
gtSysInfo->IsL3HashModeEnabled = false;
gtSysInfo->IsDynamicallyPopulated = false;
};
const HardwareInfo ICLLP_1x4x8::hwInfo = {
&ICLLP::platform,
&emptySkuTable,
&emptyWaTable,
&ICLLP_1x4x8::gtSystemInfo,
ICLLP::capabilityTable,
};
GT_SYSTEM_INFO ICLLP_1x4x8::gtSystemInfo = {0};
void ICLLP_1x4x8::setupHardwareInfo(GT_SYSTEM_INFO *gtSysInfo, FeatureTable *featureTable, bool setupFeatureTable) {
gtSysInfo->EUCount = 31;
gtSysInfo->ThreadCount = 31 * ICLLP::threadsPerEu;
gtSysInfo->SliceCount = 1;
gtSysInfo->SubSliceCount = 4;
gtSysInfo->L3CacheSizeInKb = 2304;
gtSysInfo->L3BankCount = 6;
gtSysInfo->MaxFillRate = 8;
gtSysInfo->TotalVsThreads = 364;
gtSysInfo->TotalHsThreads = 224;
gtSysInfo->TotalDsThreads = 364;
gtSysInfo->TotalGsThreads = 224;
gtSysInfo->TotalPsThreadsWindowerRange = 128;
gtSysInfo->CsrSizeInMb = 5;
gtSysInfo->MaxEuPerSubSlice = ICLLP::maxEuPerSubslice;
gtSysInfo->MaxSlicesSupported = 1;
gtSysInfo->MaxSubSlicesSupported = 4;
gtSysInfo->IsL3HashModeEnabled = false;
gtSysInfo->IsDynamicallyPopulated = false;
};
const HardwareInfo ICLLP_1x6x8::hwInfo = {
&ICLLP::platform,
&emptySkuTable,
&emptyWaTable,
&ICLLP_1x6x8::gtSystemInfo,
ICLLP::capabilityTable,
};
GT_SYSTEM_INFO ICLLP_1x6x8::gtSystemInfo = {0};
void ICLLP_1x6x8::setupHardwareInfo(GT_SYSTEM_INFO *gtSysInfo, FeatureTable *featureTable, bool setupFeatureTable) {
gtSysInfo->EUCount = 47;
gtSysInfo->ThreadCount = 47 * ICLLP::threadsPerEu;
gtSysInfo->SliceCount = 1;
gtSysInfo->SubSliceCount = 6;
gtSysInfo->L3CacheSizeInKb = 2304;
gtSysInfo->L3BankCount = 6;
gtSysInfo->MaxFillRate = 8;
gtSysInfo->TotalVsThreads = 364;
gtSysInfo->TotalHsThreads = 224;
gtSysInfo->TotalDsThreads = 364;
gtSysInfo->TotalGsThreads = 224;
gtSysInfo->TotalPsThreadsWindowerRange = 128;
gtSysInfo->CsrSizeInMb = 5;
gtSysInfo->MaxEuPerSubSlice = ICLLP::maxEuPerSubslice;
gtSysInfo->MaxSlicesSupported = 1;
gtSysInfo->MaxSubSlicesSupported = 4;
gtSysInfo->IsL3HashModeEnabled = false;
gtSysInfo->IsDynamicallyPopulated = false;
};
const HardwareInfo ICLLP_1x1x8::hwInfo = {
&ICLLP::platform,
&emptySkuTable,
&emptyWaTable,
&ICLLP_1x1x8::gtSystemInfo,
ICLLP::capabilityTable,
};
GT_SYSTEM_INFO ICLLP_1x1x8::gtSystemInfo = {0};
void ICLLP_1x1x8::setupHardwareInfo(GT_SYSTEM_INFO *gtSysInfo, FeatureTable *featureTable, bool setupFeatureTable) {
gtSysInfo->EUCount = 8;
gtSysInfo->ThreadCount = 8 * ICLLP::threadsPerEu;
gtSysInfo->SliceCount = 1;
gtSysInfo->SubSliceCount = 1;
gtSysInfo->L3CacheSizeInKb = 2304;
gtSysInfo->L3BankCount = 6;
gtSysInfo->MaxFillRate = 8;
gtSysInfo->TotalVsThreads = 364;
gtSysInfo->TotalHsThreads = 224;
gtSysInfo->TotalDsThreads = 364;
gtSysInfo->TotalGsThreads = 224;
gtSysInfo->TotalPsThreadsWindowerRange = 128;
gtSysInfo->CsrSizeInMb = 5;
gtSysInfo->MaxEuPerSubSlice = ICLLP::maxEuPerSubslice;
gtSysInfo->MaxSlicesSupported = 1;
gtSysInfo->MaxSubSlicesSupported = 4;
gtSysInfo->IsL3HashModeEnabled = false;
gtSysInfo->IsDynamicallyPopulated = false;
};
const HardwareInfo ICLLP::hwInfo = ICLLP_1x8x8::hwInfo;
void setupICLLPHardwareInfoImpl(GT_SYSTEM_INFO *gtSysInfo, FeatureTable *featureTable, bool setupFeatureTable, const std::string &hwInfoConfig) {
if (hwInfoConfig == "1x8x8") {
ICLLP_1x8x8::setupHardwareInfo(gtSysInfo, featureTable, setupFeatureTable);
} else if (hwInfoConfig == "1x4x8") {
ICLLP_1x4x8::setupHardwareInfo(gtSysInfo, featureTable, setupFeatureTable);
} else if (hwInfoConfig == "1x6x8") {
ICLLP_1x6x8::setupHardwareInfo(gtSysInfo, featureTable, setupFeatureTable);
} else if (hwInfoConfig == "1x1x8") {
ICLLP_1x1x8::setupHardwareInfo(gtSysInfo, featureTable, setupFeatureTable);
} else if (hwInfoConfig == "default") {
// Default config
ICLLP_1x8x8::setupHardwareInfo(gtSysInfo, featureTable, setupFeatureTable);
} else {
UNRECOVERABLE_IF(true);
}
} // namespace NEO
void (*ICLLP::setupHardwareInfo)(GT_SYSTEM_INFO *, FeatureTable *, bool, const std::string &) = setupICLLPHardwareInfoImpl;
} // namespace NEO

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "hw_info_gen11.h"
namespace NEO {
struct LKF;
template <>
struct HwMapper<IGFX_LAKEFIELD> {
enum { gfxFamily = IGFX_GEN11_CORE };
static const char *abbreviation;
typedef GfxFamilyMapper<static_cast<GFXCORE_FAMILY>(gfxFamily)>::GfxFamily GfxFamily;
typedef LKF GfxProduct;
};
} // namespace NEO

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/aub_mem_dump/aub_services.h"
#include "runtime/memory_manager/memory_constants.h"
#include "engine_node.h"
#include "hw_cmds_lkf.h"
#include "hw_info_lkf.h"
namespace NEO {
const char *HwMapper<IGFX_LAKEFIELD>::abbreviation = "lkf";
bool isSimulationLKF(unsigned short deviceId) {
switch (deviceId) {
case ILKF_1x8x8_DESK_DEVICE_F0_ID:
return true;
}
return false;
};
const PLATFORM LKF::platform = {
IGFX_LAKEFIELD,
PCH_UNKNOWN,
IGFX_GEN11_CORE,
IGFX_GEN11_CORE,
PLATFORM_NONE, // default init
0, // usDeviceID
0, // usRevId. 0 sets the stepping to A0
0, // usDeviceID_PCH
0, // usRevId_PCH
GTTYPE_UNDEFINED};
const RuntimeCapabilityTable LKF::capabilityTable{
{0, 0, 0, false, false, false}, // kmdNotifyProperties
{true, false}, // whitelistedRegisters
MemoryConstants::max36BitAddress, // gpuAddressSpace
83.333, // defaultProfilingTimerResolution
MemoryConstants::pageSize, // requiredPreemptionSurfaceSize
&isSimulationLKF, // isSimulation
PreemptionMode::MidThread, // defaultPreemptionMode
aub_stream::ENGINE_RCS, // defaultEngineType
0, // maxRenderFrequency
12, // clVersionSupport
CmdServicesMemTraceVersion::DeviceValues::Lkf, // aubDeviceId
1, // extraQuantityThreadsPerEU
64, // slmSize
false, // ftrSupportsFP64
false, // ftrSupports64BitMath
false, // ftrSvm
true, // ftrSupportsCoherency
true, // ftrSupportsVmeAvcTextureSampler
true, // ftrSupportsVmeAvcPreemption
false, // ftrRenderCompressedBuffers
false, // ftrRenderCompressedImages
true, // ftr64KBpages
true, // instrumentationEnabled
true, // forceStatelessCompilationFor32Bit
false, // isCore
true, // sourceLevelDebuggerSupported
false, // supportsVme
false // supportCacheFlushAfterWalker
};
const HardwareInfo LKF_1x8x8::hwInfo = {
&LKF::platform,
&emptySkuTable,
&emptyWaTable,
&LKF_1x8x8::gtSystemInfo,
LKF::capabilityTable,
};
GT_SYSTEM_INFO LKF_1x8x8::gtSystemInfo = {0};
void LKF_1x8x8::setupHardwareInfo(GT_SYSTEM_INFO *gtSysInfo, FeatureTable *featureTable, bool setupFeatureTable) {
gtSysInfo->EUCount = 64;
gtSysInfo->ThreadCount = 64 * LKF::threadsPerEu;
gtSysInfo->SliceCount = 1;
gtSysInfo->SubSliceCount = 8;
gtSysInfo->L3CacheSizeInKb = 2560;
gtSysInfo->L3BankCount = 8;
gtSysInfo->MaxFillRate = 16;
gtSysInfo->TotalVsThreads = 448;
gtSysInfo->TotalHsThreads = 448;
gtSysInfo->TotalDsThreads = 448;
gtSysInfo->TotalGsThreads = 448;
gtSysInfo->TotalPsThreadsWindowerRange = 64;
gtSysInfo->CsrSizeInMb = 8;
gtSysInfo->MaxEuPerSubSlice = LKF::maxEuPerSubslice;
gtSysInfo->MaxSlicesSupported = LKF::maxSlicesSupported;
gtSysInfo->MaxSubSlicesSupported = LKF::maxSubslicesSupported;
gtSysInfo->IsL3HashModeEnabled = false;
gtSysInfo->IsDynamicallyPopulated = false;
};
const HardwareInfo LKF::hwInfo = LKF_1x8x8::hwInfo;
void setupLKFHardwareInfoImpl(GT_SYSTEM_INFO *gtSysInfo, FeatureTable *featureTable, bool setupFeatureTable, const std::string &hwInfoConfig) {
if (hwInfoConfig == "1x8x8") {
LKF_1x8x8::setupHardwareInfo(gtSysInfo, featureTable, setupFeatureTable);
} else if (hwInfoConfig == "default") {
// Default config
LKF_1x8x8::setupHardwareInfo(gtSysInfo, featureTable, setupFeatureTable);
} else {
UNRECOVERABLE_IF(true);
}
} // namespace NEO
void (*LKF::setupHardwareInfo)(GT_SYSTEM_INFO *, FeatureTable *, bool, const std::string &) = setupLKFHardwareInfoImpl;
} // namespace NEO

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/gen11/hw_cmds_base.h"
#include "runtime/mem_obj/image.h"
#include "runtime/mem_obj/image.inl"
#include "runtime/mem_obj/image_base.inl"
#include <map>
namespace NEO {
typedef ICLFamily Family;
static auto gfxCore = IGFX_GEN11_CORE;
template <typename GfxFamily>
void ImageHw<GfxFamily>::setMediaSurfaceRotation(void *memory) {
using MEDIA_SURFACE_STATE = typename GfxFamily::MEDIA_SURFACE_STATE;
using SURFACE_FORMAT = typename MEDIA_SURFACE_STATE::SURFACE_FORMAT;
auto surfaceState = reinterpret_cast<MEDIA_SURFACE_STATE *>(memory);
surfaceState->setRotation(MEDIA_SURFACE_STATE::ROTATION_NO_ROTATION_OR_0_DEGREE);
surfaceState->setXOffset(0);
surfaceState->setYOffset(0);
}
template <typename GfxFamily>
void ImageHw<GfxFamily>::setSurfaceMemoryObjectControlStateIndexToMocsTable(void *memory, uint32_t value) {
using MEDIA_SURFACE_STATE = typename GfxFamily::MEDIA_SURFACE_STATE;
using SURFACE_FORMAT = typename MEDIA_SURFACE_STATE::SURFACE_FORMAT;
auto surfaceState = reinterpret_cast<MEDIA_SURFACE_STATE *>(memory);
surfaceState->setSurfaceMemoryObjectControlStateIndexToMocsTables(value);
}
template <>
void ImageHw<Family>::appendSurfaceStateParams(RENDER_SURFACE_STATE *surfaceState) {
if (hasAlphaChannel(&imageFormat)) {
surfaceState->setSampleTapDiscardDisable(RENDER_SURFACE_STATE::SAMPLE_TAP_DISCARD_DISABLE_ENABLE);
}
}
#include "runtime/mem_obj/image_factory_init.inl"
} // namespace NEO

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/helpers/kernel_commands.h"
#include "runtime/helpers/kernel_commands.inl"
#include "runtime/helpers/kernel_commands_base.inl"
#include "runtime/os_interface/debug_settings_manager.h"
#include "hw_cmds.h"
namespace NEO {
template <>
bool KernelCommandsHelper<ICLFamily>::doBindingTablePrefetch() {
return false;
}
template struct KernelCommandsHelper<ICLFamily>;
} // namespace NEO

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/command_stream/command_stream_receiver_with_aub_dump.inl"
#include "runtime/os_interface/linux/device_command_stream.inl"
#include "runtime/os_interface/linux/drm_command_stream.inl"
namespace NEO {
template class DeviceCommandStreamReceiver<ICLFamily>;
template class DrmCommandStreamReceiver<ICLFamily>;
template class CommandStreamReceiverWithAUBDump<DrmCommandStreamReceiver<ICLFamily>>;
} // namespace NEO

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/os_interface/hw_info_config.inl"
#ifdef SUPPORT_ICLLP
#include "hw_info_config_icllp.inl"
#endif
#ifdef SUPPORT_LKF
#include "hw_info_config_lkf.inl"
#endif

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/helpers/hw_info.h"
#include "runtime/os_interface/hw_info_config.h"
namespace NEO {
template <>
int HwInfoConfigHw<IGFX_ICELAKE_LP>::configureHardwareCustom(HardwareInfo *hwInfo, OSInterface *osIface) {
FeatureTable *pSkuTable = const_cast<FeatureTable *>(hwInfo->pSkuTable);
GT_SYSTEM_INFO *pSysInfo = const_cast<GT_SYSTEM_INFO *>(hwInfo->pSysInfo);
WorkaroundTable *pWaTable = const_cast<WorkaroundTable *>(hwInfo->pWaTable);
pSysInfo->SliceCount = 1;
pSkuTable->ftrPPGTT = true;
pSkuTable->ftrSVM = true;
pSkuTable->ftrL3IACoherency = true;
pSkuTable->ftrIA32eGfxPTEs = true;
pSkuTable->ftrStandardMipTailFormat = true;
pSkuTable->ftrDisplayYTiling = true;
pSkuTable->ftrTranslationTable = true;
pSkuTable->ftrUserModeTranslationTable = true;
pSkuTable->ftrTileMappedResource = true;
pSkuTable->ftrEnableGuC = true;
pSkuTable->ftrFbc = true;
pSkuTable->ftrFbc2AddressTranslation = true;
pSkuTable->ftrFbcBlitterTracking = true;
pSkuTable->ftrFbcCpuTracking = true;
pSkuTable->ftrTileY = true;
pSkuTable->ftrAstcHdr2D = true;
pSkuTable->ftrAstcLdr2D = true;
pWaTable->wa4kAlignUVOffsetNV12LinearSurface = true;
pWaTable->waReportPerfCountUseGlobalContextID = true;
return 0;
}
template class HwInfoConfigHw<IGFX_ICELAKE_LP>;
} // namespace NEO

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/helpers/hw_info.h"
#include "runtime/os_interface/hw_info_config.h"
namespace NEO {
template <>
int HwInfoConfigHw<IGFX_LAKEFIELD>::configureHardwareCustom(HardwareInfo *hwInfo, OSInterface *osIface) {
FeatureTable *pSkuTable = const_cast<FeatureTable *>(hwInfo->pSkuTable);
GT_SYSTEM_INFO *pSysInfo = const_cast<GT_SYSTEM_INFO *>(hwInfo->pSysInfo);
WorkaroundTable *pWaTable = const_cast<WorkaroundTable *>(hwInfo->pWaTable);
pSysInfo->SliceCount = 1;
pSkuTable->ftrPPGTT = true;
pSkuTable->ftrSVM = true;
pSkuTable->ftrL3IACoherency = true;
pSkuTable->ftrIA32eGfxPTEs = true;
pSkuTable->ftrStandardMipTailFormat = true;
pSkuTable->ftrDisplayYTiling = true;
pSkuTable->ftrTranslationTable = true;
pSkuTable->ftrUserModeTranslationTable = true;
pSkuTable->ftrTileMappedResource = true;
pSkuTable->ftrEnableGuC = true;
pSkuTable->ftrFbc = true;
pSkuTable->ftrFbc2AddressTranslation = true;
pSkuTable->ftrFbcBlitterTracking = true;
pSkuTable->ftrFbcCpuTracking = true;
pSkuTable->ftrTileY = true;
pSkuTable->ftrAstcHdr2D = true;
pSkuTable->ftrAstcLdr2D = true;
pWaTable->wa4kAlignUVOffsetNV12LinearSurface = true;
pWaTable->waReportPerfCountUseGlobalContextID = true;
return 0;
}
template class HwInfoConfigHw<IGFX_LAKEFIELD>;
} // namespace NEO

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/command_stream/csr_definitions.h"
#include "runtime/helpers/pipeline_select_helper.h"
#include "runtime/helpers/preamble.inl"
#include "reg_configs_common.h"
namespace NEO {
template <>
uint32_t PreambleHelper<ICLFamily>::getL3Config(const HardwareInfo &hwInfo, bool useSLM) {
uint32_t l3Config = 0;
switch (hwInfo.pPlatform->eProductFamily) {
case IGFX_ICELAKE_LP:
l3Config = getL3ConfigHelper<IGFX_ICELAKE_LP>(useSLM);
break;
default:
l3Config = getL3ConfigHelper<IGFX_ICELAKE_LP>(true);
}
return l3Config;
}
template <>
void PreambleHelper<ICLFamily>::programPipelineSelect(LinearStream *pCommandStream, const DispatchFlags &dispatchFlags) {
typedef typename ICLFamily::PIPELINE_SELECT PIPELINE_SELECT;
auto pCmd = (PIPELINE_SELECT *)pCommandStream->getSpace(sizeof(PIPELINE_SELECT));
*pCmd = ICLFamily::cmdInitPipelineSelect;
auto mask = pipelineSelectEnablePipelineSelectMaskBits | pipelineSelectMediaSamplerDopClockGateMaskBits | pipelineSelectMediaSamplerPowerClockGateMaskBits;
pCmd->setMaskBits(mask);
pCmd->setPipelineSelection(PIPELINE_SELECT::PIPELINE_SELECTION_GPGPU);
pCmd->setMediaSamplerDopClockGateEnable(!dispatchFlags.mediaSamplerRequired);
pCmd->setMediaSamplerPowerClockGateDisable(dispatchFlags.mediaSamplerRequired);
}
template <>
void PreambleHelper<ICLFamily>::addPipeControlBeforeVfeCmd(LinearStream *pCommandStream, const HardwareInfo *hwInfo) {
auto pipeControl = pCommandStream->getSpaceForCmd<PIPE_CONTROL>();
*pipeControl = ICLFamily::cmdInitPipeControl;
pipeControl->setCommandStreamerStallEnable(true);
if (hwInfo->pWaTable->waSendMIFLUSHBeforeVFE) {
pipeControl->setRenderTargetCacheFlushEnable(true);
pipeControl->setDepthCacheFlushEnable(true);
pipeControl->setDcFlushEnable(true);
}
}
template <>
uint32_t PreambleHelper<ICLFamily>::getDefaultThreadArbitrationPolicy() {
return ThreadArbitrationPolicy::RoundRobinAfterDependency;
}
template <>
void PreambleHelper<ICLFamily>::programThreadArbitration(LinearStream *pCommandStream, uint32_t requiredThreadArbitrationPolicy) {
UNRECOVERABLE_IF(requiredThreadArbitrationPolicy == ThreadArbitrationPolicy::NotPresent);
auto pipeControl = pCommandStream->getSpaceForCmd<PIPE_CONTROL>();
*pipeControl = ICLFamily::cmdInitPipeControl;
pipeControl->setCommandStreamerStallEnable(true);
auto pCmd = pCommandStream->getSpaceForCmd<MI_LOAD_REGISTER_IMM>();
*pCmd = ICLFamily::cmdInitLoadRegisterImm;
pCmd->setRegisterOffset(RowChickenReg4::address);
pCmd->setDataDword(RowChickenReg4::regDataForArbitrationPolicy[requiredThreadArbitrationPolicy]);
}
template <>
size_t PreambleHelper<ICLFamily>::getThreadArbitrationCommandsSize() {
return sizeof(MI_LOAD_REGISTER_IMM) + sizeof(PIPE_CONTROL);
}
template <>
size_t PreambleHelper<ICLFamily>::getAdditionalCommandsSize(const Device &device) {
size_t totalSize = PreemptionHelper::getRequiredPreambleSize<ICLFamily>(device);
totalSize += getKernelDebuggingCommandsSize(device.isSourceLevelDebuggerActive());
return totalSize;
}
template struct PreambleHelper<ICLFamily>;
} // namespace NEO

59
runtime/gen11/preemption_gen11.cpp Normal file
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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/command_stream/preemption.h"
#include "runtime/command_stream/preemption.inl"
#include "runtime/memory_manager/graphics_allocation.h"
namespace NEO {
typedef ICLFamily GfxFamily;
template <>
struct PreemptionConfig<GfxFamily> {
static constexpr uint32_t mmioAddress = 0x2580;
static constexpr uint32_t maskVal = (1 << 1) | (1 << 2);
static constexpr uint32_t maskShift = 16;
static constexpr uint32_t mask = maskVal << maskShift;
static constexpr uint32_t threadGroupVal = (1 << 1);
static constexpr uint32_t cmdLevelVal = (1 << 2);
static constexpr uint32_t midThreadVal = 0;
};
template <>
size_t PreemptionHelper::getPreemptionWaCsSize<GfxFamily>(const Device &device) {
return 0;
}
template <>
void PreemptionHelper::applyPreemptionWaCmdsBegin<GfxFamily>(LinearStream *pCommandStream, const Device &device) {
}
template <>
void PreemptionHelper::applyPreemptionWaCmdsEnd<GfxFamily>(LinearStream *pCommandStream, const Device &device) {
}
template void PreemptionHelper::programCmdStream<GfxFamily>(LinearStream &cmdStream,
PreemptionMode newPreemptionMode, PreemptionMode oldPreemptionMode,
GraphicsAllocation *preemptionCsr, Device &device);
template size_t PreemptionHelper::getRequiredPreambleSize<GfxFamily>(const Device &device);
template void PreemptionHelper::programCsrBaseAddress<GfxFamily>(LinearStream &preambleCmdStream, Device &device, const GraphicsAllocation *preemptionCsr);
template void PreemptionHelper::programStateSip<GfxFamily>(LinearStream &preambleCmdStream, Device &device);
template size_t PreemptionHelper::getRequiredStateSipCmdSize<GfxFamily>(const Device &device);
template size_t PreemptionHelper::getRequiredCmdStreamSize<GfxFamily>(PreemptionMode newPreemptionMode, PreemptionMode oldPreemptionMode);
template <>
void PreemptionHelper::programInterfaceDescriptorDataPreemption<GfxFamily>(INTERFACE_DESCRIPTOR_DATA<GfxFamily> *idd, PreemptionMode preemptionMode) {
using INTERFACE_DESCRIPTOR_DATA = typename GfxFamily::INTERFACE_DESCRIPTOR_DATA;
if (preemptionMode == PreemptionMode::MidThread) {
idd->setThreadPreemptionDisable(INTERFACE_DESCRIPTOR_DATA::THREAD_PREEMPTION_DISABLE_DISABLE);
} else {
idd->setThreadPreemptionDisable(INTERFACE_DESCRIPTOR_DATA::THREAD_PREEMPTION_DISABLE_ENABLE);
}
}
} // namespace NEO

41
runtime/gen11/reg_configs.h Normal file
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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "runtime/helpers/preamble.h"
namespace NEO {
struct ICLFamily;
template <>
struct L3CNTLREGConfig<IGFX_ICELAKE_LP> {
static const uint32_t valueForSLM = 0xA0000720u;
static const uint32_t valueForNoSLM = 0xA0000720u;
};
template <>
struct L3CNTLRegisterOffset<ICLFamily> {
static const uint32_t registerOffset = 0x7034;
};
namespace gen11HdcModeRegister {
const uint32_t address = 0xE5F4;
const uint32_t forceNonCoherentEnableBit = 4;
} // namespace gen11HdcModeRegister
namespace gen11PowerClockStateRegister {
const uint32_t address = 0x20C8;
const uint32_t minEuCountShift = 0;
const uint32_t maxEuCountShift = 4;
const uint32_t subSliceCountShift = 8;
const uint32_t sliceCountShift = 12;
const uint32_t vmeSliceCount = 1;
const uint32_t enabledValue = 0x80040800u;
const uint32_t disabledValue = 0x80040800u;
} // namespace gen11PowerClockStateRegister
} // namespace NEO

19
runtime/gen11/sampler_gen11.cpp Normal file
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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/sampler/sampler.h"
#include "runtime/sampler/sampler.inl"
#include "hw_cmds.h"
namespace NEO {
typedef ICLFamily Family;
static auto gfxCore = IGFX_GEN11_CORE;
#include "runtime/sampler/sampler_factory_init.inl"
} // namespace NEO

147
runtime/gen11/scheduler_definitions.h Normal file
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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#define SCHEDULER_COMPILATION_SIZE 8
#define SIZEOF_INTERFACE_DESCRIPTOR_DATA_G11 32
#define NUMBER_OF_INERFACE_DESCRIPTORS 64
#define IDT_BREAKDOWN (NUMBER_OF_INERFACE_DESCRIPTORS - 2)
#define MAX_WKG_SIZE 448
#define INTERFACE_DESCRIPTOR_TABLE_SIZE_G11 (NUMBER_OF_INERFACE_DESCRIPTORS * SIZEOF_INTERFACE_DESCRIPTOR_DATA_G11)
#define SIZEOF_COLOR_CALCULATOR_STATE_G11 0xC0
#define INTERFACE_DESCRIPTOR_TABLE_START_ADDRESS_G11 SIZEOF_COLOR_CALCULATOR_STATE_G11
#define OCLRT_SIZEOF_SAMPLER_STATE_G11 (16)
#define SIZEOF_COLOR_CALCULATOR_STATE SIZEOF_COLOR_CALCULATOR_STATE_G11
#define SIZEOF_INTERFACE_DESCRIPTOR_DATA SIZEOF_INTERFACE_DESCRIPTOR_DATA_G11
#define INTERFACE_DESCRIPTOR_TABLE_SIZE INTERFACE_DESCRIPTOR_TABLE_SIZE_G11
#define INTERFACE_DESCRIPTOR_TABLE_START_ADDRESS INTERFACE_DESCRIPTOR_TABLE_START_ADDRESS_G11
#define OCLRT_SIZEOF_SAMPLER_STATE OCLRT_SIZEOF_SAMPLER_STATE_G11
#define SECOND_LEVEL_BUFFER_SPACE_FOR_EACH_ENQUEUE (SECOND_LEVEL_BUFFER_SPACE_FOR_EACH_ENQUEUE_GEN11)
#define SECOND_LEVEL_BUFFER_NUMBER_OF_ENQUEUES (SECOND_LEVEL_BUFFER_NUMBER_OF_ENQUEUES_GEN11)
//#define OCLRT_MEDIA_VFE_STATE_OFFSET ( MEDIA_STATE_FLUSH_INITIAL_OFFSET + OCLRT_SIZEOF_MSFLUSH_DWORD )
#define OCLRT_MEDIA_VFE_STATE_OFFSET (0)
//address is QWORD in size and starts on DWORD 1
#define MEDIA_VFE_STATE_ADDRESS_OFFSET (OCLRT_MEDIA_VFE_STATE_OFFSET + 1)
// DWORD OFFSET
#define MEDIA_STATE_FLUSH_INITIAL_OFFSET 0
//bits 0-5 of 1st DWORD
#define MEDIA_STATE_FLUSH_INITIAL_INTERFACE_DESCRIPTOR_OFFSET (MEDIA_STATE_FLUSH_INITIAL_OFFSET + 1)
#define MI_ARB_CHECK_AFTER_MEDIA_STATE_FLUSH_INITIAL_OFFSET 0
#define MI_ATOMIC_CMD_OFFSET 0
#define MEDIA_INTERFACE_DESCRIPTOR_LOAD_OFFSET (MEDIA_STATE_FLUSH_INITIAL_OFFSET + OCLRT_SIZEOF_MSFLUSH_DWORD)
// DWORD OFFSET of InterfaceDescriptor Length
// bits 0 - 16
#define MEDIA_INTERFACE_DESCRIPTOR_LOAD_INTERFACEDESCRIPTORLENGTH_OFFSET (MEDIA_INTERFACE_DESCRIPTOR_LOAD_OFFSET + 2)
// DWORD OFFSET of Interface Descriptor Start Address
#define MEDIA_INTERFACE_DESCRIPTOR_LOAD_INTERFACEDESCRIPTORSTARTADDRESS_OFFSET (MEDIA_INTERFACE_DESCRIPTOR_LOAD_OFFSET + 3)
#define PIPE_CONTROL_FOR_TIMESTAMP_START_OFFSET (MEDIA_INTERFACE_DESCRIPTOR_LOAD_OFFSET + OCLRT_SIZEOF_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DEVICE_CMD_DWORD_OFFSET)
#define INTERFACE_DESCRIPTOR_SAMPLER_STATE_TABLE_DWORD 3
#define INTERFACE_DESCRIPTOR_BINDING_TABLE_POINTER_DWORD 4
#define INTERFACE_DESCRIPTOR_CONSTANT_URB_ENTRY_READ_OFFSET 5
#define INTERFACE_DESCRIPTOR_HWTHREADS_NUMBER_DWORD 6
#define INTERFACE_DESCRIPTOR_SLMSIZE_DWORD 6
#define INTERFACE_DESCRIPTOR_HWTHREADS_UPPER_BIT 9
#define SAMPLER_STATE_INDIRECT_STATE_MASK (0x7FFFFC0)
#define SAMPLER_STATE_BORDER_COLOR_MASK (0xFFFFFFE0)
#define SAMPLER_STATE_DESCRIPTOR_BORDER_COLOR_POINTER_DWORD 2
#define GPGPU_WALKER_OFFSET (PIPE_CONTROL_FOR_TIMESTAMP_START_OFFSET + OCLRT_PIPE_CONTROL_CMD_DEVICE_CMD_G11_DWORD_OFFSET)
// DWORD OFFSET of the Interface Descriptor Offset for GPGPU_WALKER
// bits 0 - 5
#define GPGPU_WALKER_INTERFACE_DESCRIPTOR_ID_OFFSET (GPGPU_WALKER_OFFSET + 1)
// DWORD OFFSET of the Indirect data length Offset for GPGPU_WALKER
// bits 0 - 16
#define GPGPU_WALKER_INDIRECT_DATA_LENGTH_OFFSET (GPGPU_WALKER_OFFSET + 2)
// DWORD OFFSET of the Indirect Start Address for GPGPU_WALKER
#define GPGPU_WALKER_INDIRECT_START_ADDRESS_OFFSET (GPGPU_WALKER_OFFSET + 3)
// DWORD OFFSET of the Thread Width Counter Maximum for GPGPU_WALKER
// bits 0 - 5
#define GPGPU_WALKER_THREAD_WIDTH_DWORD (GPGPU_WALKER_OFFSET + 4)
// DWORD OFFSET of the Thread Height Counter Maximum for GPGPU_WALKER
// bits 8 - 13
#define GPGPU_WALKER_THREAD_HEIGHT_DWORD (GPGPU_WALKER_OFFSET + 4)
// DWORD OFFSET of the Thread Depth Counter Maximum for GPGPU_WALKER
// bits 16 - 21
#define GPGPU_WALKER_THREAD_DEPTH_DWORD (GPGPU_WALKER_OFFSET + 4)
// DWORD OFFSET of the SIMD Size for GPGPU_WALKER
// bits 30 - 31
#define GPGPU_WALKER_SIMDSIZE_DWORD (GPGPU_WALKER_OFFSET + 4)
// DWORD OFFSET of the Starting in X pos for GPGPU_WALKER
//bits 0 - 31
#define GPGPU_WALKER_GROUP_ID_START_X (GPGPU_WALKER_OFFSET + 5)
// DWORD OFFSET of the X Dimension for GPGPU_WALKER
#define GPGPU_WALKER_XDIM_DWORD (GPGPU_WALKER_OFFSET + 7)
// DWORD OFFSET of the Starting in Y pos for GPGPU_WALKER
//bits 0 - 31
#define GPGPU_WALKER_GROUP_ID_START_Y (GPGPU_WALKER_OFFSET + 8)
// DWORD OFFSET of the Y Dimension for GPGPU_WALKER
#define GPGPU_WALKER_YDIM_DWORD (GPGPU_WALKER_OFFSET + 10)
// DWORD OFFSET of the Starting in Z pos for GPGPU_WALKER
//bits 0 - 31
#define GPGPU_WALKER_GROUP_ID_START_Z (GPGPU_WALKER_OFFSET + 11)
// DWORD OFFSET of the X Dimension for GPGPU_WALKER
#define GPGPU_WALKER_ZDIM_DWORD (GPGPU_WALKER_OFFSET + 12)
// DWORD OFFSET of the Right or X Mask for GPGPU_WALKER
#define GPGPU_WALKER_XMASK_DWORD (GPGPU_WALKER_OFFSET + 13)
// DWORD OFFSET of the Bottom or Y Mask for GPGPU_WALKER
#define GPGPU_WALKER_YMASK_DWORD (GPGPU_WALKER_OFFSET + 14)
#define MEDIA_STATE_FLUSH_OFFSET (GPGPU_WALKER_OFFSET + OCLRT_GPGPU_WALKER_CMD_DEVICE_CMD_G11_DWORD_OFFSET)
//bits 0-5 of 1st DWORD of M_S_F command
#define MEDIA_STATE_FLUSH_INTERFACE_DESCRIPTOR_OFFSET (MEDIA_STATE_FLUSH_OFFSET + 1)
#define PIPE_CONTROL_FOR_TIMESTAMP_END_OFFSET (MEDIA_STATE_FLUSH_OFFSET + OCLRT_SIZEOF_MSFLUSH_DWORD)
#define PIPE_CONTROL_FOR_TIMESTAMP_END_OFFSET_TO_PATCH (PIPE_CONTROL_FOR_TIMESTAMP_END_OFFSET)
#define PIPE_CONTROL_POST_SYNC_DWORD 1
#define PIPE_CONTROL_POST_SYNC_START_BIT 14
#define PIPE_CONTROL_POST_SYNC_END_BIT 15
#define PIPE_CONTROL_GENERATE_TIME_STAMP 3
#define PIPE_CONTROL_NO_POSTSYNC_OPERATION 0
#define PIPE_CONTROL_ADDRESS_FIELD_DWORD 2
#define PIPE_CONTROL_PROFILING_START_TIMESTAMP_ADDRESS_OFFSET (PIPE_CONTROL_FOR_TIMESTAMP_START_OFFSET + PIPE_CONTROL_ADDRESS_FIELD_DWORD) //DWORD 2
#define PIPE_CONTROL_GRAPHICS_ADDRESS_START_BIT 2
#define PIPE_CONTROL_GRAPHICS_ADDRESS_END_BIT 31
#define PIPE_CONTROL_GRAPHICS_ADDRESS_HIGH_START_BIT 0
#define PIPE_CONTROL_GRAPHICS_ADDRESS_HIGH_END_BIT 15
#define PIPE_CONTROL_TIME_STAMP_DWORD0 0x7A000004
#define PIPE_CONTROL_TIME_STAMP_DWORD1 0x0010C4A4
#define PIPE_CONTROL_CSTALL_DWORD0 0x7A000004
#define PIPE_CONTROL_CSTALL_DWORD1 0x001004A4
#define PIPE_CONTROL_TAG_WRITE_DWORD0 0x7A000004
#define PIPE_CONTROL_TAG_WRITE_DWORD1 0x001044A4
// the value of g_cInitMiBatchBufferStartCmdG11 DWORD0
#define OCLRT_BATCH_BUFFER_BEGIN_CMD_DWORD0 (0x18800101)
#if defined WA_LRI_COMMANDS_EXIST
#define IMM_LOAD_REGISTER_FOR_ENABLE_PREEMPTION_OFFSET (PIPE_CONTROL_FOR_TIMESTAMP_END_OFFSET + OCLRT_PIPE_CONTROL_CMD_DEVICE_CMD_G11_DWORD_OFFSET + OCLRT_PIPE_CONTROL_CMD_DEVICE_CMD_G11_DWORD_OFFSET)
#endif
#define OCLRT_LOAD_REGISTER_IMM_CMD 0x11000001
#define CTXT_PREMP_DBG_ADDRESS_VALUE 0x2248
#define CTXT_PREMP_ON_MI_ARB_CHECK_ONLY 0x00000100
#define CTXT_PREMP_DEFAULT_VALUE 0x0
#define IMM_LOAD_REGISTER_ADDRESS_DWORD_OFFSET 1
#define IMM_LOAD_REGISTER_VALUE_DWORD_OFFSET 2

88
runtime/gen11/scheduler_igdrcl_built_in.inl Normal file
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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
uint GetPatchValueForSLMSize(uint slMsize) {
uint PatchValue = 0;
if (slMsize == 0) {
PatchValue = 0;
} else if (slMsize <= (1 * 1024)) {
PatchValue = 1;
} else if (slMsize <= (2 * 1024)) {
PatchValue = 2;
} else if (slMsize <= (4 * 1024)) {
PatchValue = 3;
} else if (slMsize <= (8 * 1024)) {
PatchValue = 4;
} else if (slMsize <= (16 * 1024)) {
PatchValue = 5;
} else if (slMsize <= (32 * 1024)) {
PatchValue = 6;
} else if (slMsize <= (64 * 1024)) {
PatchValue = 7;
}
return PatchValue;
}
//on SKL we have pipe control in pairs, therefore when we NOOP we need to do this for both pipe controls
void NOOPCSStallPipeControl(__global uint *secondaryBatchBuffer, uint dwordOffset, uint pipeControlOffset) {
dwordOffset += pipeControlOffset;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
}
//on SKL+ with mid thread preemption we need to have 2 pipe controls instead of 1 any time we do post sync operation
void PutCSStallPipeControl(__global uint *secondaryBatchBuffer, uint dwordOffset, uint pipeControlOffset) {
dwordOffset += pipeControlOffset;
//first pipe control doing CS stall
secondaryBatchBuffer[dwordOffset] = PIPE_CONTROL_CSTALL_DWORD0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = PIPE_CONTROL_CSTALL_DWORD1;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
//second pipe control , doing actual timestamp write
secondaryBatchBuffer[dwordOffset] = PIPE_CONTROL_CSTALL_DWORD0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = PIPE_CONTROL_CSTALL_DWORD1;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
}

13
runtime/gen11/state_base_address_gen11.cpp Normal file
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@@ -0,0 +1,13 @@
/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/helpers/state_base_address.h"
#include "runtime/helpers/state_base_address.inl"
namespace NEO {
template struct StateBaseAddressHelper<ICLFamily>;
}

39
runtime/gen11/tbx_command_stream_receiver_gen11.cpp Normal file
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@@ -0,0 +1,39 @@
/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/command_stream/command_stream_receiver_with_aub_dump.inl"
#include "runtime/command_stream/tbx_command_stream_receiver_hw.h"
#include "runtime/command_stream/tbx_command_stream_receiver_hw.inl"
#include "runtime/helpers/array_count.h"
#include "runtime/helpers/base_object.h"
#include "hw_cmds.h"
namespace NEO {
typedef ICLFamily Family;
static auto gfxCore = IGFX_GEN11_CORE;
template <>
uint32_t TbxCommandStreamReceiverHw<Family>::getMaskAndValueForPollForCompletion() const {
return 0x80;
}
template <>
bool TbxCommandStreamReceiverHw<Family>::getpollNotEqualValueForPollForCompletion() const {
return true;
}
template <>
void populateFactoryTable<TbxCommandStreamReceiverHw<Family>>() {
extern TbxCommandStreamReceiverCreateFunc tbxCommandStreamReceiverFactory[IGFX_MAX_CORE];
UNRECOVERABLE_IF(!isInRange(gfxCore, tbxCommandStreamReceiverFactory));
tbxCommandStreamReceiverFactory[gfxCore] = TbxCommandStreamReceiverHw<Family>::create;
}
template class TbxCommandStreamReceiverHw<Family>;
template class CommandStreamReceiverWithAUBDump<TbxCommandStreamReceiverHw<Family>>;
} // namespace NEO

17
runtime/gen11/windows/command_stream_receiver_gen11.cpp Normal file
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@@ -0,0 +1,17 @@
/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/command_stream/command_stream_receiver_with_aub_dump.inl"
#include "runtime/os_interface/windows/device_command_stream.inl"
#include "runtime/os_interface/windows/wddm_device_command_stream.inl"
namespace NEO {
template class DeviceCommandStreamReceiver<ICLFamily>;
template class WddmCommandStreamReceiver<ICLFamily>;
template class CommandStreamReceiverWithAUBDump<WddmCommandStreamReceiver<ICLFamily>>;
} // namespace NEO

16
runtime/gen11/windows/gmm_callbacks_gen11.cpp Normal file
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@@ -0,0 +1,16 @@
/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/helpers/gmm_callbacks.h"
#include "runtime/helpers/gmm_callbacks.inl"
#include "hw_cmds.h"
using namespace NEO;
template struct DeviceCallbacks<ICLFamily>;
template struct TTCallbacks<ICLFamily>;

31
runtime/gen11/windows/hw_info_config_gen11.cpp Normal file
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@@ -0,0 +1,31 @@
/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/helpers/hw_info.h"
#include "runtime/os_interface/hw_info_config.h"
#include "runtime/os_interface/hw_info_config.inl"
namespace NEO {
#ifdef SUPPORT_ICLLP
template <>
int HwInfoConfigHw<IGFX_ICELAKE_LP>::configureHardwareCustom(HardwareInfo *hwInfo, OSInterface *osIface) {
return 0;
}
template class HwInfoConfigHw<IGFX_ICELAKE_LP>;
#endif
#ifdef SUPPORT_LKF
template <>
int HwInfoConfigHw<IGFX_LAKEFIELD>::configureHardwareCustom(HardwareInfo *hwInfo, OSInterface *osIface) {
return 0;
}
template class HwInfoConfigHw<IGFX_LAKEFIELD>;
#endif
} // namespace NEO

5
runtime/gen_common/aub_mapper.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2018 Intel Corporation
* Copyright (C) 2017-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -15,3 +15,6 @@
#ifdef SUPPORT_GEN10
#include "runtime/gen10/aub_mapper.h"
#endif
#ifdef SUPPORT_GEN11
#include "runtime/gen11/aub_mapper.h"
#endif

5
runtime/gen_common/hw_cmds.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2018 Intel Corporation
* Copyright (C) 2017-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -15,3 +15,6 @@
#ifdef SUPPORT_GEN10
#include "runtime/gen10/hw_cmds.h"
#endif
#ifdef SUPPORT_GEN11
#include "runtime/gen11/hw_cmds.h"
#endif

4
runtime/gen_common/reg_configs/reg_configs_common.h
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@@ -15,7 +15,9 @@
#ifdef SUPPORT_GEN10
#include "runtime/gen10/reg_configs.h"
#endif
#ifdef SUPPORT_GEN11
#include "runtime/gen11/reg_configs.h"
#endif
#include <cstdint>
namespace NEO {

1
runtime/helpers/pipeline_select_helper.h
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@@ -11,4 +11,5 @@
namespace NEO {
const uint32_t pipelineSelectEnablePipelineSelectMaskBits = 0x3;
const uint32_t pipelineSelectMediaSamplerDopClockGateMaskBits = 0x10;
const uint32_t pipelineSelectMediaSamplerPowerClockGateMaskBits = 0x40;
} // namespace NEO

1
runtime/memory_manager/memory_constants.h
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@@ -39,6 +39,7 @@ static const uint64_t max32BitAppAddress = maxNBitValue<31>;
static const uint64_t max64BitAppAddress = maxNBitValue<47>;
static const uint32_t sizeOf4GBinPageEntities = (MemoryConstants::gigaByte * 4 - MemoryConstants::pageSize) / MemoryConstants::pageSize;
static const uint64_t max32BitAddress = maxNBitValue<32>;
static const uint64_t max36BitAddress = ((1ULL << 36) - 1);
static const uint64_t max48BitAddress = maxNBitValue<48>;
static const uintptr_t page4kEntryMask = std::numeric_limits<uintptr_t>::max() & ~MemoryConstants::pageMask;
static const uintptr_t page64kEntryMask = std::numeric_limits<uintptr_t>::max() & ~MemoryConstants::page64kMask;

14
unit_tests/aub_tests/gen11/CMakeLists.txt Normal file
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@@ -0,0 +1,14 @@
#
# Copyright (C) 2017-2019 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
if(TESTS_GEN11)
target_sources(igdrcl_aub_tests PRIVATE
${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
${CMAKE_CURRENT_SOURCE_DIR}/aub_tests_configuration_gen11.cpp
${IGDRCL_SOURCE_DIR}/unit_tests/gen11/unit_test_helper_gen11.cpp
)
add_subdirectories()
endif()

13
unit_tests/aub_tests/gen11/aub_tests_configuration_gen11.cpp Normal file
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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/gen_common/hw_cmds.h"
#include "unit_tests/aub_tests/aub_tests_configuration.inl"
using namespace NEO;
template AubTestsConfig GetAubTestsConfig<ICLFamily>();

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#
# Copyright (C) 2017-2019 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
target_sources(igdrcl_aub_tests PRIVATE
${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
${CMAKE_CURRENT_SOURCE_DIR}/aub_batch_buffer_tests_gen11.h
${CMAKE_CURRENT_SOURCE_DIR}/aub_batch_buffer_tests_gen11.cpp
)

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unit_tests/aub_tests/gen11/batch_buffer/aub_batch_buffer_tests_gen11.cpp Normal file
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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "aub_batch_buffer_tests_gen11.h"
#include "unit_tests/fixtures/device_fixture.h"
using Gen11AubBatchBufferTests = Test<NEO::DeviceFixture>;
static constexpr auto gpuBatchBufferAddr = 0x800400001000; // 48-bit GPU address
GEN11TEST_F(Gen11AubBatchBufferTests, givenSimpleRCSWithBatchBufferWhenItHasMSBSetInGpuAddressThenAUBShouldBeSetupSuccessfully) {
setupAUBWithBatchBuffer<FamilyType>(pDevice, aub_stream::ENGINE_RCS, gpuBatchBufferAddr);
}

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "runtime/aub/aub_helper.h"
#include "unit_tests/aub_tests/command_stream/aub_mem_dump_tests.h"
template <typename FamilyType>
void setupAUBWithBatchBuffer(const NEO::Device *pDevice, aub_stream::EngineType engineType, uint64_t gpuBatchBufferAddr) {
typedef typename NEO::AUBFamilyMapper<FamilyType>::AUB AUB;
const auto &csTraits = NEO::CommandStreamReceiverSimulatedCommonHw<FamilyType>::getCsTraits(engineType);
auto mmioBase = csTraits.mmioBase;
uint64_t physAddress = 0x10000;
NEO::AUBCommandStreamReceiver::AubFileStream aubFile;
std::string filePath(NEO::folderAUB);
filePath.append(Os::fileSeparator);
std::string baseName("simple");
baseName.append(csTraits.name);
baseName.append("WithBatchBuffer");
baseName.append(".aub");
filePath.append(getAubFileName(pDevice, baseName));
aubFile.fileHandle.open(filePath.c_str(), std::ofstream::binary);
// Header
aubFile.init(AubMemDump::SteppingValues::A, AUB::Traits::device);
aubFile.writeMMIO(AubMemDump::computeRegisterOffset(mmioBase, 0x229c), 0xffff8280);
const size_t sizeHWSP = 0x1000;
const size_t alignHWSP = 0x1000;
auto pGlobalHWStatusPage = alignedMalloc(sizeHWSP, alignHWSP);
uint32_t ggttGlobalHardwareStatusPage = (uint32_t)((uintptr_t)pGlobalHWStatusPage);
AubGTTData data = {true, false};
AUB::reserveAddressGGTT(aubFile, ggttGlobalHardwareStatusPage, sizeHWSP, physAddress, data);
physAddress += sizeHWSP;
aubFile.writeMMIO(AubMemDump::computeRegisterOffset(mmioBase, 0x2080), ggttGlobalHardwareStatusPage);
using MI_NOOP = typename FamilyType::MI_NOOP;
using MI_BATCH_BUFFER_START = typename FamilyType::MI_BATCH_BUFFER_START;
using MI_BATCH_BUFFER_END = typename FamilyType::MI_BATCH_BUFFER_END;
// create a user mode batch buffer
auto physBatchBuffer = physAddress;
const auto sizeBatchBuffer = 0x1000;
auto gpuBatchBuffer = static_cast<uintptr_t>(gpuBatchBufferAddr);
physAddress += sizeBatchBuffer;
NEO::AubHelperHw<FamilyType> aubHelperHw(false);
AUB::reserveAddressPPGTT(aubFile, gpuBatchBuffer, sizeBatchBuffer, physBatchBuffer, 7, aubHelperHw);
uint8_t batchBuffer[sizeBatchBuffer];
auto noop = FamilyType::cmdInitNoop;
uint32_t noopId = 0xbaadd;
{
auto pBatchBuffer = (void *)batchBuffer;
*(MI_NOOP *)pBatchBuffer = noop;
pBatchBuffer = ptrOffset(pBatchBuffer, sizeof(MI_NOOP));
*(MI_NOOP *)pBatchBuffer = noop;
pBatchBuffer = ptrOffset(pBatchBuffer, sizeof(MI_NOOP));
*(MI_NOOP *)pBatchBuffer = noop;
pBatchBuffer = ptrOffset(pBatchBuffer, sizeof(MI_NOOP));
noop.TheStructure.Common.IdentificationNumberRegisterWriteEnable = true;
noop.TheStructure.Common.IdentificationNumber = noopId++;
*(MI_NOOP *)pBatchBuffer = noop;
pBatchBuffer = ptrOffset(pBatchBuffer, sizeof(MI_NOOP));
*(MI_BATCH_BUFFER_END *)pBatchBuffer = FamilyType::cmdInitBatchBufferEnd;
pBatchBuffer = ptrOffset(pBatchBuffer, sizeof(MI_BATCH_BUFFER_END));
auto sizeBufferUsed = ptrDiff(pBatchBuffer, batchBuffer);
AUB::addMemoryWrite(aubFile, physBatchBuffer, batchBuffer, sizeBufferUsed, AubMemDump::AddressSpaceValues::TraceNonlocal, AubMemDump::DataTypeHintValues::TraceBatchBuffer);
}
const size_t sizeRing = 0x4 * 0x1000;
const size_t alignRing = 0x1000;
size_t sizeCommands = 0;
auto pRing = alignedMalloc(sizeRing, alignRing);
auto ggttRing = (uint32_t)(uintptr_t)pRing;
auto physRing = physAddress;
physAddress += sizeRing;
auto rRing = AUB::reserveAddressGGTT(aubFile, ggttRing, sizeRing, physRing, data);
ASSERT_NE(static_cast<uint64_t>(-1), rRing);
EXPECT_EQ(rRing, physRing);
auto cur = (uint32_t *)pRing;
auto bbs = FamilyType::cmdInitBatchBufferStart;
bbs.setBatchBufferStartAddressGraphicsaddress472(gpuBatchBuffer);
bbs.setAddressSpaceIndicator(MI_BATCH_BUFFER_START::ADDRESS_SPACE_INDICATOR_PPGTT);
*(MI_BATCH_BUFFER_START *)cur = bbs;
cur = ptrOffset(cur, sizeof(MI_BATCH_BUFFER_START));
noop.TheStructure.Common.IdentificationNumberRegisterWriteEnable = true;
noop.TheStructure.Common.IdentificationNumber = noopId;
*cur++ = noop.TheStructure.RawData[0];
sizeCommands = ptrDiff(cur, pRing);
AUB::addMemoryWrite(aubFile, physRing, pRing, sizeCommands, AubMemDump::AddressSpaceValues::TraceNonlocal, csTraits.aubHintCommandBuffer);
auto sizeLRCA = csTraits.sizeLRCA;
auto pLRCABase = alignedMalloc(csTraits.sizeLRCA, csTraits.alignLRCA);
csTraits.initialize(pLRCABase);
csTraits.setRingHead(pLRCABase, 0x0000);
csTraits.setRingTail(pLRCABase, static_cast<uint32_t>(sizeCommands));
csTraits.setRingBase(pLRCABase, ggttRing);
auto ringCtrl = static_cast<uint32_t>((sizeRing - 0x1000) | 1);
csTraits.setRingCtrl(pLRCABase, ringCtrl);
auto ggttLRCA = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(pLRCABase));
auto physLRCA = physAddress;
physAddress += sizeLRCA;
AUB::reserveAddressGGTT(aubFile, ggttLRCA, sizeLRCA, physLRCA, data);
AUB::addMemoryWrite(aubFile, physLRCA, pLRCABase, sizeLRCA, AubMemDump::AddressSpaceValues::TraceNonlocal, csTraits.aubHintLRCA);
typename AUB::MiContextDescriptorReg contextDescriptor = {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}};
contextDescriptor.sData.Valid = true;
contextDescriptor.sData.ForcePageDirRestore = false;
contextDescriptor.sData.ForceRestore = false;
contextDescriptor.sData.Legacy = true;
contextDescriptor.sData.FaultSupport = 0;
contextDescriptor.sData.PrivilegeAccessOrPPGTT = true;
contextDescriptor.sData.ADor64bitSupport = AUB::Traits::addressingBits > 32;
contextDescriptor.sData.LogicalRingCtxAddress = (uintptr_t)pLRCABase / 4096;
contextDescriptor.sData.ContextID = 0;
aubFile.writeMMIO(AubMemDump::computeRegisterOffset(mmioBase, 0x2510), contextDescriptor.ulData[0]);
aubFile.writeMMIO(AubMemDump::computeRegisterOffset(mmioBase, 0x2514), contextDescriptor.ulData[1]);
// Load our new exec list
aubFile.writeMMIO(AubMemDump::computeRegisterOffset(mmioBase, 0x2550), 1);
// Poll until HW complete
using AubMemDump::CmdServicesMemTraceRegisterPoll;
aubFile.registerPoll(
AubMemDump::computeRegisterOffset(mmioBase, 0x2234), //EXECLIST_STATUS
0x00008000,
0x00008000,
false,
CmdServicesMemTraceRegisterPoll::TimeoutActionValues::Abort);
alignedFree(pRing);
alignedFree(pLRCABase);
alignedFree(pGlobalHWStatusPage);
aubFile.fileHandle.close();
}

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unit_tests/aub_tests/gen11/execution_model/CMakeLists.txt Normal file
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#
# Copyright (C) 2017-2019 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
target_sources(igdrcl_aub_tests PRIVATE
${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
${CMAKE_CURRENT_SOURCE_DIR}/enqueue_parent_kernel_tests_gen11.cpp
)

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unit_tests/aub_tests/gen11/execution_model/enqueue_parent_kernel_tests_gen11.cpp Normal file
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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/built_ins/built_ins.h"
#include "runtime/mem_obj/image.h"
#include "runtime/sampler/sampler.h"
#include "test.h"
#include "unit_tests/aub_tests/fixtures/aub_parent_kernel_fixture.h"
#include "unit_tests/fixtures/buffer_fixture.h"
using namespace NEO;
typedef AUBParentKernelFixture GEN11AUBParentKernelFixture;
GEN11TEST_F(GEN11AUBParentKernelFixture, EnqueueParentKernel) {
if (pDevice->getSupportedClVersion() >= 20) {
ASSERT_NE(nullptr, pKernel);
ASSERT_TRUE(pKernel->isParentKernel);
const cl_queue_properties properties[3] = {(CL_QUEUE_ON_DEVICE | CL_QUEUE_OUT_OF_ORDER_EXEC_MODE_ENABLE),
0, 0};
DeviceQueue *devQueue = DeviceQueue::create(
&pCmdQ->getContext(),
pDevice,
properties[0],
retVal);
BuiltIns &builtIns = *pDevice->getExecutionEnvironment()->getBuiltIns();
SchedulerKernel &scheduler = builtIns.getSchedulerKernel(pCmdQ->getContext());
// Aub execution takes huge time for bigger GWS
scheduler.setGws(24);
size_t offset[3] = {0, 0, 0};
size_t gws[3] = {1, 1, 1};
size_t lws[3] = {1, 1, 1};
// clang-format off
cl_image_format imageFormat;
imageFormat.image_channel_data_type = CL_UNSIGNED_INT8;
imageFormat.image_channel_order = CL_R;
cl_image_desc desc = { 0 };
desc.image_array_size = 0;
desc.image_depth = 1;
desc.image_height = 4;
desc.image_width = 4;
desc.image_type = CL_MEM_OBJECT_IMAGE3D;
desc.image_row_pitch = 0;
desc.image_slice_pitch = 0;
// clang-format on
auto surfaceFormat = Image::getSurfaceFormatFromTable(0, &imageFormat);
Image *image = Image::create(
pContext,
0,
surfaceFormat,
&desc,
nullptr,
retVal);
Buffer *buffer = BufferHelper<BufferUseHostPtr<>>::create(pContext);
cl_mem bufferMem = buffer;
cl_mem imageMem = image;
auto sampler = Sampler::create(
pContext,
CL_TRUE,
CL_ADDRESS_NONE,
CL_FILTER_LINEAR,
retVal);
uint64_t argScalar = 2;
pKernel->setArg(
3,
sizeof(uint64_t),
&argScalar);
pKernel->setArg(
2,
sizeof(cl_mem),
&bufferMem);
pKernel->setArg(
1,
sizeof(cl_mem),
&imageMem);
pKernel->setArg(
0,
sizeof(cl_sampler),
&sampler);
pCmdQ->enqueueKernel(pKernel, 1, offset, gws, lws, 0, 0, 0);
pCmdQ->finish(false);
uint32_t expectedNumberOfEnqueues = 1;
IGIL_CommandQueue *igilQueue = reinterpret_cast<IGIL_CommandQueue *>(devQueue->getQueueBuffer()->getUnderlyingBuffer());
uint64_t gpuAddress = devQueue->getQueueBuffer()->getGpuAddress();
uint32_t *pointerTonumberOfEnqueues = &igilQueue->m_controls.m_TotalNumberOfQueues;
size_t offsetToEnqueues = ptrDiff(pointerTonumberOfEnqueues, igilQueue);
gpuAddress = gpuAddress + offsetToEnqueues;
AUBCommandStreamFixture::expectMemory<FamilyType>((void *)(uintptr_t)gpuAddress, &expectedNumberOfEnqueues, sizeof(uint32_t));
AUBCommandStreamFixture::expectMemory<FamilyType>((void *)(uintptr_t)buffer->getGraphicsAllocation()->getGpuAddress(), &argScalar, sizeof(size_t));
delete devQueue;
delete image;
delete buffer;
delete sampler;
}
}

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#
# Copyright (C) 2018-2019 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
if(TESTS_GEN11)
set(IGDRCL_SRCS_tests_gen11
${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
${CMAKE_CURRENT_SOURCE_DIR}/coherency_tests_gen11.cpp
${CMAKE_CURRENT_SOURCE_DIR}/command_stream_receiver_hw_tests_gen11.cpp
${CMAKE_CURRENT_SOURCE_DIR}/enqueue_kernel_gen11.cpp
${CMAKE_CURRENT_SOURCE_DIR}/enqueue_media_kernel_gen11.cpp
${CMAKE_CURRENT_SOURCE_DIR}/hw_helper_tests_gen11.cpp
${CMAKE_CURRENT_SOURCE_DIR}/image_tests_gen11.cpp
${CMAKE_CURRENT_SOURCE_DIR}/kernel_tests_gen11.cpp
${CMAKE_CURRENT_SOURCE_DIR}/preamble_tests_gen11.cpp
${CMAKE_CURRENT_SOURCE_DIR}/program_media_sampler_tests_gen11.cpp
${CMAKE_CURRENT_SOURCE_DIR}/sampler_tests_gen11.cpp
${CMAKE_CURRENT_SOURCE_DIR}/scheduler_source_tests_gen11.cpp
${CMAKE_CURRENT_SOURCE_DIR}/tbx_command_stream_receiver_tests_gen11.cpp
${CMAKE_CURRENT_SOURCE_DIR}/test_device_caps_gen11.cpp
${CMAKE_CURRENT_SOURCE_DIR}/test_device_queue_hw_gen11.cpp
${CMAKE_CURRENT_SOURCE_DIR}/test_platform_caps_gen11.cpp
${CMAKE_CURRENT_SOURCE_DIR}/test_preamble_gen11.cpp
${CMAKE_CURRENT_SOURCE_DIR}/test_preemption_gen11.cpp
${CMAKE_CURRENT_SOURCE_DIR}/test_sample_gen11.cpp
${CMAKE_CURRENT_SOURCE_DIR}/unit_test_helper_gen11.cpp
)
target_sources(igdrcl_tests PRIVATE ${IGDRCL_SRCS_tests_gen11})
add_subdirectories()
endif()

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "unit_tests/gen_common/gen_cmd_parse.h"
#include "gtest/gtest.h"
using GenStruct = NEO::GEN11;
using GenGfxFamily = NEO::ICLFamily;
#include "unit_tests/gen_common/cmd_parse_base.inl"
#include "unit_tests/gen_common/cmd_parse_base_mi_arb.inl"
#include "unit_tests/gen_common/cmd_parse_gpgpu_walker.inl"
#include "unit_tests/gen_common/cmd_parse_sip.inl"
#include "unit_tests/helpers/hw_parse.h"
#include "unit_tests/helpers/hw_parse.inl"
template <>
size_t CmdParse<GenGfxFamily>::getCommandLengthHwSpecific(void *cmd) {
{
auto pCmd = genCmdCast<GPGPU_WALKER *>(cmd);
if (pCmd)
return pCmd->TheStructure.Common.DwordLength + 2;
}
{
auto pCmd = genCmdCast<MEDIA_INTERFACE_DESCRIPTOR_LOAD *>(cmd);
if (pCmd)
return pCmd->TheStructure.Common.DwordLength + 2;
}
{
auto pCmd = genCmdCast<MEDIA_VFE_STATE *>(cmd);
if (pCmd)
return pCmd->TheStructure.Common.DwordLength + 2;
}
{
auto pCmd = genCmdCast<MEDIA_STATE_FLUSH *>(cmd);
if (pCmd)
return pCmd->TheStructure.Common.DwordLength + 2;
}
{
auto pCmd = genCmdCast<GPGPU_CSR_BASE_ADDRESS *>(cmd);
if (pCmd)
return pCmd->TheStructure.Common.DwordLength + 2;
}
{
auto pCmd = genCmdCast<STATE_SIP *>(cmd);
if (pCmd)
return pCmd->TheStructure.Common.DwordLength + 2;
}
return 0;
}
template <>
const char *CmdParse<GenGfxFamily>::getCommandNameHwSpecific(void *cmd) {
if (nullptr != genCmdCast<GPGPU_WALKER *>(cmd)) {
return "GPGPU_WALKER";
}
if (nullptr != genCmdCast<MEDIA_INTERFACE_DESCRIPTOR_LOAD *>(cmd)) {
return "MEDIA_INTERFACE_DESCRIPTOR_LOAD";
}
if (nullptr != genCmdCast<MEDIA_VFE_STATE *>(cmd)) {
return "MEDIA_VFE_STATE";
}
if (nullptr != genCmdCast<MEDIA_STATE_FLUSH *>(cmd)) {
return "MEDIA_STATE_FLUSH";
}
if (nullptr != genCmdCast<GPGPU_CSR_BASE_ADDRESS *>(cmd)) {
return "GPGPU_CSR_BASE_ADDRESS";
}
if (nullptr != genCmdCast<STATE_SIP *>(cmd)) {
return "STATE_SIP";
}
return "UNKNOWN";
}
template struct CmdParse<GenGfxFamily>;
namespace NEO {
template void HardwareParse::findHardwareCommands<ICLFamily>();
template void HardwareParse::findHardwareCommands<ICLFamily>(IndirectHeap *);
template const void *HardwareParse::getStatelessArgumentPointer<ICLFamily>(const Kernel &kernel, uint32_t indexArg, IndirectHeap &ioh);
} // namespace NEO

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/command_stream/command_stream_receiver_hw.h"
#include "runtime/gen11/reg_configs.h"
#include "runtime/helpers/hw_helper.h"
#include "test.h"
#include "unit_tests/helpers/hw_parse.h"
#include "unit_tests/mocks/mock_device.h"
using namespace NEO;
struct Gen11CoherencyRequirements : public ::testing::Test {
typedef typename ICLFamily::MI_LOAD_REGISTER_IMM MI_LOAD_REGISTER_IMM;
struct myCsr : public CommandStreamReceiverHw<ICLFamily> {
using CommandStreamReceiver::commandStream;
myCsr(ExecutionEnvironment &executionEnvironment) : CommandStreamReceiverHw<ICLFamily>(executionEnvironment){};
CsrSizeRequestFlags *getCsrRequestFlags() { return &csrSizeRequestFlags; }
};
void overrideCoherencyRequest(bool requestChanged, bool requireCoherency) {
csr->getCsrRequestFlags()->coherencyRequestChanged = requestChanged;
flags.requiresCoherency = requireCoherency;
}
void SetUp() override {
device.reset(MockDevice::createWithNewExecutionEnvironment<MockDevice>(platformDevices[0]));
csr = new myCsr(*device->executionEnvironment);
device->resetCommandStreamReceiver(csr);
}
myCsr *csr = nullptr;
std::unique_ptr<MockDevice> device;
DispatchFlags flags = {};
};
GEN11TEST_F(Gen11CoherencyRequirements, coherencyCmdSize) {
auto lriSize = sizeof(MI_LOAD_REGISTER_IMM);
overrideCoherencyRequest(false, false);
auto retSize = csr->getCmdSizeForComputeMode();
EXPECT_EQ(0u, retSize);
overrideCoherencyRequest(false, true);
retSize = csr->getCmdSizeForComputeMode();
EXPECT_EQ(0u, retSize);
overrideCoherencyRequest(true, true);
retSize = csr->getCmdSizeForComputeMode();
EXPECT_EQ(lriSize, retSize);
overrideCoherencyRequest(true, false);
retSize = csr->getCmdSizeForComputeMode();
EXPECT_EQ(lriSize, retSize);
}
GEN11TEST_F(Gen11CoherencyRequirements, hdcModeCmdValues) {
auto lriSize = sizeof(MI_LOAD_REGISTER_IMM);
char buff[MemoryConstants::pageSize];
LinearStream stream(buff, MemoryConstants::pageSize);
auto expectedCmd = FamilyType::cmdInitLoadRegisterImm;
expectedCmd.setRegisterOffset(gen11HdcModeRegister::address);
expectedCmd.setDataDword(DwordBuilder::build(gen11HdcModeRegister::forceNonCoherentEnableBit, true));
overrideCoherencyRequest(true, false);
csr->programComputeMode(stream, flags);
EXPECT_EQ(csr->getCmdSizeForComputeMode(), stream.getUsed());
auto cmd = reinterpret_cast<MI_LOAD_REGISTER_IMM *>(stream.getCpuBase());
EXPECT_TRUE(memcmp(&expectedCmd, cmd, lriSize) == 0);
overrideCoherencyRequest(true, true);
csr->programComputeMode(stream, flags);
EXPECT_EQ(csr->getCmdSizeForComputeMode() * 2, stream.getUsed());
cmd = reinterpret_cast<MI_LOAD_REGISTER_IMM *>(ptrOffset(stream.getCpuBase(), lriSize));
expectedCmd.setDataDword(DwordBuilder::build(gen11HdcModeRegister::forceNonCoherentEnableBit, true, false));
EXPECT_TRUE(memcmp(&expectedCmd, cmd, lriSize) == 0);
}
struct Gen11CoherencyProgramingTest : public Gen11CoherencyRequirements {
void SetUp() override {
Gen11CoherencyRequirements::SetUp();
startOffset = csr->commandStream.getUsed();
}
void flushTask(bool coherencyRequired) {
flags.requiresCoherency = coherencyRequired;
auto graphicAlloc = csr->getMemoryManager()->allocateGraphicsMemoryWithProperties(MockAllocationProperties{MemoryConstants::pageSize});
IndirectHeap stream(graphicAlloc);
startOffset = csr->commandStream.getUsed();
csr->flushTask(stream, 0, stream, stream, stream, 0, flags, *device);
csr->getMemoryManager()->freeGraphicsMemory(graphicAlloc);
};
void findMmio(bool expectToBeProgrammed, uint32_t registerAddress) {
HardwareParse hwParser;
hwParser.parseCommands<ICLFamily>(csr->commandStream, startOffset);
bool foundOne = false;
for (auto it = hwParser.cmdList.begin(); it != hwParser.cmdList.end(); it++) {
auto cmd = genCmdCast<MI_LOAD_REGISTER_IMM *>(*it);
if (cmd && cmd->getRegisterOffset() == registerAddress) {
EXPECT_FALSE(foundOne);
foundOne = true;
}
}
EXPECT_EQ(expectToBeProgrammed, foundOne);
};
void findMmio(bool expectToBeProgrammed) {
findMmio(expectToBeProgrammed, gen11HdcModeRegister::address);
}
size_t startOffset;
};
GEN11TEST_F(Gen11CoherencyProgramingTest, givenCsrWhenFlushFirstTaskWithoutCoherencyRequiredThenProgramMmio) {
flushTask(false);
findMmio(true);
}
GEN11TEST_F(Gen11CoherencyProgramingTest, givenCsrWhenFlushFirstTaskWithCoherencyRequiredThenProgramMmio) {
flushTask(true);
findMmio(true);
}
GEN11TEST_F(Gen11CoherencyProgramingTest, givenCsrWithFlushedFirstTaskWithCoherencyRequiredWhenFlushNextTaskWithoutChangingCoherencyRequirementThenDoNotProgramMmio) {
flushTask(true);
flushTask(true);
findMmio(false);
}
GEN11TEST_F(Gen11CoherencyProgramingTest, givenCsrWithFlushedFirstTaskWithoutCoherencyRequiredWhenFlushNextTaskWithoutChangingCoherencyRequirementThenDoNotProgramMmio) {
flushTask(false);
flushTask(false);
findMmio(false);
}
GEN11TEST_F(Gen11CoherencyProgramingTest, givenCsrWithFlushedFirstTaskWithCoherencyRequiredWhenFlushNextTaskWithChangingCoherencyRequirementThenProgramMmio) {
flushTask(true);
flushTask(false);
findMmio(true);
}
GEN11TEST_F(Gen11CoherencyProgramingTest, givenCsrWithFlushedFirstTaskWithoutCoherencyRequiredWhenFlushNextTaskWithChangingCoherencyRequirementThenProgramMmio) {
flushTask(false);
flushTask(true);
findMmio(true);
}

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/command_queue/command_queue_hw.h"
#include "runtime/command_stream/command_stream_receiver.h"
#include "runtime/command_stream/linear_stream.h"
#include "test.h"
#include "unit_tests/fixtures/device_fixture.h"
#include "unit_tests/helpers/hw_parse.h"
#include "unit_tests/mocks/mock_command_queue.h"
#include "unit_tests/mocks/mock_context.h"
#include "unit_tests/mocks/mock_csr.h"
#include "unit_tests/mocks/mock_event.h"
#include "unit_tests/mocks/mock_kernel.h"
#include "gtest/gtest.h"
#include "reg_configs_common.h"
using namespace NEO;
#include "unit_tests/command_stream/command_stream_receiver_hw_tests.inl"
using CommandStreamReceiverHwTestGen11 = CommandStreamReceiverHwTest<ICLFamily>;
GEN11TEST_F(CommandStreamReceiverHwTestGen11, GivenKernelWithSlmWhenPreviousNOSLML3WasSentThenProgramL3WithSLML3Config) {
givenKernelWithSlmWhenPreviousNOSLML3WasSentThenProgramL3WithSLML3ConfigImpl();
}
GEN11TEST_F(CommandStreamReceiverHwTestGen11, GivenBlockedKernelWithSlmWhenPreviousNOSLML3WasSentThenProgramL3WithSLML3ConfigAfterUnblocking) {
givenBlockedKernelWithSlmWhenPreviousNOSLML3WasSentThenProgramL3WithSLML3ConfigAfterUnblockingImpl();
}
GEN11TEST_F(CommandStreamReceiverHwTestGen11, whenProgrammingMiSemaphoreWaitThenSetRegisterPollModeMemoryPoll) {
using MI_SEMAPHORE_WAIT = typename FamilyType::MI_SEMAPHORE_WAIT;
MI_SEMAPHORE_WAIT miSemaphoreWait = FamilyType::cmdInitMiSemaphoreWait;
EXPECT_EQ(MI_SEMAPHORE_WAIT::REGISTER_POLL_MODE::REGISTER_POLL_MODE_MEMORY_POLL, miSemaphoreWait.getRegisterPollMode());
}

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/command_queue/command_queue_hw.h"
#include "test.h"
#include "unit_tests/fixtures/device_fixture.h"
#include "unit_tests/helpers/hw_parse.h"
#include "unit_tests/helpers/static_size3.h"
#include "unit_tests/mocks/mock_kernel.h"
#include "reg_configs_common.h"
namespace NEO {
using Gen11EnqueueTest = Test<DeviceFixture>;
GEN11TEST_F(Gen11EnqueueTest, givenKernelRequiringIndependentForwardProgressWhenKernelIsSubmittedThenDefaultPolicyIsProgrammed) {
MockContext mc;
CommandQueueHw<FamilyType> cmdQ{&mc, pDevice, 0};
MockKernelWithInternals mockKernel(*pDevice);
mockKernel.executionEnvironment.SubgroupIndependentForwardProgressRequired = true;
cmdQ.enqueueKernel(mockKernel.mockKernel, 1, nullptr, StatickSize3<1, 1, 1>(), nullptr, 0, nullptr, nullptr);
HardwareParse hwParser;
hwParser.parseCommands<FamilyType>(cmdQ);
auto cmd = findMmioCmd<FamilyType>(hwParser.cmdList.begin(), hwParser.cmdList.end(), RowChickenReg4::address);
ASSERT_NE(nullptr, cmd);
EXPECT_EQ(RowChickenReg4::regDataForArbitrationPolicy[PreambleHelper<FamilyType>::getDefaultThreadArbitrationPolicy()], cmd->getDataDword());
EXPECT_EQ(1U, countMmio<FamilyType>(hwParser.cmdList.begin(), hwParser.cmdList.end(), RowChickenReg4::address));
}
GEN11TEST_F(Gen11EnqueueTest, givenKernelNotRequiringIndependentForwardProgressWhenKernelIsSubmittedThenAgeBasedPolicyIsProgrammed) {
MockContext mc;
CommandQueueHw<FamilyType> cmdQ{&mc, pDevice, 0};
MockKernelWithInternals mockKernel(*pDevice);
mockKernel.executionEnvironment.SubgroupIndependentForwardProgressRequired = false;
cmdQ.enqueueKernel(mockKernel.mockKernel, 1, nullptr, StatickSize3<1, 1, 1>(), nullptr, 0, nullptr, nullptr);
HardwareParse hwParser;
hwParser.parseCommands<FamilyType>(cmdQ);
auto cmd = findMmioCmd<FamilyType>(hwParser.cmdList.begin(), hwParser.cmdList.end(), RowChickenReg4::address);
ASSERT_NE(nullptr, cmd);
EXPECT_EQ(RowChickenReg4::regDataForArbitrationPolicy[ThreadArbitrationPolicy::AgeBased], cmd->getDataDword());
EXPECT_EQ(1U, countMmio<FamilyType>(hwParser.cmdList.begin(), hwParser.cmdList.end(), RowChickenReg4::address));
}
} // namespace NEO

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/helpers/pipeline_select_helper.h"
#include "runtime/helpers/preamble.h"
#include "test.h"
#include "unit_tests/fixtures/media_kernel_fixture.h"
using namespace NEO;
typedef MediaKernelFixture<HelloWorldFixtureFactory> MediaKernelTest;
auto expectedMask = pipelineSelectEnablePipelineSelectMaskBits |
pipelineSelectMediaSamplerDopClockGateMaskBits |
pipelineSelectMediaSamplerPowerClockGateMaskBits;
GEN11TEST_F(MediaKernelTest, givenGen11CsrWhenEnqueueBlockedVmeKernelFirstTimeThenProgramPipelineSelectionAndMediaSampler) {
typedef typename ICLFamily::PIPELINE_SELECT PIPELINE_SELECT;
cl_uint workDim = 1;
size_t globalWorkOffset[3] = {0, 0, 0};
size_t globalWorkSize[3] = {1, 1, 1};
UserEvent userEvent(context);
cl_event blockedEvent = &userEvent;
auto retVal = pCmdQ->enqueueKernel(
pVmeKernel,
workDim,
globalWorkOffset,
globalWorkSize,
nullptr,
1,
&blockedEvent,
nullptr);
ASSERT_EQ(CL_SUCCESS, retVal);
userEvent.setStatus(CL_COMPLETE);
parseCommands<ICLFamily>(*pCmdQ);
ASSERT_NE(cmdPipelineSelect, nullptr);
auto *pCmd = genCmdCast<PIPELINE_SELECT *>(cmdPipelineSelect);
auto expectedPipelineSelection = PIPELINE_SELECT::PIPELINE_SELECTION_GPGPU;
EXPECT_EQ(expectedMask, pCmd->getMaskBits());
EXPECT_EQ(expectedPipelineSelection, pCmd->getPipelineSelection());
EXPECT_FALSE(pCmd->getMediaSamplerDopClockGateEnable());
}
GEN11TEST_F(MediaKernelTest, givenGen11CsrWhenEnqueueBlockedNonVmeKernelFirstTimeThenProgramPipelineSelectionAndMediaSampler) {
typedef typename ICLFamily::PIPELINE_SELECT PIPELINE_SELECT;
cl_uint workDim = 1;
size_t globalWorkOffset[3] = {0, 0, 0};
size_t globalWorkSize[3] = {1, 1, 1};
UserEvent userEvent(context);
cl_event blockedEvent = &userEvent;
auto retVal = pCmdQ->enqueueKernel(
pKernel,
workDim,
globalWorkOffset,
globalWorkSize,
nullptr,
1,
&blockedEvent,
nullptr);
ASSERT_EQ(CL_SUCCESS, retVal);
userEvent.setStatus(CL_COMPLETE);
parseCommands<ICLFamily>(*pCmdQ);
ASSERT_NE(cmdPipelineSelect, nullptr);
auto *pCmd = genCmdCast<PIPELINE_SELECT *>(cmdPipelineSelect);
auto expectedPipelineSelection = PIPELINE_SELECT::PIPELINE_SELECTION_GPGPU;
EXPECT_EQ(expectedMask, pCmd->getMaskBits());
EXPECT_EQ(expectedPipelineSelection, pCmd->getPipelineSelection());
EXPECT_TRUE(pCmd->getMediaSamplerDopClockGateEnable());
}
GEN11TEST_F(MediaKernelTest, givenGen11CsrWhenEnqueueVmeKernelFirstTimeThenProgramPipelineSelectionAndMediaSampler) {
typedef typename ICLFamily::PIPELINE_SELECT PIPELINE_SELECT;
enqueueVmeKernel<ICLFamily>();
auto numCommands = getCommandsList<PIPELINE_SELECT>().size();
EXPECT_EQ(1u, numCommands);
auto pCmd = getCommand<PIPELINE_SELECT>();
auto expectedPipelineSelection = PIPELINE_SELECT::PIPELINE_SELECTION_GPGPU;
EXPECT_EQ(expectedMask, pCmd->getMaskBits());
EXPECT_EQ(expectedPipelineSelection, pCmd->getPipelineSelection());
EXPECT_FALSE(pCmd->getMediaSamplerDopClockGateEnable());
EXPECT_EQ(1u, pCmd->getMediaSamplerPowerClockGateDisable());
}
GEN11TEST_F(MediaKernelTest, givenGen11CsrWhenEnqueueNonVmeKernelFirstTimeThenProgramPipelineSelectionAndMediaSampler) {
typedef typename ICLFamily::PIPELINE_SELECT PIPELINE_SELECT;
enqueueRegularKernel<ICLFamily>();
auto numCommands = getCommandsList<PIPELINE_SELECT>().size();
EXPECT_EQ(1u, numCommands);
auto pCmd = getCommand<PIPELINE_SELECT>();
auto expectedPipelineSelection = PIPELINE_SELECT::PIPELINE_SELECTION_GPGPU;
EXPECT_EQ(expectedMask, pCmd->getMaskBits());
EXPECT_EQ(expectedPipelineSelection, pCmd->getPipelineSelection());
EXPECT_TRUE(pCmd->getMediaSamplerDopClockGateEnable());
EXPECT_EQ(0u, pCmd->getMediaSamplerPowerClockGateDisable());
}
GEN11TEST_F(MediaKernelTest, givenGen11CsrWhenEnqueueVmeKernelTwiceThenProgramPipelineSelectOnce) {
typedef typename ICLFamily::PIPELINE_SELECT PIPELINE_SELECT;
enqueueVmeKernel<ICLFamily>();
auto numCommands = getCommandsList<PIPELINE_SELECT>().size();
EXPECT_EQ(1u, numCommands);
}
GEN11TEST_F(MediaKernelTest, givenGen11CsrWhenEnqueueNonVmeKernelTwiceThenProgramPipelineSelectOnce) {
typedef typename ICLFamily::PIPELINE_SELECT PIPELINE_SELECT;
enqueueVmeKernel<ICLFamily>();
auto numCommands = getCommandsList<PIPELINE_SELECT>().size();
EXPECT_EQ(1u, numCommands);
}
GEN11TEST_F(MediaKernelTest, givenGen11CsrWhenEnqueueVmeKernelAfterNonVmeKernelThenProgramPipelineSelectionAndMediaSamplerTwice) {
typedef typename ICLFamily::PIPELINE_SELECT PIPELINE_SELECT;
enqueueRegularKernel<ICLFamily>();
enqueueVmeKernel<ICLFamily>();
auto commands = getCommandsList<PIPELINE_SELECT>();
EXPECT_EQ(2u, commands.size());
auto pCmd = static_cast<PIPELINE_SELECT *>(commands.back());
EXPECT_EQ(expectedMask, pCmd->getMaskBits());
EXPECT_FALSE(pCmd->getMediaSamplerDopClockGateEnable());
EXPECT_EQ(1u, pCmd->getMediaSamplerPowerClockGateDisable());
}
GEN11TEST_F(MediaKernelTest, givenGen11CsrWhenEnqueueNonVmeKernelAfterVmeKernelThenProgramProgramPipelineSelectionAndMediaSamplerTwice) {
typedef typename ICLFamily::PIPELINE_SELECT PIPELINE_SELECT;
enqueueVmeKernel<ICLFamily>();
enqueueRegularKernel<ICLFamily>();
auto commands = getCommandsList<PIPELINE_SELECT>();
EXPECT_EQ(2u, commands.size());
auto pCmd = static_cast<PIPELINE_SELECT *>(commands.back());
EXPECT_EQ(expectedMask, pCmd->getMaskBits());
EXPECT_TRUE(pCmd->getMediaSamplerDopClockGateEnable());
EXPECT_EQ(0u, pCmd->getMediaSamplerPowerClockGateDisable());
}
ICLLPTEST_F(MediaKernelTest, givenIcllpDefaultLastVmeSubsliceConfigIsFalse) {
auto csr = static_cast<UltCommandStreamReceiver<FamilyType> *>(&pDevice->getCommandStreamReceiver());
EXPECT_FALSE(csr->lastVmeSubslicesConfig);
}
ICLLPTEST_F(MediaKernelTest, givenIcllpCSRWhenEnqueueVmeKernelThenVmeSubslicesConfigChangesToTrue) {
auto csr = static_cast<UltCommandStreamReceiver<FamilyType> *>(&pDevice->getCommandStreamReceiver());
enqueueVmeKernel<FamilyType>();
EXPECT_TRUE(csr->lastVmeSubslicesConfig);
}
ICLLPTEST_F(MediaKernelTest, givenIcllpCSRWhenEnqueueRegularKernelAfterVmeKernelThenVmeSubslicesConfigChangesToFalse) {
auto csr = static_cast<UltCommandStreamReceiver<FamilyType> *>(&pDevice->getCommandStreamReceiver());
enqueueVmeKernel<FamilyType>();
enqueueRegularKernel<FamilyType>();
EXPECT_FALSE(csr->lastVmeSubslicesConfig);
}
ICLLPTEST_F(MediaKernelTest, givenIcllpCSRWhenEnqueueRegularKernelThenVmeSubslicesConfigDoesntChangeToTrue) {
auto csr = static_cast<UltCommandStreamReceiver<FamilyType> *>(&pDevice->getCommandStreamReceiver());
enqueueRegularKernel<FamilyType>();
EXPECT_FALSE(csr->lastVmeSubslicesConfig);
}
ICLLPTEST_F(MediaKernelTest, givenIcllpCSRWhenEnqueueRegularKernelAfterRegularKernelThenVmeSubslicesConfigDoesntChangeToTrue) {
auto csr = static_cast<UltCommandStreamReceiver<FamilyType> *>(&pDevice->getCommandStreamReceiver());
enqueueRegularKernel<FamilyType>();
enqueueRegularKernel<FamilyType>();
EXPECT_FALSE(csr->lastVmeSubslicesConfig);
}
ICLLPTEST_F(MediaKernelTest, givenIcllpCSRWhenEnqueueVmeKernelAfterRegularKernelThenVmeSubslicesConfigChangesToTrue) {
auto csr = static_cast<UltCommandStreamReceiver<FamilyType> *>(&pDevice->getCommandStreamReceiver());
enqueueRegularKernel<FamilyType>();
enqueueVmeKernel<FamilyType>();
EXPECT_TRUE(csr->lastVmeSubslicesConfig);
}
ICLLPTEST_F(MediaKernelTest, icllpCmdSizeForVme) {
typedef typename FamilyType::MI_LOAD_REGISTER_IMM MI_LOAD_REGISTER_IMM;
typedef typename FamilyType::PIPE_CONTROL PIPE_CONTROL;
auto csr = static_cast<UltCommandStreamReceiver<FamilyType> *>(&pDevice->getCommandStreamReceiver());
size_t programVmeCmdSize = sizeof(MI_LOAD_REGISTER_IMM) + 2 * sizeof(PIPE_CONTROL);
EXPECT_EQ(0u, csr->getCmdSizeForMediaSampler(false));
EXPECT_EQ(programVmeCmdSize, csr->getCmdSizeForMediaSampler(true));
}

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "unit_tests/helpers/get_gpgpu_engines_tests.inl"
#include "unit_tests/helpers/hw_helper_tests.h"
using HwHelperTestGen11 = HwHelperTest;
GEN11TEST_F(HwHelperTestGen11, getMaxBarriersPerSliceReturnsCorrectSize) {
auto &helper = HwHelper::get(renderCoreFamily);
EXPECT_EQ(32u, helper.getMaxBarrierRegisterPerSlice());
}
GEN11TEST_F(HwHelperTestGen11, setCapabilityCoherencyFlag) {
auto &helper = HwHelper::get(renderCoreFamily);
bool coherency = false;
helper.setCapabilityCoherencyFlag(&hwInfoHelper.hwInfo, coherency);
EXPECT_TRUE(coherency);
}
GEN11TEST_F(HwHelperTestGen11, setupPreemptionRegisters) {
auto &helper = HwHelper::get(renderCoreFamily);
bool preemption = false;
preemption = helper.setupPreemptionRegisters(&hwInfoHelper.hwInfo, preemption);
EXPECT_FALSE(preemption);
preemption = true;
preemption = helper.setupPreemptionRegisters(&hwInfoHelper.hwInfo, preemption);
EXPECT_FALSE(preemption);
}
GEN11TEST_F(HwHelperTestGen11, adjustDefaultEngineType) {
auto engineType = hwInfoHelper.hwInfo.capabilityTable.defaultEngineType;
auto &helper = HwHelper::get(renderCoreFamily);
helper.adjustDefaultEngineType(&hwInfoHelper.hwInfo);
EXPECT_EQ(engineType, hwInfoHelper.hwInfo.capabilityTable.defaultEngineType);
}
GEN11TEST_F(HwHelperTestGen11, givenGen11PlatformWhenSetupHardwareCapabilitiesIsCalledThenDefaultImplementationIsUsed) {
auto &helper = HwHelper::get(renderCoreFamily);
// Test default method implementation
testDefaultImplementationOfSetupHardwareCapabilities(helper, hwInfoHelper.hwInfo);
}
GEN11TEST_F(HwHelperTestGen11, whenGetConfigureAddressSpaceModeThenReturnZero) {
auto &helper = HwHelper::get(renderCoreFamily);
EXPECT_EQ(0u, helper.getConfigureAddressSpaceMode());
}
GEN11TEST_F(HwHelperTestGen11, whenGetGpgpuEnginesThenReturnTwoRcsEngines) {
whenGetGpgpuEnginesThenReturnTwoRcsEngines<FamilyType>();
EXPECT_EQ(2u, pDevice->getExecutionEnvironment()->commandStreamReceivers[0].size());
}

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#
# Copyright (C) 2018-2019 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
if(TESTS_ICLLP)
set(IGDRCL_SRCS_tests_gen11_icllp
${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
${CMAKE_CURRENT_SOURCE_DIR}/test_hw_info_config_icllp.cpp
)
target_sources(igdrcl_tests PRIVATE ${IGDRCL_SRCS_tests_gen11_icllp})
add_subdirectories()
endif()

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#
# Copyright (C) 2018-2019 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
set(IGDRCL_SRCS_tests_gen11_icllp_linux
${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
${CMAKE_CURRENT_SOURCE_DIR}/hw_info_config_tests_icllp.cpp
)
if(UNIX)
target_sources(igdrcl_tests PRIVATE ${IGDRCL_SRCS_tests_gen11_icllp_linux})
add_subdirectory(dll)
endif()

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#
# Copyright (C) 2018-2019 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
set(IGDRCL_SRCS_linux_dll_tests_gen11_icllp
${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
${CMAKE_CURRENT_SOURCE_DIR}/device_id_tests_icllp.cpp
)
target_sources(igdrcl_linux_dll_tests PRIVATE ${IGDRCL_SRCS_linux_dll_tests_gen11_icllp})

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/os_interface/linux/drm_neo.h"
#include "test.h"
#include "hw_cmds.h"
#include <array>
using namespace NEO;
TEST(IcllpDeviceIdTest, supportedDeviceId) {
std::array<DeviceDescriptor, 9> expectedDescriptors = {{
{IICL_LP_1x1x8_ULT_DEVICE_A0_ID, &ICLLP_1x1x8::hwInfo, &ICLLP_1x1x8::setupHardwareInfo, GTTYPE_GT1},
{IICL_LP_1x4x8_ULT_DEVICE_F0_ID, &ICLLP_1x4x8::hwInfo, &ICLLP_1x4x8::setupHardwareInfo, GTTYPE_GT1},
{IICL_LP_1x4x8_ULX_DEVICE_F0_ID, &ICLLP_1x4x8::hwInfo, &ICLLP_1x4x8::setupHardwareInfo, GTTYPE_GT1},
{IICL_LP_GT1_MOB_DEVICE_F0_ID, &ICLLP_1x4x8::hwInfo, &ICLLP_1x4x8::setupHardwareInfo, GTTYPE_GT1},
{IICL_LP_1x6x8_ULX_DEVICE_F0_ID, &ICLLP_1x6x8::hwInfo, &ICLLP_1x6x8::setupHardwareInfo, GTTYPE_GT1},
{IICL_LP_1x6x8_ULT_DEVICE_F0_ID, &ICLLP_1x6x8::hwInfo, &ICLLP_1x6x8::setupHardwareInfo, GTTYPE_GT1},
{IICL_LP_1x8x8_SUPERSKU_DEVICE_F0_ID, &ICLLP_1x8x8::hwInfo, &ICLLP_1x8x8::setupHardwareInfo, GTTYPE_GT2},
{IICL_LP_1x8x8_ULT_DEVICE_F0_ID, &ICLLP_1x8x8::hwInfo, &ICLLP_1x8x8::setupHardwareInfo, GTTYPE_GT2},
{IICL_LP_1x8x8_ULX_DEVICE_F0_ID, &ICLLP_1x8x8::hwInfo, &ICLLP_1x8x8::setupHardwareInfo, GTTYPE_GT2},
}};
auto compareStructs = [](const DeviceDescriptor *first, const DeviceDescriptor *second) {
return first->deviceId == second->deviceId && first->pHwInfo == second->pHwInfo &&
first->setupHardwareInfo == second->setupHardwareInfo && first->eGtType == second->eGtType;
};
size_t startIndex = 0;
while (!compareStructs(&expectedDescriptors[0], &deviceDescriptorTable[startIndex]) &&
deviceDescriptorTable[startIndex].deviceId != 0) {
startIndex++;
};
EXPECT_NE(0u, deviceDescriptorTable[startIndex].deviceId);
for (auto &expected : expectedDescriptors) {
EXPECT_TRUE(compareStructs(&expected, &deviceDescriptorTable[startIndex]));
startIndex++;
}
}

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "unit_tests/helpers/gtest_helpers.h"
#include "unit_tests/os_interface/linux/hw_info_config_linux_tests.h"
using namespace NEO;
using namespace std;
struct HwInfoConfigTestLinuxIcllp : HwInfoConfigTestLinux {
void SetUp() override {
HwInfoConfigTestLinux::SetUp();
drm->StoredDeviceID = IICL_LP_GT1_MOB_DEVICE_F0_ID;
drm->setGtType(GTTYPE_GT1);
}
};
ICLLPTEST_F(HwInfoConfigTestLinuxIcllp, configureHwInfo) {
auto hwInfoConfig = HwInfoConfig::get(productFamily);
int ret = hwInfoConfig->configureHwInfo(pInHwInfo, &outHwInfo, osInterface);
EXPECT_EQ(0, ret);
EXPECT_EQ((unsigned short)drm->StoredDeviceID, outHwInfo.pPlatform->usDeviceID);
EXPECT_EQ((unsigned short)drm->StoredDeviceRevID, outHwInfo.pPlatform->usRevId);
EXPECT_EQ((uint32_t)drm->StoredEUVal, outHwInfo.pSysInfo->EUCount);
EXPECT_EQ((uint32_t)drm->StoredSSVal, outHwInfo.pSysInfo->SubSliceCount);
EXPECT_EQ(1u, outHwInfo.pSysInfo->SliceCount);
EXPECT_EQ(aub_stream::ENGINE_RCS, outHwInfo.capabilityTable.defaultEngineType);
EXPECT_EQ(GTTYPE_GT1, outHwInfo.pPlatform->eGTType);
EXPECT_TRUE(outHwInfo.pSkuTable->ftrGT1);
EXPECT_FALSE(outHwInfo.pSkuTable->ftrGT1_5);
EXPECT_FALSE(outHwInfo.pSkuTable->ftrGT2);
EXPECT_FALSE(outHwInfo.pSkuTable->ftrGT3);
EXPECT_FALSE(outHwInfo.pSkuTable->ftrGT4);
EXPECT_FALSE(outHwInfo.pSkuTable->ftrGTA);
EXPECT_FALSE(outHwInfo.pSkuTable->ftrGTC);
EXPECT_FALSE(outHwInfo.pSkuTable->ftrGTX);
EXPECT_TRUE(outHwInfo.pSkuTable->ftrTileY);
}
ICLLPTEST_F(HwInfoConfigTestLinuxIcllp, negative) {
auto hwInfoConfig = HwInfoConfig::get(productFamily);
drm->StoredRetValForDeviceID = -1;
int ret = hwInfoConfig->configureHwInfo(pInHwInfo, &outHwInfo, osInterface);
EXPECT_EQ(-1, ret);
ReleaseOutHwInfoStructs();
drm->StoredRetValForDeviceID = 0;
drm->StoredRetValForDeviceRevID = -1;
ret = hwInfoConfig->configureHwInfo(pInHwInfo, &outHwInfo, osInterface);
EXPECT_EQ(-1, ret);
ReleaseOutHwInfoStructs();
drm->StoredRetValForDeviceRevID = 0;
drm->StoredRetValForEUVal = -1;
ret = hwInfoConfig->configureHwInfo(pInHwInfo, &outHwInfo, osInterface);
EXPECT_EQ(-1, ret);
ReleaseOutHwInfoStructs();
drm->StoredRetValForEUVal = 0;
drm->StoredRetValForSSVal = -1;
ret = hwInfoConfig->configureHwInfo(pInHwInfo, &outHwInfo, osInterface);
EXPECT_EQ(-1, ret);
}
using IcllpHwInfoTests = ::testing::Test;
ICLLPTEST_F(IcllpHwInfoTests, icllp1x8x8systemInfo) {
GT_SYSTEM_INFO requestedGtSystemInfo = {};
GT_SYSTEM_INFO expectedGtSystemInfo = {};
FeatureTable featureTable = {};
expectedGtSystemInfo.EUCount = 63;
expectedGtSystemInfo.ThreadCount = 63 * ICLLP::threadsPerEu;
expectedGtSystemInfo.SliceCount = 1;
expectedGtSystemInfo.SubSliceCount = 8;
expectedGtSystemInfo.L3CacheSizeInKb = 3072;
expectedGtSystemInfo.L3BankCount = 8;
expectedGtSystemInfo.MaxFillRate = 16;
expectedGtSystemInfo.TotalVsThreads = 336;
expectedGtSystemInfo.TotalHsThreads = 336;
expectedGtSystemInfo.TotalDsThreads = 336;
expectedGtSystemInfo.TotalGsThreads = 336;
expectedGtSystemInfo.TotalPsThreadsWindowerRange = 64;
expectedGtSystemInfo.CsrSizeInMb = 8;
expectedGtSystemInfo.MaxEuPerSubSlice = ICLLP::maxEuPerSubslice;
expectedGtSystemInfo.MaxSlicesSupported = ICLLP::maxSlicesSupported;
expectedGtSystemInfo.MaxSubSlicesSupported = ICLLP::maxSubslicesSupported;
expectedGtSystemInfo.IsL3HashModeEnabled = false;
expectedGtSystemInfo.IsDynamicallyPopulated = false;
ICLLP_1x8x8::setupHardwareInfo(&requestedGtSystemInfo, &featureTable, false);
EXPECT_TRUE(memcmp(&requestedGtSystemInfo, &expectedGtSystemInfo, sizeof(GT_SYSTEM_INFO)) == 0);
}
ICLLPTEST_F(IcllpHwInfoTests, icllp1x4x8systemInfo) {
GT_SYSTEM_INFO requestedGtSystemInfo = {};
GT_SYSTEM_INFO expectedGtSystemInfo = {};
FeatureTable featureTable = {};
expectedGtSystemInfo.EUCount = 31;
expectedGtSystemInfo.ThreadCount = 31 * ICLLP::threadsPerEu;
expectedGtSystemInfo.SliceCount = 1;
expectedGtSystemInfo.SubSliceCount = 4;
expectedGtSystemInfo.L3CacheSizeInKb = 2304;
expectedGtSystemInfo.L3BankCount = 6;
expectedGtSystemInfo.MaxFillRate = 8;
expectedGtSystemInfo.TotalVsThreads = 364;
expectedGtSystemInfo.TotalHsThreads = 224;
expectedGtSystemInfo.TotalDsThreads = 364;
expectedGtSystemInfo.TotalGsThreads = 224;
expectedGtSystemInfo.TotalPsThreadsWindowerRange = 128;
expectedGtSystemInfo.CsrSizeInMb = 5;
expectedGtSystemInfo.MaxEuPerSubSlice = ICLLP::maxEuPerSubslice;
expectedGtSystemInfo.MaxSlicesSupported = 1;
expectedGtSystemInfo.MaxSubSlicesSupported = 4;
expectedGtSystemInfo.IsL3HashModeEnabled = false;
expectedGtSystemInfo.IsDynamicallyPopulated = false;
ICLLP_1x4x8::setupHardwareInfo(&requestedGtSystemInfo, &featureTable, false);
EXPECT_TRUE(memcmp(&requestedGtSystemInfo, &expectedGtSystemInfo, sizeof(GT_SYSTEM_INFO)) == 0);
}
ICLLPTEST_F(IcllpHwInfoTests, icllp1x6x8systemInfo) {
GT_SYSTEM_INFO requestedGtSystemInfo = {};
GT_SYSTEM_INFO expectedGtSystemInfo = {};
FeatureTable featureTable = {};
expectedGtSystemInfo.EUCount = 47;
expectedGtSystemInfo.ThreadCount = 47 * ICLLP::threadsPerEu;
expectedGtSystemInfo.SliceCount = 1;
expectedGtSystemInfo.SubSliceCount = 6;
expectedGtSystemInfo.L3CacheSizeInKb = 2304;
expectedGtSystemInfo.L3BankCount = 6;
expectedGtSystemInfo.MaxFillRate = 8;
expectedGtSystemInfo.TotalVsThreads = 364;
expectedGtSystemInfo.TotalHsThreads = 224;
expectedGtSystemInfo.TotalDsThreads = 364;
expectedGtSystemInfo.TotalGsThreads = 224;
expectedGtSystemInfo.TotalPsThreadsWindowerRange = 128;
expectedGtSystemInfo.CsrSizeInMb = 5;
expectedGtSystemInfo.MaxEuPerSubSlice = ICLLP::maxEuPerSubslice;
expectedGtSystemInfo.MaxSlicesSupported = 1;
expectedGtSystemInfo.MaxSubSlicesSupported = 4;
expectedGtSystemInfo.IsL3HashModeEnabled = false;
expectedGtSystemInfo.IsDynamicallyPopulated = false;
ICLLP_1x6x8::setupHardwareInfo(&requestedGtSystemInfo, &featureTable, false);
EXPECT_TRUE(memcmp(&requestedGtSystemInfo, &expectedGtSystemInfo, sizeof(GT_SYSTEM_INFO)) == 0);
}
ICLLPTEST_F(IcllpHwInfoTests, icllp1x1x8systemInfo) {
GT_SYSTEM_INFO requestedGtSystemInfo = {};
GT_SYSTEM_INFO expectedGtSystemInfo = {};
FeatureTable featureTable = {};
expectedGtSystemInfo.EUCount = 8;
expectedGtSystemInfo.ThreadCount = 8 * ICLLP::threadsPerEu;
expectedGtSystemInfo.SliceCount = 1;
expectedGtSystemInfo.SubSliceCount = 1;
expectedGtSystemInfo.L3CacheSizeInKb = 2304;
expectedGtSystemInfo.L3BankCount = 6;
expectedGtSystemInfo.MaxFillRate = 8;
expectedGtSystemInfo.TotalVsThreads = 364;
expectedGtSystemInfo.TotalHsThreads = 224;
expectedGtSystemInfo.TotalDsThreads = 364;
expectedGtSystemInfo.TotalGsThreads = 224;
expectedGtSystemInfo.TotalPsThreadsWindowerRange = 128;
expectedGtSystemInfo.CsrSizeInMb = 5;
expectedGtSystemInfo.MaxEuPerSubSlice = ICLLP::maxEuPerSubslice;
expectedGtSystemInfo.MaxSlicesSupported = 1;
expectedGtSystemInfo.MaxSubSlicesSupported = 4;
expectedGtSystemInfo.IsL3HashModeEnabled = false;
expectedGtSystemInfo.IsDynamicallyPopulated = false;
ICLLP_1x1x8::setupHardwareInfo(&requestedGtSystemInfo, &featureTable, false);
EXPECT_TRUE(memcmp(&requestedGtSystemInfo, &expectedGtSystemInfo, sizeof(GT_SYSTEM_INFO)) == 0);
}

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "test.h"
using namespace NEO;
TEST(IcllpHwInfoConfig, givenHwInfoConfigStringThenAfterSetupResultingHwInfoIsCorrect) {
if (IGFX_ICELAKE_LP != productFamily) {
return;
}
GT_SYSTEM_INFO gInfo = {0};
FeatureTable fTable;
std::string strConfig = "1x8x8";
hardwareInfoSetup[productFamily](&gInfo, &fTable, false, strConfig);
EXPECT_EQ(gInfo.SliceCount, 1u);
EXPECT_EQ(gInfo.SubSliceCount, 8u);
EXPECT_EQ(gInfo.EUCount, 63u);
strConfig = "1x4x8";
gInfo = {0};
hardwareInfoSetup[productFamily](&gInfo, &fTable, false, strConfig);
EXPECT_EQ(gInfo.SliceCount, 1u);
EXPECT_EQ(gInfo.SubSliceCount, 4u);
EXPECT_EQ(gInfo.EUCount, 31u);
strConfig = "1x6x8";
gInfo = {0};
hardwareInfoSetup[productFamily](&gInfo, &fTable, false, strConfig);
EXPECT_EQ(gInfo.SliceCount, 1u);
EXPECT_EQ(gInfo.SubSliceCount, 6u);
EXPECT_EQ(gInfo.EUCount, 47u);
strConfig = "1x1x8";
gInfo = {0};
hardwareInfoSetup[productFamily](&gInfo, &fTable, false, strConfig);
EXPECT_EQ(gInfo.SliceCount, 1u);
EXPECT_EQ(gInfo.SubSliceCount, 1u);
EXPECT_EQ(gInfo.EUCount, 8u);
strConfig = "default";
gInfo = {0};
hardwareInfoSetup[productFamily](&gInfo, &fTable, false, strConfig);
EXPECT_EQ(gInfo.SliceCount, 1u);
EXPECT_EQ(gInfo.SubSliceCount, 8u);
EXPECT_EQ(gInfo.EUCount, 63u);
strConfig = "erroneous";
gInfo = {0};
EXPECT_ANY_THROW(hardwareInfoSetup[productFamily](&gInfo, &fTable, false, strConfig));
EXPECT_EQ(gInfo.SliceCount, 0u);
EXPECT_EQ(gInfo.SubSliceCount, 0u);
EXPECT_EQ(gInfo.EUCount, 0u);
}

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#
# Copyright (C) 2018-2019 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
set(IGDRCL_SRCS_tests_gen11_icllp_windows
${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
${CMAKE_CURRENT_SOURCE_DIR}/hw_info_config_tests_icllp.cpp
)
if(WIN32)
target_sources(igdrcl_tests PRIVATE ${IGDRCL_SRCS_tests_gen11_icllp_windows})
endif()

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/os_interface/windows/os_interface.h"
#include "unit_tests/os_interface/windows/hw_info_config_win_tests.h"
using namespace NEO;
using namespace std;
using HwInfoConfigTestWindowsIcllp = HwInfoConfigTestWindows;
ICLLPTEST_F(HwInfoConfigTestWindowsIcllp, whenCallAdjustPlatformThenDoNothing) {
EXPECT_EQ(IGFX_ICELAKE_LP, productFamily);
auto hwInfoConfig = HwInfoConfig::get(productFamily);
hwInfoConfig->adjustPlatformForProductFamily(&testHwInfo);
int ret = memcmp(outHwInfo.pPlatform, testHwInfo.pPlatform, sizeof(PLATFORM));
EXPECT_EQ(0, ret);
}

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/mem_obj/image.h"
#include "test.h"
#include "unit_tests/fixtures/image_fixture.h"
#include "unit_tests/mocks/mock_context.h"
using namespace NEO;
typedef ICLFamily::RENDER_SURFACE_STATE RENDER_SURFACE_STATE;
struct AppendSurfaceStateParamsTest : public ::testing::Test {
void SetUp() override {
surfaceState = ICLFamily::cmdInitRenderSurfaceState;
EXPECT_EQ(RENDER_SURFACE_STATE::SAMPLE_TAP_DISCARD_DISABLE_DISABLE, surfaceState.getSampleTapDiscardDisable());
imageDesc.image_width = 32;
imageDesc.image_height = 0;
imageDesc.image_depth = 0;
imageDesc.image_array_size = 1;
imageDesc.image_row_pitch = 0;
imageDesc.image_slice_pitch = 0;
imageDesc.num_mip_levels = 0;
imageDesc.num_samples = 0;
imageDesc.mem_object = NULL;
imageDesc.image_type = CL_MEM_OBJECT_IMAGE1D;
flags = CL_MEM_READ_WRITE;
}
void createImage() {
auto surfaceFormat = Image::getSurfaceFormatFromTable(flags, &imageFormat);
EXPECT_NE(nullptr, surfaceFormat);
image.reset(Image::create(&context, flags, surfaceFormat, &imageDesc, nullptr, retVal));
}
cl_int retVal = CL_SUCCESS;
MockContext context;
std::unique_ptr<Image> image;
cl_image_format imageFormat;
cl_image_desc imageDesc;
cl_mem_flags flags;
RENDER_SURFACE_STATE surfaceState;
};
GEN11TEST_F(AppendSurfaceStateParamsTest, givenImageFormatWithoutAlphaChannelWhenAppendSurfaceStateParamsThenTapDiscardConfigDoesntChange) {
imageFormat.image_channel_data_type = CL_FLOAT;
imageFormat.image_channel_order = CL_R;
createImage();
auto imageHw = static_cast<ImageHw<ICLFamily> *>(image.get());
imageHw->appendSurfaceStateParams(&surfaceState);
bool tapDiscardConfigChanged = RENDER_SURFACE_STATE::SAMPLE_TAP_DISCARD_DISABLE_DISABLE != surfaceState.getSampleTapDiscardDisable();
EXPECT_FALSE(tapDiscardConfigChanged);
}
GEN11TEST_F(AppendSurfaceStateParamsTest, givenImageFormatWithAlphaChannelWhenAppendSurfaceStateParamsThenTapDiscardConfigChanges) {
imageFormat.image_channel_data_type = CL_FLOAT;
imageFormat.image_channel_order = CL_RGBA;
createImage();
auto imageHw = static_cast<ImageHw<ICLFamily> *>(image.get());
imageHw->appendSurfaceStateParams(&surfaceState);
bool tapDiscardConfigChanged = RENDER_SURFACE_STATE::SAMPLE_TAP_DISCARD_DISABLE_DISABLE != surfaceState.getSampleTapDiscardDisable();
EXPECT_TRUE(tapDiscardConfigChanged);
}
typedef ::testing::Test gen11ImageTests;
GEN11TEST_F(gen11ImageTests, givenImageForGen11WhenClearColorParametersAreSetThenSurfaceStateIsNotModified) {
typedef typename FamilyType::RENDER_SURFACE_STATE RENDER_SURFACE_STATE;
MockContext context;
auto image = std::unique_ptr<Image>(ImageHelper<Image1dDefaults>::create(&context));
auto surfaceStateBefore = FamilyType::cmdInitRenderSurfaceState;
auto surfaceStateAfter = FamilyType::cmdInitRenderSurfaceState;
auto imageHw = static_cast<ImageHw<FamilyType> *>(image.get());
EXPECT_EQ(0, memcmp(&surfaceStateBefore, &surfaceStateAfter, sizeof(RENDER_SURFACE_STATE)));
imageHw->setClearColorParams(&surfaceStateAfter, imageHw->getGraphicsAllocation()->getDefaultGmm());
EXPECT_EQ(0, memcmp(&surfaceStateBefore, &surfaceStateAfter, sizeof(RENDER_SURFACE_STATE)));
}

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/helpers/kernel_commands.h"
#include "test.h"
#include "unit_tests/fixtures/device_fixture.h"
#include "unit_tests/mocks/mock_kernel.h"
using namespace NEO;
using Gen11KernelTest = Test<DeviceFixture>;
GEN11TEST_F(Gen11KernelTest, givenKernelWhenCanTransformImagesIsCalledThenReturnsTrue) {
MockKernelWithInternals mockKernel(*pDevice);
auto retVal = mockKernel.mockKernel->Kernel::canTransformImages();
EXPECT_TRUE(retVal);
}
using Gen11KernelCommandsTest = testing::Test;
GEN11TEST_F(Gen11KernelCommandsTest, givenGen11PlatformWhenDoBindingTablePrefetchIsCalledThenReturnsFalse) {
EXPECT_FALSE(KernelCommandsHelper<FamilyType>::doBindingTablePrefetch());
}

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#
# Copyright (C) 2018-2019 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
if(TESTS_LKF)
set(IGDRCL_SRCS_tests_gen11_lkf
${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
${CMAKE_CURRENT_SOURCE_DIR}/test_hw_info_config_lkf.cpp
)
target_sources(igdrcl_tests PRIVATE ${IGDRCL_SRCS_tests_gen11_lkf})
add_subdirectories()
endif()

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#
# Copyright (C) 2018-2019 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
set(IGDRCL_SRCS_tests_gen11_lkf_linux
${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
${CMAKE_CURRENT_SOURCE_DIR}/hw_info_config_tests_lkf.cpp
)
if(UNIX)
target_sources(igdrcl_tests PRIVATE ${IGDRCL_SRCS_tests_gen11_lkf_linux})
add_subdirectory(dll)
endif()

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#
# Copyright (C) 2018-2019 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
set(IGDRCL_SRCS_linux_dll_tests_gen11_lkf
${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
${CMAKE_CURRENT_SOURCE_DIR}/device_id_tests_lkf.cpp
)
target_sources(igdrcl_linux_dll_tests PRIVATE ${IGDRCL_SRCS_linux_dll_tests_gen11_lkf})

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/os_interface/linux/drm_neo.h"
#include "test.h"
#include "hw_cmds.h"
#include <array>
using namespace NEO;
TEST(LkfDeviceIdTest, supportedDeviceId) {
std::array<DeviceDescriptor, 1> expectedDescriptors = {{
{ILKF_1x8x8_DESK_DEVICE_F0_ID, &LKF_1x8x8::hwInfo, &LKF_1x8x8::setupHardwareInfo, GTTYPE_GT1},
}};
auto compareStructs = [](const DeviceDescriptor *first, const DeviceDescriptor *second) {
return first->deviceId == second->deviceId && first->pHwInfo == second->pHwInfo &&
first->setupHardwareInfo == second->setupHardwareInfo && first->eGtType == second->eGtType;
};
size_t startIndex = 0;
while (!compareStructs(&expectedDescriptors[0], &deviceDescriptorTable[startIndex]) &&
deviceDescriptorTable[startIndex].deviceId != 0) {
startIndex++;
};
EXPECT_NE(0u, deviceDescriptorTable[startIndex].deviceId);
for (auto &expected : expectedDescriptors) {
EXPECT_TRUE(compareStructs(&expected, &deviceDescriptorTable[startIndex]));
startIndex++;
}
}

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "unit_tests/helpers/gtest_helpers.h"
#include "unit_tests/os_interface/linux/hw_info_config_linux_tests.h"
using namespace NEO;
struct HwInfoConfigTestLinuxLkf : HwInfoConfigTestLinux {
void SetUp() override {
HwInfoConfigTestLinux::SetUp();
drm->StoredDeviceID = ILKF_1x8x8_DESK_DEVICE_F0_ID;
drm->setGtType(GTTYPE_GT1);
drm->StoredSSVal = 8;
}
};
TEST_F(HwInfoConfigTestLinuxLkf, configureHwInfoLkf) {
auto hwInfoConfig = HwInfoConfigHw<IGFX_LAKEFIELD>::get();
int ret = hwInfoConfig->configureHwInfo(pInHwInfo, &outHwInfo, osInterface);
EXPECT_EQ(0, ret);
EXPECT_EQ((unsigned short)drm->StoredDeviceID, outHwInfo.pPlatform->usDeviceID);
EXPECT_EQ((unsigned short)drm->StoredDeviceRevID, outHwInfo.pPlatform->usRevId);
EXPECT_EQ((uint32_t)drm->StoredEUVal, outHwInfo.pSysInfo->EUCount);
EXPECT_EQ((uint32_t)drm->StoredSSVal, outHwInfo.pSysInfo->SubSliceCount);
EXPECT_EQ(1u, outHwInfo.pSysInfo->SliceCount);
EXPECT_EQ(GTTYPE_GT1, outHwInfo.pPlatform->eGTType);
EXPECT_TRUE(outHwInfo.pSkuTable->ftrGT1);
EXPECT_FALSE(outHwInfo.pSkuTable->ftrGT1_5);
EXPECT_FALSE(outHwInfo.pSkuTable->ftrGT2);
EXPECT_FALSE(outHwInfo.pSkuTable->ftrGT3);
EXPECT_FALSE(outHwInfo.pSkuTable->ftrGT4);
EXPECT_FALSE(outHwInfo.pSkuTable->ftrGTA);
EXPECT_FALSE(outHwInfo.pSkuTable->ftrGTC);
EXPECT_FALSE(outHwInfo.pSkuTable->ftrGTX);
EXPECT_TRUE(outHwInfo.pSkuTable->ftrTileY);
ReleaseOutHwInfoStructs();
}
TEST_F(HwInfoConfigTestLinuxLkf, negative) {
auto hwInfoConfig = HwInfoConfigHw<IGFX_LAKEFIELD>::get();
drm->StoredRetValForDeviceID = -1;
int ret = hwInfoConfig->configureHwInfo(pInHwInfo, &outHwInfo, osInterface);
EXPECT_EQ(-1, ret);
ReleaseOutHwInfoStructs();
drm->StoredRetValForDeviceID = 0;
drm->StoredRetValForDeviceRevID = -1;
ret = hwInfoConfig->configureHwInfo(pInHwInfo, &outHwInfo, osInterface);
EXPECT_EQ(-1, ret);
ReleaseOutHwInfoStructs();
drm->StoredRetValForDeviceRevID = 0;
drm->StoredRetValForEUVal = -1;
ret = hwInfoConfig->configureHwInfo(pInHwInfo, &outHwInfo, osInterface);
EXPECT_EQ(-1, ret);
ReleaseOutHwInfoStructs();
drm->StoredRetValForEUVal = 0;
drm->StoredRetValForSSVal = -1;
ret = hwInfoConfig->configureHwInfo(pInHwInfo, &outHwInfo, osInterface);
EXPECT_EQ(-1, ret);
}
template <typename T>
class LkfHwInfoTests : public ::testing::Test {};
typedef ::testing::Types<LKF_1x8x8> lkfTestTypes;
TYPED_TEST_CASE(LkfHwInfoTests, lkfTestTypes);
TYPED_TEST(LkfHwInfoTests, gtSetupIsCorrect) {
GT_SYSTEM_INFO gtSystemInfo;
FeatureTable featureTable = {};
memset(&gtSystemInfo, 0, sizeof(gtSystemInfo));
TypeParam::setupHardwareInfo(&gtSystemInfo, &featureTable, false);
EXPECT_GT(gtSystemInfo.EUCount, 0u);
EXPECT_GT(gtSystemInfo.ThreadCount, 0u);
EXPECT_GT(gtSystemInfo.SliceCount, 0u);
EXPECT_GT(gtSystemInfo.SubSliceCount, 0u);
EXPECT_GT_VAL(gtSystemInfo.L3CacheSizeInKb, 0u);
EXPECT_EQ(gtSystemInfo.CsrSizeInMb, 8u);
EXPECT_FALSE(gtSystemInfo.IsDynamicallyPopulated);
}

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "test.h"
using namespace NEO;
TEST(LkfHwInfoConfig, givenHwInfoConfigStringThenAfterSetupResultingHwInfoIsCorrect) {
if (IGFX_LAKEFIELD != productFamily) {
return;
}
GT_SYSTEM_INFO gInfo = {0};
FeatureTable fTable;
std::string strConfig = "1x8x8";
hardwareInfoSetup[productFamily](&gInfo, &fTable, false, strConfig);
EXPECT_EQ(gInfo.SliceCount, 1u);
EXPECT_EQ(gInfo.SubSliceCount, 8u);
EXPECT_EQ(gInfo.EUCount, 64u);
strConfig = "default";
gInfo = {0};
hardwareInfoSetup[productFamily](&gInfo, &fTable, false, strConfig);
EXPECT_EQ(gInfo.SliceCount, 1u);
EXPECT_EQ(gInfo.SubSliceCount, 8u);
EXPECT_EQ(gInfo.EUCount, 64u);
strConfig = "erroneous";
gInfo = {0};
EXPECT_ANY_THROW(hardwareInfoSetup[productFamily](&gInfo, &fTable, false, strConfig));
EXPECT_EQ(gInfo.SliceCount, 0u);
EXPECT_EQ(gInfo.SubSliceCount, 0u);
EXPECT_EQ(gInfo.EUCount, 0u);
}

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#
# Copyright (C) 2018-2019 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
set(IGDRCL_SRCS_tests_gen11_lkf_windows
${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
${CMAKE_CURRENT_SOURCE_DIR}/hw_info_config_tests_lkf.cpp
)
if(WIN32)
target_sources(igdrcl_tests PRIVATE ${IGDRCL_SRCS_tests_gen11_lkf_windows})
endif()

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/os_interface/windows/os_interface.h"
#include "unit_tests/os_interface/windows/hw_info_config_win_tests.h"
using namespace NEO;
using HwInfoConfigTestWindowsLkf = HwInfoConfigTestWindows;
LKFTEST_F(HwInfoConfigTestWindowsLkf, whenCallAdjustPlatformThenDoNothing) {
EXPECT_EQ(IGFX_LAKEFIELD, productFamily);
auto hwInfoConfig = HwInfoConfig::get(productFamily);
hwInfoConfig->adjustPlatformForProductFamily(&testHwInfo);
int ret = memcmp(outHwInfo.pPlatform, testHwInfo.pPlatform, sizeof(PLATFORM));
EXPECT_EQ(0, ret);
}

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "unit_tests/helpers/debug_manager_state_restore.h"
#include "unit_tests/source_level_debugger/source_level_debugger_preamble_test.h"
#include "gtest/gtest.h"
using namespace NEO;
typedef ICLFamily GfxFamily;
#include "unit_tests/source_level_debugger/source_level_debugger_preamble_test.inl"
using PreambleTestGen11 = ::testing::Test;
GEN11TEST_F(PreambleTestGen11, givenMidThreadPreemptionAndDebuggingActiveWhenStateSipIsProgrammedThenCorrectSipKernelIsUsed) {
SourceLevelDebuggerPreambleTest<FamilyType>::givenMidThreadPreemptionAndDebuggingActiveWhenStateSipIsProgrammedThenCorrectSipKernelIsUsedTest();
}
GEN11TEST_F(PreambleTestGen11, givenMidThreadPreemptionAndDebuggingActiveWhenPreambleSizeIsQueriedThenCorrecrSizeIsReturned) {
SourceLevelDebuggerPreambleTest<FamilyType>::givenMidThreadPreemptionAndDebuggingActiveWhenPreambleSizeIsQueriedThenCorrecrSizeIsReturnedTest();
}
GEN11TEST_F(PreambleTestGen11, givenPreemptionDisabledAndDebuggingActiveWhenPreambleIsProgrammedThenCorrectSipKernelIsUsed) {
SourceLevelDebuggerPreambleTest<FamilyType>::givenPreemptionDisabledAndDebuggingActiveWhenPreambleIsProgrammedThenCorrectSipKernelIsUsedTest();
}
GEN11TEST_F(PreambleTestGen11, givenPreemptionDisabledAndDebuggingActiveWhenPreambleSizeIsQueriedThenCorrecrSizeIsReturned) {
SourceLevelDebuggerPreambleTest<FamilyType>::givenPreemptionDisabledAndDebuggingActiveWhenPreambleSizeIsQueriedThenCorrecrSizeIsReturnedTest();
}
GEN11TEST_F(PreambleTestGen11, givenMidThreadPreemptionAndDisabledDebuggingWhenPreambleIsProgrammedThenCorrectSipKernelIsUsed) {
SourceLevelDebuggerPreambleTest<FamilyType>::givenMidThreadPreemptionAndDisabledDebuggingWhenPreambleIsProgrammedThenCorrectSipKernelIsUsedTest();
}
GEN11TEST_F(PreambleTestGen11, givenMidThreadPreemptionAndDisabledDebuggingWhenPreambleSizeIsQueriedThenCorrecrSizeIsReturned) {
SourceLevelDebuggerPreambleTest<FamilyType>::givenMidThreadPreemptionAndDisabledDebuggingWhenPreambleSizeIsQueriedThenCorrecrSizeIsReturnedTest();
}
GEN11TEST_F(PreambleTestGen11, givenDisabledPreemptionAndDisabledDebuggingWhenPreambleSizeIsQueriedThenCorrecrSizeIsReturned) {
SourceLevelDebuggerPreambleTest<FamilyType>::givenDisabledPreemptionAndDisabledDebuggingWhenPreambleSizeIsQueriedThenCorrecrSizeIsReturnedTest();
}
GEN11TEST_F(PreambleTestGen11, givenKernelDebuggingActiveAndDisabledPreemptionWhenGetAdditionalCommandsSizeIsCalledThen2MiLoadRegisterImmCmdsAndStateSipAreInlcuded) {
SourceLevelDebuggerPreambleTest<FamilyType>::givenKernelDebuggingActiveAndDisabledPreemptionWhenGetAdditionalCommandsSizeIsCalledThen2MiLoadRegisterImmCmdsAreInlcudedTest();
}

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/command_stream/command_stream_receiver_hw.h"
#include "runtime/gen11/reg_configs.h"
#include "runtime/helpers/hw_helper.h"
#include "test.h"
#include "unit_tests/helpers/debug_manager_state_restore.h"
#include "unit_tests/helpers/hw_parse.h"
#include "unit_tests/mocks/mock_device.h"
using namespace NEO;
struct Gen11MediaSamplerProgramingTest : public ::testing::Test {
typedef typename ICLFamily::MI_LOAD_REGISTER_IMM MI_LOAD_REGISTER_IMM;
typedef typename ICLFamily::PIPE_CONTROL PIPE_CONTROL;
struct myCsr : public CommandStreamReceiverHw<ICLFamily> {
using CommandStreamReceiver::commandStream;
using CommandStreamReceiverHw<ICLFamily>::programMediaSampler;
myCsr(ExecutionEnvironment &executionEnvironment) : CommandStreamReceiverHw<ICLFamily>(executionEnvironment){};
void overrideLastVmeSubliceConfig(bool value) {
lastVmeSubslicesConfig = value;
}
};
void overrideMediaRequest(bool lastVmeConfig, bool mediaSamplerRequired) {
csr->overrideLastVmeSubliceConfig(lastVmeConfig);
flags.mediaSamplerRequired = mediaSamplerRequired;
}
void SetUp() override {
device.reset(MockDevice::createWithNewExecutionEnvironment<MockDevice>(platformDevices[0]));
csr = new myCsr(*device->executionEnvironment);
device->resetCommandStreamReceiver(csr);
stream.reset(new LinearStream(buff, MemoryConstants::pageSize));
}
void programMediaSampler() {
csr->programMediaSampler(*stream, flags);
}
size_t getCmdSize() {
return csr->getCmdSizeForMediaSampler(flags.mediaSamplerRequired);
}
myCsr *csr = nullptr;
std::unique_ptr<MockDevice> device;
DispatchFlags flags = {};
char buff[MemoryConstants::pageSize];
std::unique_ptr<LinearStream> stream;
};
template <typename PIPE_CONTROL>
void setFlushAllCaches(PIPE_CONTROL &pc) {
pc.setDcFlushEnable(true);
pc.setRenderTargetCacheFlushEnable(true);
pc.setInstructionCacheInvalidateEnable(true);
pc.setTextureCacheInvalidationEnable(true);
pc.setPipeControlFlushEnable(true);
pc.setVfCacheInvalidationEnable(true);
pc.setConstantCacheInvalidationEnable(true);
pc.setStateCacheInvalidationEnable(true);
}
ICLLPTEST_F(Gen11MediaSamplerProgramingTest, givenVmeEnableSubsliceDisabledWhenPowerClockStateRegisterEnableThenExpectCorrectCmdValues) {
uint32_t programVmeCmdSize = sizeof(MI_LOAD_REGISTER_IMM) + 2 * sizeof(PIPE_CONTROL);
overrideMediaRequest(false, true);
size_t estimatedCmdSize = getCmdSize();
EXPECT_EQ(programVmeCmdSize, estimatedCmdSize);
auto expectedMiLrCmd = FamilyType::cmdInitLoadRegisterImm;
expectedMiLrCmd.setRegisterOffset(gen11PowerClockStateRegister::address);
auto expectedRegValue = (device->getHardwareInfo().pSysInfo->SubSliceCount / 2) << gen11PowerClockStateRegister::subSliceCountShift;
expectedRegValue |= (gen11PowerClockStateRegister::vmeSliceCount << gen11PowerClockStateRegister::sliceCountShift);
expectedRegValue |= (device->getHardwareInfo().pSysInfo->MaxEuPerSubSlice << gen11PowerClockStateRegister::minEuCountShift);
expectedRegValue |= (device->getHardwareInfo().pSysInfo->MaxEuPerSubSlice << gen11PowerClockStateRegister::maxEuCountShift);
expectedRegValue |= gen11PowerClockStateRegister::enabledValue;
expectedMiLrCmd.setDataDword(expectedRegValue);
programMediaSampler();
ASSERT_EQ(programVmeCmdSize, stream->getUsed());
auto expectedPipeControlCmd = FamilyType::cmdInitPipeControl;
expectedPipeControlCmd.setCommandStreamerStallEnable(0x1);
setFlushAllCaches(expectedPipeControlCmd);
auto pipeControlCmd = reinterpret_cast<PIPE_CONTROL *>(stream->getCpuBase());
EXPECT_EQ(0, memcmp(&expectedPipeControlCmd, pipeControlCmd, sizeof(PIPE_CONTROL)));
size_t cmdOffset = sizeof(PIPE_CONTROL);
auto miLrCmd = reinterpret_cast<MI_LOAD_REGISTER_IMM *>(ptrOffset(stream->getCpuBase(), cmdOffset));
EXPECT_EQ(0, memcmp(&expectedMiLrCmd, miLrCmd, sizeof(MI_LOAD_REGISTER_IMM)));
cmdOffset += sizeof(MI_LOAD_REGISTER_IMM);
expectedPipeControlCmd = FamilyType::cmdInitPipeControl;
expectedPipeControlCmd.setCommandStreamerStallEnable(0x1);
pipeControlCmd = reinterpret_cast<PIPE_CONTROL *>(ptrOffset(stream->getCpuBase(), cmdOffset));
EXPECT_EQ(0, memcmp(&expectedPipeControlCmd, pipeControlCmd, sizeof(PIPE_CONTROL)));
}
ICLLPTEST_F(Gen11MediaSamplerProgramingTest, givenVmeEnableSubsliceEnabledWhenPowerClockStateRegisterDisableThenExpectCorrectCmdValues) {
constexpr uint32_t programVmeCmdSize = sizeof(MI_LOAD_REGISTER_IMM) + 3 * sizeof(PIPE_CONTROL);
overrideMediaRequest(true, false);
size_t estimatedCmdSize = getCmdSize();
EXPECT_EQ(programVmeCmdSize, estimatedCmdSize);
programMediaSampler();
auto expectedMiLrCmd = FamilyType::cmdInitLoadRegisterImm;
expectedMiLrCmd.setRegisterOffset(gen11PowerClockStateRegister::address);
auto expectedRegValue = (device->getHardwareInfo().pSysInfo->SubSliceCount / 2) << gen11PowerClockStateRegister::subSliceCountShift;
expectedRegValue |= ((device->getHardwareInfo().pSysInfo->SliceCount * 2) << gen11PowerClockStateRegister::sliceCountShift);
expectedRegValue |= (device->getHardwareInfo().pSysInfo->MaxEuPerSubSlice << gen11PowerClockStateRegister::minEuCountShift);
expectedRegValue |= (device->getHardwareInfo().pSysInfo->MaxEuPerSubSlice << gen11PowerClockStateRegister::maxEuCountShift);
expectedRegValue |= gen11PowerClockStateRegister::disabledValue;
expectedMiLrCmd.setDataDword(expectedRegValue);
ASSERT_EQ(programVmeCmdSize, stream->getUsed());
auto expectedPipeControlCmd = FamilyType::cmdInitPipeControl;
expectedPipeControlCmd.setCommandStreamerStallEnable(0x1);
setFlushAllCaches(expectedPipeControlCmd);
expectedPipeControlCmd.setGenericMediaStateClear(true);
auto pipeControlCmd = reinterpret_cast<PIPE_CONTROL *>(stream->getCpuBase());
EXPECT_EQ(0, memcmp(&expectedPipeControlCmd, pipeControlCmd, sizeof(PIPE_CONTROL)));
size_t cmdOffset = sizeof(PIPE_CONTROL);
pipeControlCmd = reinterpret_cast<PIPE_CONTROL *>(ptrOffset(stream->getCpuBase(), cmdOffset));
expectedPipeControlCmd = FamilyType::cmdInitPipeControl;
expectedPipeControlCmd.setCommandStreamerStallEnable(0x1);
EXPECT_EQ(0, memcmp(&expectedPipeControlCmd, pipeControlCmd, sizeof(PIPE_CONTROL)));
cmdOffset += sizeof(PIPE_CONTROL);
auto miLrCmd = reinterpret_cast<MI_LOAD_REGISTER_IMM *>(ptrOffset(stream->getCpuBase(), cmdOffset));
EXPECT_EQ(0, memcmp(&expectedMiLrCmd, miLrCmd, sizeof(MI_LOAD_REGISTER_IMM)));
cmdOffset += sizeof(MI_LOAD_REGISTER_IMM);
pipeControlCmd = reinterpret_cast<PIPE_CONTROL *>(ptrOffset(stream->getCpuBase(), cmdOffset));
EXPECT_EQ(0, memcmp(&expectedPipeControlCmd, pipeControlCmd, sizeof(PIPE_CONTROL)));
}
ICLLPTEST_F(Gen11MediaSamplerProgramingTest, givenVmeEnableSubsliceEnabledWhenPowerClockStateRegisterEnabledThenExpectNoCmds) {
constexpr uint32_t programVmeCmdSize = 0;
overrideMediaRequest(true, true);
size_t estimatedCmdSize = getCmdSize();
EXPECT_EQ(programVmeCmdSize, estimatedCmdSize);
programMediaSampler();
EXPECT_EQ(programVmeCmdSize, stream->getUsed());
}
ICLLPTEST_F(Gen11MediaSamplerProgramingTest, givenVmeEnableSubsliceDisabledWhenPowerClockStateRegisterDisableThenExpectNoCmds) {
constexpr uint32_t programVmeCmdSize = 0;
overrideMediaRequest(false, false);
size_t estimatedCmdSize = getCmdSize();
EXPECT_EQ(programVmeCmdSize, estimatedCmdSize);
programMediaSampler();
EXPECT_EQ(programVmeCmdSize, stream->getUsed());
}

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/sampler/sampler.h"
#include "test.h"
#include "unit_tests/fixtures/device_fixture.h"
#include "unit_tests/mocks/mock_context.h"
#include <memory>
using namespace NEO;
typedef Test<DeviceFixture> Gen11SamplerTest;
GEN11TEST_F(Gen11SamplerTest, appendSamplerStateParamsDoesNothing) {
typedef typename FamilyType::SAMPLER_STATE SAMPLER_STATE;
std::unique_ptr<MockContext> context(new MockContext());
std::unique_ptr<SamplerHw<FamilyType>> sampler(new SamplerHw<FamilyType>(context.get(), CL_FALSE, CL_ADDRESS_NONE, CL_FILTER_NEAREST));
auto stateWithoutAppendedParams = FamilyType::cmdInitSamplerState;
auto stateWithAppendedParams = FamilyType::cmdInitSamplerState;
EXPECT_TRUE(memcmp(&stateWithoutAppendedParams, &stateWithAppendedParams, sizeof(SAMPLER_STATE)) == 0);
sampler->appendSamplerStateParams(&stateWithAppendedParams);
EXPECT_TRUE(memcmp(&stateWithoutAppendedParams, &stateWithAppendedParams, sizeof(SAMPLER_STATE)) == 0);
}

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/device_queue/device_queue_hw.h"
#include "hw_cmds.h"
// Keep the order of device_enqueue.h and scheduler_definitions.h as the latter uses defines from the first one
#include "runtime/gen11/device_enqueue.h"
#include "runtime/gen11/scheduler_definitions.h"
#include "unit_tests/scheduler/scheduler_source_tests.h"
// Keep this include below scheduler_definitions.h and device_enqueue.h headers as it depends on defines defined in them
#include "unit_tests/scheduler/scheduler_source_tests.inl"
using namespace NEO;
static_assert((SECOND_LEVEL_BUFFER_SPACE_FOR_EACH_ENQUEUE_GEN11 & (MemoryConstants::cacheLineSize - 1)) == 0, "Second level buffer space incorrect for gen11");
typedef SchedulerSourceTest SchedulerSourceTestGen11;
GEN11TEST_F(SchedulerSourceTestGen11, GivenDeviceQueueWhenCommandsSizeIsCalculatedThenItEqualsSpaceForEachEnqueueInSchedulerKernelCode) {
givenDeviceQueueWhenCommandsSizeIsCalculatedThenItEqualsSpaceForEachEnqueueInSchedulerKernelCodeTest<FamilyType>();
}
GEN11TEST_F(SchedulerSourceTestGen11, GivenDeviceQueueWhenSlbDummyCommandsAreBuildThenSizeUsedIsCorrect) {
givenDeviceQueueWhenSlbDummyCommandsAreBuildThenSizeUsedIsCorrectTest<FamilyType>();
}
GEN11TEST_F(SchedulerSourceTestGen11, GivenDeviceQueueThenNumberOfEnqueuesEqualsNumberOfEnqueuesInSchedulerKernelCode) {
givenDeviceQueueThenNumberOfEnqueuesEqualsNumberOfEnqueuesInSchedulerKernelCodeTest<FamilyType>();
}

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/command_stream/tbx_command_stream_receiver_hw.h"
#include "test.h"
#include "unit_tests/fixtures/device_fixture.h"
using namespace NEO;
using Gen11TbxCommandStreamReceiverTests = Test<DeviceFixture>;
GEN11TEST_F(Gen11TbxCommandStreamReceiverTests, whenAskedForPollForCompletionParametersThenReturnCorrectValues) {
class MyMockTbxHw : public TbxCommandStreamReceiverHw<FamilyType> {
public:
MyMockTbxHw(ExecutionEnvironment &executionEnvironment)
: TbxCommandStreamReceiverHw<FamilyType>(executionEnvironment) {}
using TbxCommandStreamReceiverHw<FamilyType>::getpollNotEqualValueForPollForCompletion;
using TbxCommandStreamReceiverHw<FamilyType>::getMaskAndValueForPollForCompletion;
};
MyMockTbxHw myMockTbxHw(*pDevice->executionEnvironment);
EXPECT_EQ(0x80u, myMockTbxHw.getMaskAndValueForPollForCompletion());
EXPECT_TRUE(myMockTbxHw.getpollNotEqualValueForPollForCompletion());
}

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/helpers/hw_helper.h"
#include "test.h"
#include "unit_tests/fixtures/device_fixture.h"
using namespace NEO;
typedef Test<DeviceFixture> Gen11DeviceCaps;
LKFTEST_F(Gen11DeviceCaps, givenLKFWhenCheckedOCLVersionThen21IsReported) {
const auto &caps = pDevice->getDeviceInfo();
EXPECT_STREQ("OpenCL 1.2 NEO ", caps.clVersion);
EXPECT_STREQ("OpenCL C 1.2 ", caps.clCVersion);
}
LKFTEST_F(Gen11DeviceCaps, givenLKFWhenCheckedSvmSupportThenNoSvmIsReported) {
const auto &caps = pDevice->getDeviceInfo();
EXPECT_EQ(caps.svmCapabilities, 0u);
}
LKFTEST_F(Gen11DeviceCaps, givenLkfWhenDoublePrecissionIsCheckedThenFalseIsReturned) {
EXPECT_FALSE(pDevice->getHardwareInfo().capabilityTable.ftrSupportsFP64);
EXPECT_FALSE(pDevice->getHardwareInfo().capabilityTable.ftrSupports64BitMath);
}
LKFTEST_F(Gen11DeviceCaps, givenLkfWhenExtensionStringIsCheckedThenFP64IsNotReported) {
const auto &caps = pDevice->getDeviceInfo();
std::string extensionString = caps.deviceExtensions;
EXPECT_EQ(std::string::npos, extensionString.find(std::string("cl_khr_fp64")));
EXPECT_EQ(0u, caps.doubleFpConfig);
}
LKFTEST_F(Gen11DeviceCaps, givenLkfWhenSlmSizeIsRequiredThenReturnCorrectValue) {
EXPECT_EQ(64u, pDevice->getHardwareInfo().capabilityTable.slmSize);
}
ICLLPTEST_F(Gen11DeviceCaps, lpSkusDontSupportFP64) {
const auto &caps = pDevice->getDeviceInfo();
std::string extensionString = caps.deviceExtensions;
EXPECT_EQ(std::string::npos, extensionString.find(std::string("cl_khr_fp64")));
EXPECT_EQ(0u, caps.doubleFpConfig);
}
ICLLPTEST_F(Gen11DeviceCaps, lpSkusDontSupportCorrectlyRoundedDivideSqrt) {
const auto &caps = pDevice->getDeviceInfo();
EXPECT_EQ(0u, caps.singleFpConfig & CL_FP_CORRECTLY_ROUNDED_DIVIDE_SQRT);
}
ICLLPTEST_F(Gen11DeviceCaps, givenIclLpWhenSlmSizeIsRequiredThenReturnCorrectValue) {
EXPECT_EQ(64u, pDevice->getHardwareInfo().capabilityTable.slmSize);
}
GEN11TEST_F(Gen11DeviceCaps, defaultPreemptionMode) {
EXPECT_TRUE(PreemptionMode::MidThread == pDevice->getHardwareInfo().capabilityTable.defaultPreemptionMode);
}
GEN11TEST_F(Gen11DeviceCaps, whitelistedRegisters) {
EXPECT_TRUE(pDevice->getHardwareInfo().capabilityTable.whitelistedRegisters.csChicken1_0x2580);
EXPECT_FALSE(pDevice->getHardwareInfo().capabilityTable.whitelistedRegisters.chicken0hdc_0xE5F0);
}
GEN11TEST_F(Gen11DeviceCaps, profilingTimerResolution) {
const auto &caps = pDevice->getDeviceInfo();
EXPECT_EQ(83u, caps.outProfilingTimerResolution);
}
GEN11TEST_F(Gen11DeviceCaps, kmdNotifyMechanism) {
EXPECT_FALSE(pDevice->getHardwareInfo().capabilityTable.kmdNotifyProperties.enableKmdNotify);
EXPECT_EQ(0, pDevice->getHardwareInfo().capabilityTable.kmdNotifyProperties.delayKmdNotifyMicroseconds);
EXPECT_FALSE(pDevice->getHardwareInfo().capabilityTable.kmdNotifyProperties.enableQuickKmdSleep);
EXPECT_EQ(0, pDevice->getHardwareInfo().capabilityTable.kmdNotifyProperties.delayQuickKmdSleepMicroseconds);
EXPECT_FALSE(pDevice->getHardwareInfo().capabilityTable.kmdNotifyProperties.enableQuickKmdSleepForSporadicWaits);
EXPECT_EQ(0, pDevice->getHardwareInfo().capabilityTable.kmdNotifyProperties.delayQuickKmdSleepForSporadicWaitsMicroseconds);
}
GEN11TEST_F(Gen11DeviceCaps, compression) {
EXPECT_FALSE(pDevice->getHardwareInfo().capabilityTable.ftrRenderCompressedBuffers);
EXPECT_FALSE(pDevice->getHardwareInfo().capabilityTable.ftrRenderCompressedImages);
}
GEN11TEST_F(Gen11DeviceCaps, givenHwInfoWhenRequestedComputeUnitsUsedForScratchThenReturnValidValue) {
const auto &hwInfo = pDevice->getHardwareInfo();
auto &hwHelper = HwHelper::get(hwInfo.pPlatform->eRenderCoreFamily);
uint32_t expectedValue = hwInfo.pSysInfo->MaxSubSlicesSupported * hwInfo.pSysInfo->MaxEuPerSubSlice * 8;
EXPECT_EQ(expectedValue, hwHelper.getComputeUnitsUsedForScratch(&hwInfo));
EXPECT_EQ(expectedValue, pDevice->getDeviceInfo().computeUnitsUsedForScratch);
}
GEN11TEST_F(Gen11DeviceCaps, givenGen11WhenCheckSupportCacheFlushAfterWalkerThenFalse) {
EXPECT_FALSE(pDevice->getHardwareInfo().capabilityTable.supportCacheFlushAfterWalker);
}
typedef Test<DeviceFixture> IclLpUsDeviceIdTest;
ICLLPTEST_F(IclLpUsDeviceIdTest, isSimulationCap) {
unsigned short iclLpSimulationIds[2] = {
IICL_LP_GT1_MOB_DEVICE_F0_ID,
0, // default, non-simulation
};
NEO::MockDevice *mockDevice = nullptr;
for (auto id : iclLpSimulationIds) {
mockDevice = createWithUsDeviceId(id);
ASSERT_NE(mockDevice, nullptr);
if (id == 0)
EXPECT_FALSE(mockDevice->isSimulation());
else
EXPECT_TRUE(mockDevice->isSimulation());
delete mockDevice;
}
}
ICLLPTEST_F(IclLpUsDeviceIdTest, GivenICLLPWhenCheckftr64KBpagesThenFalse) {
EXPECT_FALSE(pDevice->getHardwareInfo().capabilityTable.ftr64KBpages);
}
typedef Test<DeviceFixture> LkfUsDeviceIdTest;
LKFTEST_F(LkfUsDeviceIdTest, isSimulationCap) {
unsigned short lkfSimulationIds[2] = {
ILKF_1x8x8_DESK_DEVICE_F0_ID,
0, // default, non-simulation
};
NEO::MockDevice *mockDevice = nullptr;
for (auto id : lkfSimulationIds) {
mockDevice = createWithUsDeviceId(id);
ASSERT_NE(mockDevice, nullptr);
if (id == 0)
EXPECT_FALSE(mockDevice->isSimulation());
else
EXPECT_TRUE(mockDevice->isSimulation());
delete mockDevice;
}
}

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/context/context.h"
#include "unit_tests/fixtures/device_host_queue_fixture.h"
#include "unit_tests/helpers/hw_parse.h"
#include "unit_tests/mocks/mock_device_queue.h"
#include <memory>
using namespace NEO;
using namespace DeviceHostQueue;
typedef DeviceQueueHwTest Gen11DeviceQueueSlb;
GEN11TEST_F(Gen11DeviceQueueSlb, expectedAllocationSize) {
deviceQueue = createQueueObject();
ASSERT_NE(deviceQueue, nullptr);
auto expectedSize = getMinimumSlbSize<FamilyType>();
expectedSize *= 128; //num of enqueues
expectedSize += sizeof(typename FamilyType::MI_BATCH_BUFFER_START);
expectedSize = alignUp(expectedSize, MemoryConstants::pageSize);
expectedSize += MockDeviceQueueHw<FamilyType>::getExecutionModelCleanupSectionSize();
expectedSize += (4 * MemoryConstants::pageSize);
expectedSize = alignUp(expectedSize, MemoryConstants::pageSize);
ASSERT_NE(deviceQueue->getSlbBuffer(), nullptr);
EXPECT_EQ(deviceQueue->getSlbBuffer()->getUnderlyingBufferSize(), expectedSize);
delete deviceQueue;
}
GEN11TEST_F(Gen11DeviceQueueSlb, SlbCommandsWa) {
auto mockDeviceQueueHw = std::make_unique<MockDeviceQueueHw<FamilyType>>(pContext, device,
DeviceHostQueue::deviceQueueProperties::minimumProperties[0]);
EXPECT_FALSE(mockDeviceQueueHw->arbCheckWa);
EXPECT_FALSE(mockDeviceQueueHw->pipeControlWa);
EXPECT_FALSE(mockDeviceQueueHw->miAtomicWa);
EXPECT_FALSE(mockDeviceQueueHw->lriWa);
}
GEN11TEST_F(Gen11DeviceQueueSlb, GivenDeviceQueueWhenSingleEnqueueSpaceIsNotCachelineAlignedThenCSPrefetchIsExtendedWithCachelineAlignement) {
auto mockDeviceQueueHw = std::make_unique<MockDeviceQueueHw<FamilyType>>(pContext, device,
DeviceHostQueue::deviceQueueProperties::minimumProperties[0]);
EXPECT_LE(8 * MemoryConstants::cacheLineSize, mockDeviceQueueHw->getCSPrefetchSize());
EXPECT_EQ(0u, (mockDeviceQueueHw->getMinimumSlbSize() & (MemoryConstants::cacheLineSize - 1)));
}

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/helpers/options.h"
#include "test.h"
#include "unit_tests/fixtures/platform_fixture.h"
using namespace NEO;
struct Gen11PlatformCaps : public PlatformFixture, public ::testing::Test {
void SetUp() override {
PlatformFixture::SetUp();
}
void TearDown() override {
PlatformFixture::TearDown();
}
};
ICLLPTEST_F(Gen11PlatformCaps, lpSkusDontSupportFP64) {
const auto &caps = pPlatform->getPlatformInfo();
EXPECT_EQ(std::string::npos, caps.extensions.find(std::string("cl_khr_fp64")));
}

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/command_stream/preemption.h"
#include "unit_tests/helpers/debug_manager_state_restore.h"
#include "unit_tests/preamble/preamble_fixture.h"
#include "reg_configs_common.h"
using namespace NEO;
typedef PreambleFixture IclSlm;
GEN11TEST_F(IclSlm, shouldBeEnabledOnGen11) {
typedef ICLFamily::MI_LOAD_REGISTER_IMM MI_LOAD_REGISTER_IMM;
LinearStream &cs = linearStream;
uint32_t l3Config = PreambleHelper<FamilyType>::getL3Config(**platformDevices, true);
PreambleHelper<FamilyType>::programL3(&cs, l3Config);
parseCommands<ICLFamily>(cs);
auto itorLRI = find<MI_LOAD_REGISTER_IMM *>(cmdList.begin(), cmdList.end());
ASSERT_NE(cmdList.end(), itorLRI);
const auto &lri = *reinterpret_cast<MI_LOAD_REGISTER_IMM *>(*itorLRI);
auto RegisterOffset = L3CNTLRegisterOffset<FamilyType>::registerOffset;
EXPECT_EQ(RegisterOffset, lri.getRegisterOffset());
EXPECT_EQ(0u, lri.getDataDword() & 1);
}
GEN11TEST_F(IclSlm, givenGen11WhenProgramingL3ThenErrorDetectionBehaviorControlBitSet) {
uint32_t l3Config = PreambleHelper<FamilyType>::getL3Config(**platformDevices, true);
uint32_t errorDetectionBehaviorControlBit = 1 << 9;
EXPECT_TRUE((l3Config & errorDetectionBehaviorControlBit) != 0);
}
typedef PreambleFixture Gen11UrbEntryAllocationSize;
GEN11TEST_F(Gen11UrbEntryAllocationSize, getUrbEntryAllocationSize) {
uint32_t actualVal = PreambleHelper<FamilyType>::getUrbEntryAllocationSize();
EXPECT_EQ(0x782u, actualVal);
}
typedef PreambleVfeState Gen11PreambleVfeState;
GEN11TEST_F(Gen11PreambleVfeState, WaOff) {
typedef typename ICLFamily::PIPE_CONTROL PIPE_CONTROL;
testWaTable.waSendMIFLUSHBeforeVFE = 0;
LinearStream &cs = linearStream;
PreambleHelper<ICLFamily>::programVFEState(&linearStream, **platformDevices, 0, 0);
parseCommands<ICLFamily>(cs);
auto itorPC = find<PIPE_CONTROL *>(cmdList.begin(), cmdList.end());
ASSERT_NE(cmdList.end(), itorPC);
const auto &pc = *reinterpret_cast<PIPE_CONTROL *>(*itorPC);
EXPECT_FALSE(pc.getRenderTargetCacheFlushEnable());
EXPECT_FALSE(pc.getDepthCacheFlushEnable());
EXPECT_FALSE(pc.getDcFlushEnable());
EXPECT_EQ(1u, pc.getCommandStreamerStallEnable());
}
GEN11TEST_F(Gen11PreambleVfeState, WaOn) {
typedef typename ICLFamily::PIPE_CONTROL PIPE_CONTROL;
testWaTable.waSendMIFLUSHBeforeVFE = 1;
LinearStream &cs = linearStream;
PreambleHelper<ICLFamily>::programVFEState(&linearStream, **platformDevices, 0, 0);
parseCommands<ICLFamily>(cs);
auto itorPC = find<PIPE_CONTROL *>(cmdList.begin(), cmdList.end());
ASSERT_NE(cmdList.end(), itorPC);
const auto &pc = *reinterpret_cast<PIPE_CONTROL *>(*itorPC);
EXPECT_TRUE(pc.getRenderTargetCacheFlushEnable());
EXPECT_TRUE(pc.getDepthCacheFlushEnable());
EXPECT_TRUE(pc.getDcFlushEnable());
EXPECT_EQ(1u, pc.getCommandStreamerStallEnable());
}
typedef PreambleFixture PreemptionWatermarkGen11;
GEN11TEST_F(PreemptionWatermarkGen11, givenPreambleThenPreambleWorkAroundsIsNotProgrammed) {
PreambleHelper<FamilyType>::programGenSpecificPreambleWorkArounds(&linearStream, **platformDevices);
parseCommands<FamilyType>(linearStream);
auto cmd = findMmioCmd<FamilyType>(cmdList.begin(), cmdList.end(), FfSliceCsChknReg2::address);
ASSERT_EQ(nullptr, cmd);
size_t expectedSize = PreemptionHelper::getRequiredPreambleSize<FamilyType>(MockDevice(*platformDevices[0]));
EXPECT_EQ(expectedSize, PreambleHelper<FamilyType>::getAdditionalCommandsSize(MockDevice(*platformDevices[0])));
}
typedef PreambleFixture ThreadArbitrationGen11;
GEN11TEST_F(ThreadArbitrationGen11, givenPreambleWhenItIsProgrammedThenThreadArbitrationIsSet) {
DebugManagerStateRestore dbgRestore;
DebugManager.flags.ForcePreemptionMode.set(static_cast<int32_t>(PreemptionMode::Disabled));
typedef ICLFamily::MI_LOAD_REGISTER_IMM MI_LOAD_REGISTER_IMM;
typedef ICLFamily::PIPE_CONTROL PIPE_CONTROL;
LinearStream &cs = linearStream;
uint32_t l3Config = PreambleHelper<FamilyType>::getL3Config(**platformDevices, true);
MockDevice mockDevice(**platformDevices);
PreambleHelper<FamilyType>::programPreamble(&linearStream, mockDevice, l3Config,
ThreadArbitrationPolicy::RoundRobin,
nullptr);
parseCommands<FamilyType>(cs);
auto ppC = find<PIPE_CONTROL *>(cmdList.begin(), cmdList.end());
ASSERT_NE(ppC, cmdList.end());
auto cmd = findMmioCmd<FamilyType>(cmdList.begin(), cmdList.end(), RowChickenReg4::address);
ASSERT_NE(nullptr, cmd);
EXPECT_EQ(RowChickenReg4::regDataForArbitrationPolicy[ThreadArbitrationPolicy::RoundRobin], cmd->getDataDword());
EXPECT_EQ(0u, PreambleHelper<ICLFamily>::getAdditionalCommandsSize(MockDevice(*platformDevices[0])));
EXPECT_EQ(sizeof(MI_LOAD_REGISTER_IMM) + sizeof(PIPE_CONTROL), PreambleHelper<ICLFamily>::getThreadArbitrationCommandsSize());
}
GEN11TEST_F(ThreadArbitrationGen11, defaultArbitrationPolicy) {
EXPECT_EQ(ThreadArbitrationPolicy::RoundRobinAfterDependency, PreambleHelper<ICLFamily>::getDefaultThreadArbitrationPolicy());
}

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/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/built_ins/built_ins.h"
#include "runtime/helpers/hw_helper.h"
#include "unit_tests/fixtures/preemption_fixture.h"
#include "unit_tests/helpers/hw_parse.h"
#include "unit_tests/mocks/mock_buffer.h"
#include "unit_tests/mocks/mock_command_queue.h"
#include "unit_tests/mocks/mock_csr.h"
using namespace NEO;
using Gen11PreemptionTests = DevicePreemptionTests;
template <>
PreemptionTestHwDetails GetPreemptionTestHwDetails<ICLFamily>() {
PreemptionTestHwDetails ret;
ret.modeToRegValueMap[PreemptionMode::ThreadGroup] = DwordBuilder::build(1, true) | DwordBuilder::build(2, true, false);
ret.modeToRegValueMap[PreemptionMode::MidBatch] = DwordBuilder::build(2, true) | DwordBuilder::build(1, true, false);
ret.modeToRegValueMap[PreemptionMode::MidThread] = DwordBuilder::build(2, true, false) | DwordBuilder::build(1, true, false);
ret.defaultRegValue = ret.modeToRegValueMap[PreemptionMode::MidBatch];
ret.regAddress = 0x2580u;
return ret;
}
GEN11TEST_F(Gen11PreemptionTests, whenMidThreadPreemptionIsNotAvailableThenDoesNotProgramStateSip) {
device->setPreemptionMode(PreemptionMode::ThreadGroup);
size_t requiredSize = PreemptionHelper::getRequiredPreambleSize<FamilyType>(*device);
EXPECT_EQ(0U, requiredSize);
LinearStream cmdStream{nullptr, 0};
PreemptionHelper::getRequiredStateSipCmdSize<FamilyType>(*device);
EXPECT_EQ(0U, cmdStream.getUsed());
}
GEN11TEST_F(Gen11PreemptionTests, whenMidThreadPreemptionIsAvailableThenStateSipIsProgrammed) {
using STATE_SIP = typename FamilyType::STATE_SIP;
device->setPreemptionMode(PreemptionMode::MidThread);
executionEnvironment->DisableMidThreadPreemption = 0;
size_t requiredCmdStreamSize = PreemptionHelper::getRequiredStateSipCmdSize<FamilyType>(*device);
size_t expectedPreambleSize = sizeof(STATE_SIP);
EXPECT_EQ(expectedPreambleSize, requiredCmdStreamSize);
StackVec<char, 8192> streamStorage(requiredCmdStreamSize);
ASSERT_LE(requiredCmdStreamSize, streamStorage.size());
LinearStream cmdStream{streamStorage.begin(), streamStorage.size()};
PreemptionHelper::programStateSip<FamilyType>(cmdStream, *device);
HardwareParse hwParsePreamble;
hwParsePreamble.parseCommands<FamilyType>(cmdStream);
auto stateSipCmd = hwParsePreamble.getCommand<STATE_SIP>();
ASSERT_NE(nullptr, stateSipCmd);
EXPECT_EQ(device->getExecutionEnvironment()->getBuiltIns()->getSipKernel(SipKernelType::Csr, *device).getSipAllocation()->getGpuAddressToPatch(), stateSipCmd->getSystemInstructionPointer());
}
GEN11TEST_F(Gen11PreemptionTests, getRequiredCmdQSize) {
size_t expectedSize = 0;
EXPECT_EQ(expectedSize, PreemptionHelper::getPreemptionWaCsSize<FamilyType>(*device));
}
GEN11TEST_F(Gen11PreemptionTests, applyPreemptionWaCmds) {
size_t usedSize = 0;
auto &cmdStream = cmdQ->getCS(0);
PreemptionHelper::applyPreemptionWaCmdsBegin<FamilyType>(&cmdStream, *device);
EXPECT_EQ(usedSize, cmdStream.getUsed());
PreemptionHelper::applyPreemptionWaCmdsEnd<FamilyType>(&cmdStream, *device);
EXPECT_EQ(usedSize, cmdStream.getUsed());
}
GEN11TEST_F(Gen11PreemptionTests, givenInterfaceDescriptorDataWhenMidThreadPreemptionModeThenSetDisableThreadPreemptionBitToDisable) {
using INTERFACE_DESCRIPTOR_DATA = typename FamilyType::INTERFACE_DESCRIPTOR_DATA;
INTERFACE_DESCRIPTOR_DATA iddArg;
iddArg = FamilyType::cmdInitInterfaceDescriptorData;
iddArg.setThreadPreemptionDisable(INTERFACE_DESCRIPTOR_DATA::THREAD_PREEMPTION_DISABLE_ENABLE);
PreemptionHelper::programInterfaceDescriptorDataPreemption<FamilyType>(&iddArg, PreemptionMode::MidThread);
EXPECT_EQ(INTERFACE_DESCRIPTOR_DATA::THREAD_PREEMPTION_DISABLE_DISABLE, iddArg.getThreadPreemptionDisable());
}
GEN11TEST_F(Gen11PreemptionTests, givenInterfaceDescriptorDataWhenNoMidThreadPreemptionModeThenSetDisableThreadPreemptionBitToEnable) {
using INTERFACE_DESCRIPTOR_DATA = typename FamilyType::INTERFACE_DESCRIPTOR_DATA;
INTERFACE_DESCRIPTOR_DATA iddArg;
iddArg = FamilyType::cmdInitInterfaceDescriptorData;
iddArg.setThreadPreemptionDisable(INTERFACE_DESCRIPTOR_DATA::THREAD_PREEMPTION_DISABLE_DISABLE);
PreemptionHelper::programInterfaceDescriptorDataPreemption<FamilyType>(&iddArg, PreemptionMode::Disabled);
EXPECT_EQ(INTERFACE_DESCRIPTOR_DATA::THREAD_PREEMPTION_DISABLE_ENABLE, iddArg.getThreadPreemptionDisable());
iddArg.setThreadPreemptionDisable(INTERFACE_DESCRIPTOR_DATA::THREAD_PREEMPTION_DISABLE_DISABLE);
PreemptionHelper::programInterfaceDescriptorDataPreemption<FamilyType>(&iddArg, PreemptionMode::MidBatch);
EXPECT_EQ(INTERFACE_DESCRIPTOR_DATA::THREAD_PREEMPTION_DISABLE_ENABLE, iddArg.getThreadPreemptionDisable());
iddArg.setThreadPreemptionDisable(INTERFACE_DESCRIPTOR_DATA::THREAD_PREEMPTION_DISABLE_DISABLE);
PreemptionHelper::programInterfaceDescriptorDataPreemption<FamilyType>(&iddArg, PreemptionMode::ThreadGroup);
EXPECT_EQ(INTERFACE_DESCRIPTOR_DATA::THREAD_PREEMPTION_DISABLE_ENABLE, iddArg.getThreadPreemptionDisable());
}

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