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Revert "fix: align indirect data pointer to cacheline size in heapless mode"
This reverts commit 004e6e647f.
Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
This commit is contained in:
committed by
Compute-Runtime-Automation
parent
d22b2a8a38
commit
57c946b61c
@@ -53,8 +53,11 @@ struct uint16x16_t { // NOLINT(readability-identifier-naming)
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}
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inline void load(const void *alignedPtr) {
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DEBUG_BREAK_IF(!isAligned<32>(alignedPtr));
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value = _mm256_load_si256(reinterpret_cast<const __m256i *>(alignedPtr)); // AVX
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if (isAligned<32>(alignedPtr)) {
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value = _mm256_load_si256(reinterpret_cast<const __m256i *>(alignedPtr)); // AVX
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} else {
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loadUnaligned(alignedPtr);
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}
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}
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inline void loadUnaligned(const void *ptr) {
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@@ -62,8 +65,11 @@ struct uint16x16_t { // NOLINT(readability-identifier-naming)
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}
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inline void store(void *alignedPtr) {
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DEBUG_BREAK_IF(!isAligned<32>(alignedPtr));
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_mm256_store_si256(reinterpret_cast<__m256i *>(alignedPtr), value); // AVX
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if (isAligned<32>(alignedPtr)) {
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_mm256_store_si256(reinterpret_cast<__m256i *>(alignedPtr), value); // AVX
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} else {
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storeUnaligned(alignedPtr);
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}
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}
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inline void storeUnaligned(void *ptr) {
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