Revert "fix: align indirect data pointer to cacheline size in heapless mode"

This reverts commit 004e6e647f.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
This commit is contained in:
Compute-Runtime-Validation
2024-02-15 05:18:47 +01:00
committed by Compute-Runtime-Automation
parent d22b2a8a38
commit 57c946b61c
2 changed files with 11 additions and 7 deletions

View File

@@ -53,8 +53,11 @@ struct uint16x16_t { // NOLINT(readability-identifier-naming)
}
inline void load(const void *alignedPtr) {
DEBUG_BREAK_IF(!isAligned<32>(alignedPtr));
value = _mm256_load_si256(reinterpret_cast<const __m256i *>(alignedPtr)); // AVX
if (isAligned<32>(alignedPtr)) {
value = _mm256_load_si256(reinterpret_cast<const __m256i *>(alignedPtr)); // AVX
} else {
loadUnaligned(alignedPtr);
}
}
inline void loadUnaligned(const void *ptr) {
@@ -62,8 +65,11 @@ struct uint16x16_t { // NOLINT(readability-identifier-naming)
}
inline void store(void *alignedPtr) {
DEBUG_BREAK_IF(!isAligned<32>(alignedPtr));
_mm256_store_si256(reinterpret_cast<__m256i *>(alignedPtr), value); // AVX
if (isAligned<32>(alignedPtr)) {
_mm256_store_si256(reinterpret_cast<__m256i *>(alignedPtr), value); // AVX
} else {
storeUnaligned(alignedPtr);
}
}
inline void storeUnaligned(void *ptr) {