Switch clang-format to 6.0

Change-Id: Id96d1f47fb3d479d10d1022f1259dc030a148192
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
This commit is contained in:
Artur Harasimiuk
2018-06-12 21:54:39 +02:00
parent 5b479ec5f2
commit 75ab0c6fe1
255 changed files with 564 additions and 568 deletions

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -251,4 +251,4 @@ const char *CElfReader::getSectionName(
return pName;
}
} // namespace OclElfLib
} // namespace CLElfLib

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -198,4 +198,4 @@ struct SElf64SectionHeader {
Elf64_Xword EntrySize;
};
} // namespace ELFlib
} // namespace CLElfLib

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -201,7 +201,7 @@ bool CElfWriter::resolveBinary(
memcpy_s(pCurString, pNode->Name.size(), pNode->Name.c_str(), pNode->Name.size());
pCurString += pNode->Name.size();
}
*(pCurString++) = '\0';
*(pCurString++) = '\0'; // NOLINT
// delete the node and it's data
if (pNode->pData) {
@@ -282,4 +282,4 @@ bool CElfWriter::patchElfHeader(char *const pBinary) {
return false;
}
} // namespace OclElfLib
} // namespace CLElfLib

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -102,4 +102,4 @@ class CElfWriter {
size_t m_stringTableSize = 0U;
size_t m_totalBinarySize = 0U;
};
} // namespace ELFLib
} // namespace CLElfLib

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@@ -17,7 +17,7 @@ components:
branch: infra
clean_on_sync: true
dest_dir: infra
revision: 3579cc63a0d9ec2666c7ed58d2b624ff0f4692f3
revision: 8abea2b4f36cb427643575a3127ea3c9c8c157d5
type: git
internal:
branch: master

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -78,4 +78,4 @@ cl_int IntelAccelerator::getInfo(cl_accelerator_info_intel paramName,
return result;
}
}
} // namespace OCLRT

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -76,4 +76,4 @@ cl_int VmeAccelerator::validateVmeArgs(Context *context,
return CL_SUCCESS;
}
}
} // namespace OCLRT

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -69,4 +69,4 @@ class VmeAccelerator : public IntelAccelerator {
size_t descriptorSize,
const void *descriptor);
};
}
} // namespace OCLRT

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@@ -186,4 +186,4 @@ void LrcaHelper::initialize(void *pLRCIn) const {
setPDP2(pLRCIn, 0);
setPDP3(pLRCIn, 0);
}
}
} // namespace AubMemDump

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@@ -490,4 +490,4 @@ class BuiltInOp<HWFamily, EBuiltInOps::VmeBlockAdvancedMotionEstimateBidirection
return true;
}
};
}
} // namespace OCLRT

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@@ -45,7 +45,7 @@ float __intel__getProfilingTimerResolution() {
#include "runtime/gen8/scheduler_definitions.h"
#include "runtime/gen8/scheduler_igdrcl_built_in.inl"
#include "runtime/scheduler/scheduler.cl"
}
} // namespace Gen8SchedulerSimulation
namespace BuiltinKernelsSimulation {

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@@ -47,7 +47,7 @@ float __intel__getProfilingTimerResolution() {
#include "runtime/gen9/scheduler_definitions.h"
#include "runtime/gen9/scheduler_igdrcl_built_in.inl"
#include "runtime/scheduler/scheduler.cl"
}
} // namespace Gen9SchedulerSimulation
namespace BuiltinKernelsSimulation {

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@@ -138,7 +138,7 @@ uint4 write_imageui(image *im, uint4 coord, uint4 color) {
temp += im->bytesPerChannel;
colorSrc += 4;
}
return *(uint4 *)temp;
return *(uint4 *)temp; // NOLINT
}
uchar convert_uchar_sat(uint c) {

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -301,4 +301,4 @@ TYPE atomic_min(TYPE *first, TYPE2 second) {
gMutex.unlock();
return temp;
}
}
} // namespace BuiltinKernelsSimulation

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -52,4 +52,4 @@ cl_int CommandQueueHw<GfxFamily>::enqueueBarrierWithWaitList(
return CL_SUCCESS;
}
}
} // namespace OCLRT

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -74,4 +74,4 @@ cl_int CommandQueueHw<GfxFamily>::enqueueCopyBuffer(
return CL_SUCCESS;
}
}
} // namespace OCLRT

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@@ -93,4 +93,4 @@ cl_int CommandQueueHw<GfxFamily>::enqueueFillBuffer(
return CL_SUCCESS;
}
}
} // namespace OCLRT

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@@ -319,4 +319,4 @@ cl_int CommandQueueHw<GfxFamily>::enqueueSVMMigrateMem(cl_uint numSvmPointers,
event);
return CL_SUCCESS;
}
}
} // namespace OCLRT

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@@ -76,4 +76,4 @@ template <typename Vec, int simd>
void generateLocalIDsSimd(void *b, size_t lwsX, size_t lwsY, size_t threadsPerWorkGroup);
void generateLocalIDs(void *buffer, uint32_t simd, size_t lwsX, size_t lwsY, size_t lwsZ);
}
} // namespace OCLRT

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -157,4 +157,4 @@ inline void generateLocalIDsSimd(void *b, size_t lwsX, size_t lwsY, size_t threa
} while (++pass < passes);
}
}
} // namespace OCLRT

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -27,5 +27,5 @@
namespace OCLRT {
template void generateLocalIDsSimd<uint16x16_t, 32>(void *b, size_t lwsX, size_t lwsY, size_t threadsPerWorkGroup);
template void generateLocalIDsSimd<uint16x16_t, 16>(void *b, size_t lwsX, size_t lwsY, size_t threadsPerWorkGroup);
}
} // namespace OCLRT
#endif

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -27,4 +27,4 @@ namespace OCLRT {
template void generateLocalIDsSimd<uint16x8_t, 32>(void *b, size_t lwsX, size_t lwsY, size_t threadsPerWorkGroup);
template void generateLocalIDsSimd<uint16x8_t, 16>(void *b, size_t lwsX, size_t lwsY, size_t threadsPerWorkGroup);
template void generateLocalIDsSimd<uint16x8_t, 8>(void *b, size_t lwsX, size_t lwsY, size_t threadsPerWorkGroup);
}
} // namespace OCLRT

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -35,4 +35,4 @@ struct AUBCommandStreamReceiver {
};
typedef CommandStreamReceiver *(*AubCommandStreamReceiverCreateFunc)(const HardwareInfo &hwInfoIn, const std::string &fileName, bool standalone);
}
} // namespace OCLRT

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@@ -27,4 +27,4 @@
namespace OCLRT {
extern CommandStreamReceiver *createCommandStreamImpl(const HardwareInfo *pHwInfo);
extern bool getDevicesImpl(HardwareInfo **hwInfo, size_t &numDevicesReturned);
}
} // namespace OCLRT

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -38,4 +38,4 @@ class DeviceCommandStreamReceiver : public CommandStreamReceiverHw<GfxFamily> {
public:
static CommandStreamReceiver *create(const HardwareInfo &hwInfo, bool withAubDump);
};
}
} // namespace OCLRT

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -43,4 +43,4 @@ LinearStream::LinearStream(GraphicsAllocation *gfxAllocation)
LinearStream::LinearStream()
: LinearStream(nullptr) {
}
}
} // namespace OCLRT

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@@ -40,4 +40,4 @@ CommandStreamReceiver *TbxCommandStreamReceiver::create(const HardwareInfo &hwIn
return pCreate ? pCreate(hwInfo, withAubDump) : nullptr;
}
}
} // namespace OCLRT

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -110,4 +110,4 @@ bool BinaryCache::loadCachedBinary(const std::string kernelFileHash, Program &pr
return true;
}
} // namesapce OCLRT
} // namespace OCLRT

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@@ -46,4 +46,4 @@ class BinaryCache {
static std::mutex cacheAccessMtx;
};
} // namesapce OCLRT
} // namespace OCLRT

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -54,7 +54,7 @@ CIF::CIFMain *createMainNoSanitize(CIF::CreateCIFMainFunc_t createFunc);
template <template <CIF::Version_t> class EntryPointT>
inline bool loadCompiler(const char *libName, std::unique_ptr<OsLibrary> &outLib,
CIF::RAII::UPtr_t<CIF::CIFMain> &outLibMain) {
CIF::RAII::UPtr_t<CIF::CIFMain> &outLibMain) {
auto lib = std::unique_ptr<OsLibrary>(OsLibrary::load(libName));
if (lib == nullptr) {
DEBUG_BREAK_IF(true); // could not load library
@@ -81,5 +81,4 @@ inline bool loadCompiler(const char *libName, std::unique_ptr<OsLibrary> &outLib
return true;
}
}
} // namespace OCLRT

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -31,4 +31,4 @@ CIF::CIFMain *
createMainNoSanitize(CIF::CreateCIFMainFunc_t createFunc) {
return createFunc();
}
}
} // namespace OCLRT

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@@ -37,4 +37,4 @@ Sharing *Context::getSharing() {
return reinterpret_cast<Sharing *>(sharingFunctions[Sharing::sharingId].get());
}
}
} // namespace OCLRT

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@@ -149,4 +149,4 @@ template<> struct Map<CL_DEVICE_VERSION > : pu
template<> struct Map<CL_DRIVER_VERSION > : public MapBase<CL_DRIVER_VERSION, const char *, &DeviceInfo::driverVersion> {};
template<> struct Map<CL_DEVICE_DRIVER_VERSION_INTEL > : public MapBase<CL_DEVICE_DRIVER_VERSION_INTEL, uint32_t, &DeviceInfo::internalDriverVersion> {};
// clang-format on
}
} // namespace DeviceInfoTable

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@@ -31,4 +31,4 @@ const char *libvaDllName = "libva.so.2";
const char *sysFsPciPath = "/sys/bus/pci/devices/";
const char *tbxLibName = "libtbxAccess.so";
}
} // namespace Os

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@@ -76,4 +76,4 @@ class EventBuilder {
StackVec<Event *, 16> parentEvents;
bool doNotRegister = false;
};
}
} // namespace OCLRT

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -34,4 +34,4 @@ struct HwTimeStamps {
uint64_t GlobalCompleteTS;
uint64_t ContextCompleteTS;
};
}
} // namespace OCLRT

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -39,4 +39,4 @@ struct AUBFamilyMapper<BDWFamily> {
typedef AubMemDump::AubDump<AubTraits> AUB;
};
}
} // namespace OCLRT

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@@ -29,4 +29,4 @@ typedef BDWFamily Family;
static auto gfxCore = IGFX_GEN8_CORE;
#include "runtime/mem_obj/buffer_factory_init.inl"
}
} // namespace OCLRT

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@@ -360,4 +360,4 @@ class BDW_2x3x8 : public BDW {
private:
static GT_SYSTEM_INFO gtSystemInfo;
};
}
} // namespace OCLRT

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@@ -57,4 +57,4 @@ size_t ImageHw<BDWFamily>::getHostPtrSlicePitchForMap(uint32_t mipLevel) {
}
#include "runtime/mem_obj/image_factory_init.inl"
}
} // namespace OCLRT

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@@ -45,4 +45,4 @@ uint32_t KernelCommandsHelper<BDWFamily>::computeSlmValues(uint32_t valueIn) {
// Explicitly instantiate KernelCommandsHelper for BDW device family
template struct KernelCommandsHelper<BDWFamily>;
}
} // namespace OCLRT

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@@ -29,4 +29,4 @@ namespace OCLRT {
template class DeviceCommandStreamReceiver<BDWFamily>;
template class DrmCommandStreamReceiver<BDWFamily>;
template class CommandStreamReceiverWithAUBDump<DrmCommandStreamReceiver<BDWFamily>>;
}
} // namespace OCLRT

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -36,4 +36,4 @@ template <>
struct L3CNTLRegisterOffset<BDWFamily> {
static const uint32_t registerOffset = 0x7034;
};
}
} // namespace OCLRT

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@@ -30,4 +30,4 @@ typedef BDWFamily Family;
static auto gfxCore = IGFX_GEN8_CORE;
#include "runtime/sampler/sampler_factory_init.inl"
}
} // namespace OCLRT

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -20,29 +20,23 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
uint GetPatchValueForSLMSize( uint slMsize )
{
uint PatchValue;
if( slMsize == 0 )
{
PatchValue = 0;
}
else
{
uint count4KB = slMsize / 4096;
if( slMsize % 4096 != 0 )
{
count4KB++;
}
PatchValue = GetNextPowerof2( count4KB );
}
uint GetPatchValueForSLMSize(uint slMsize) {
uint PatchValue;
if (slMsize == 0) {
PatchValue = 0;
} else {
uint count4KB = slMsize / 4096;
if (slMsize % 4096 != 0) {
count4KB++;
}
PatchValue = GetNextPowerof2(count4KB);
}
return PatchValue;
return PatchValue;
}
//on BDW we have only 1 pipe control
void NOOPCSStallPipeControl(__global uint* secondaryBatchBuffer, uint dwordOffset, uint pipeControlOffset)
{
void NOOPCSStallPipeControl(__global uint *secondaryBatchBuffer, uint dwordOffset, uint pipeControlOffset) {
dwordOffset += pipeControlOffset;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
@@ -58,8 +52,7 @@ void NOOPCSStallPipeControl(__global uint* secondaryBatchBuffer, uint dwordOffse
dwordOffset++;
}
void PutCSStallPipeControl( __global uint* secondaryBatchBuffer, uint dwordOffset, uint pipeControlOffset )
{
void PutCSStallPipeControl(__global uint *secondaryBatchBuffer, uint dwordOffset, uint pipeControlOffset) {
dwordOffset += pipeControlOffset;
secondaryBatchBuffer[dwordOffset] = PIPE_CONTROL_CSTALL_DWORD0;
dwordOffset++;

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@@ -41,4 +41,4 @@ void populateFactoryTable<TbxCommandStreamReceiverHw<Family>>() {
template class TbxCommandStreamReceiverHw<Family>;
template class CommandStreamReceiverWithAUBDump<TbxCommandStreamReceiverHw<Family>>;
}
} // namespace OCLRT

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@@ -29,4 +29,4 @@ namespace OCLRT {
template class DeviceCommandStreamReceiver<BDWFamily>;
template class WddmCommandStreamReceiver<BDWFamily>;
template class CommandStreamReceiverWithAUBDump<WddmCommandStreamReceiver<BDWFamily>>;
}
} // namespace OCLRT

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -39,4 +39,4 @@ struct AUBFamilyMapper<SKLFamily> {
typedef AubMemDump::AubDump<AubTraits> AUB;
};
}
} // namespace OCLRT

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@@ -29,4 +29,4 @@ typedef SKLFamily Family;
static auto gfxCore = IGFX_GEN9_CORE;
#include "runtime/mem_obj/buffer_factory_init.inl"
}
} // namespace OCLRT

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@@ -53,4 +53,4 @@ void ImageHw<GfxFamily>::setSurfaceMemoryObjectControlStateIndexToMocsTable(void
}
#include "runtime/mem_obj/image_factory_init.inl"
}
} // namespace OCLRT

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@@ -31,4 +31,4 @@ template <>
bool KernelCommandsHelper<SKLFamily>::isPipeControlWArequired() { return true; }
template struct KernelCommandsHelper<SKLFamily>;
}
} // namespace OCLRT

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@@ -29,4 +29,4 @@ namespace OCLRT {
template class DeviceCommandStreamReceiver<SKLFamily>;
template class DrmCommandStreamReceiver<SKLFamily>;
template class CommandStreamReceiverWithAUBDump<DrmCommandStreamReceiver<SKLFamily>>;
}
} // namespace OCLRT

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@@ -30,4 +30,4 @@ typedef SKLFamily Family;
static auto gfxCore = IGFX_GEN9_CORE;
#include "runtime/sampler/sampler_factory_init.inl"
}
} // namespace OCLRT

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@@ -41,4 +41,4 @@ void populateFactoryTable<TbxCommandStreamReceiverHw<Family>>() {
template class TbxCommandStreamReceiverHw<Family>;
template class CommandStreamReceiverWithAUBDump<TbxCommandStreamReceiverHw<Family>>;
}
} // namespace OCLRT

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@@ -29,4 +29,4 @@ namespace OCLRT {
template class DeviceCommandStreamReceiver<SKLFamily>;
template class WddmCommandStreamReceiver<SKLFamily>;
template class CommandStreamReceiverWithAUBDump<WddmCommandStreamReceiver<SKLFamily>>;
}
} // namespace OCLRT

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@@ -55,4 +55,4 @@ void gtpinNotifyUpdateResidencyList(void *pKernel, void *pResidencyVector) {
void gtpinNotifyPlatformShutdown() {
}
}
} // namespace OCLRT

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@@ -48,4 +48,4 @@ struct GTPinKernelExec {
};
typedef struct GTPinKernelExec gtpinkexec_t;
} // OCLRT
} // namespace OCLRT

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -27,4 +27,4 @@ gtpin::GTPIN_DI_STATUS gtpinCreateBuffer(gtpin::context_handle_t context, uint32
gtpin::GTPIN_DI_STATUS gtpinFreeBuffer(gtpin::context_handle_t context, gtpin::resource_handle_t resource);
gtpin::GTPIN_DI_STATUS gtpinMapBuffer(gtpin::context_handle_t context, gtpin::resource_handle_t resource, uint8_t **pAddress);
gtpin::GTPIN_DI_STATUS gtpinUnmapBuffer(gtpin::context_handle_t context, gtpin::resource_handle_t resource);
}
} // namespace OCLRT

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@@ -33,7 +33,7 @@ using namespace OCLRT;
namespace OCLRT {
bool isGTPinInitialized = false;
gtpin::ocl::gtpin_events_t GTPinCallbacks = {0};
}
} // namespace OCLRT
GTPIN_DI_STATUS GTPin_Init(gtpin::ocl::gtpin_events_t *pGtpinEvents, driver_services_t *pDriverServices,
uint32_t *pDriverVersion) {

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@@ -36,4 +36,4 @@ void gtpinNotifyMakeResident(void *pKernel, void *pCommandStreamReceiver);
void gtpinNotifyUpdateResidencyList(void *pKernel, void *pResidencyVector);
void gtpinNotifyPlatformShutdown();
inline bool gtpinIsGTPinInitialized() { return isGTPinInitialized; }
}
} // namespace OCLRT

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -28,4 +28,4 @@ namespace OCLRT {
void abortExecution() {
abort();
}
}
} // namespace OCLRT

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -26,4 +26,4 @@ namespace OCLRT {
std::thread::id invalidThreadID;
} // OCLRT
} // namespace OCLRT

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -71,4 +71,4 @@ template class BaseObject<_cl_mem>;
template class BaseObject<_cl_platform_id>;
template class BaseObject<_cl_program>;
template class BaseObject<_cl_sampler>;
}
} // namespace OCLRT

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -27,6 +27,6 @@ namespace CacheSettings {
constexpr uint32_t l3CacheOn = GMM_RESOURCE_USAGE_OCL_BUFFER;
constexpr uint32_t l3CacheOff = GMM_RESOURCE_USAGE_OCL_BUFFER_CACHELINE_MISALIGNED;
constexpr uint32_t unknownMocs = GMM_RESOURCE_USAGE_UNKNOWN;
}
} // namespace CacheSettings
bool isL3Capable(void *ptr, size_t size);

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -35,4 +35,4 @@ bool DispatchInfo::usesStatelessPrintfSurface() const {
uint32_t DispatchInfo::getRequiredScratchSize() const {
return (kernel == nullptr) ? 0 : kernel->getScratchSize();
}
}
} // namespace OCLRT

View File

@@ -75,4 +75,4 @@ void FlatBatchBufferHelper::fixCrossThreadDataInfo(std::vector<PatchInfoData> &d
}
}
}
};
}; // namespace OCLRT

View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -119,4 +119,4 @@ class Hash {
protected:
uint32_t a, hi, lo;
};
}
} // namespace OCLRT

View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -53,4 +53,4 @@ uint32_t PerThreadDataHelper::getThreadPayloadSize(const iOpenCL::SPatchThreadPa
threadPayloadSize += (threadPayload.UnusedPerThreadConstantPresent) ? (sizeof(GRF)) : 0;
return threadPayloadSize;
}
}
} // namespace OCLRT

View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -57,4 +57,4 @@ struct PerThreadDataHelper {
static uint32_t getThreadPayloadSize(const iOpenCL::SPatchThreadPayload &threadPayload, uint32_t simd);
};
}
} // namespace OCLRT

View File

@@ -26,4 +26,4 @@
namespace OCLRT {
const uint32_t pipelineSelectEnablePipelineSelectMaskBits = 0x3;
const uint32_t pipelineSelectMediaSamplerDopClockGateMaskBits = 0x10;
}
} // namespace OCLRT

View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -117,4 +117,4 @@ returnType getCmdQueueProperties(const cl_queue_properties *properties,
}
return retVal;
}
}
} // namespace OCLRT

View File

@@ -39,4 +39,4 @@ struct StateBaseAddressHelper {
uint32_t statelessMocsIndex,
uint64_t internalHeapBase);
};
}
} // namespace OCLRT

View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -218,4 +218,4 @@ const size_t numWriteOnlySurfaceFormats = ARRAY_COUNT(writeOnlySurfaceFormats);
const size_t numReadWriteSurfaceFormats = ARRAY_COUNT(readWriteSurfaceFormats);
// clang-format on
}
} // namespace OCLRT

View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -123,4 +123,4 @@ struct uint16x16_t {
}
};
#endif // __AVX2__
}
} // namespace OCLRT

View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -121,4 +121,4 @@ struct uint16x8_t {
return result;
}
};
}
} // namespace OCLRT

View File

@@ -32,4 +32,4 @@ IndirectHeap::IndirectHeap(GraphicsAllocation *gfxAllocation, bool canBeUtilized
IndirectHeap::IndirectHeap(void *buffer, size_t bufferSize) : BaseClass(buffer, bufferSize) {
}
}
} // namespace OCLRT

View File

@@ -87,4 +87,4 @@ inline uint32_t IndirectHeap::getHeapSizeInPages() const {
return (static_cast<uint32_t>(getMaxAvailableSpace()) + MemoryConstants::pageMask) / MemoryConstants::pageSize;
}
}
}
} // namespace OCLRT

View File

@@ -57,4 +57,4 @@ bool ImageTransformer::didTransform() const {
bool ImageTransformer::hasRegisteredImages3d() const {
return !argIndexes.empty();
}
}
} // namespace OCLRT

View File

@@ -37,4 +37,4 @@ class ImageTransformer {
bool transformed = false;
std::vector<uint32_t> argIndexes;
};
}
} // namespace OCLRT

View File

@@ -1434,7 +1434,7 @@ void Kernel::createReflectionSurface() {
uint32_t parentSamplerCount = objectCount.samplerCount;
size_t maxConstantBufferSize = 0;
std::vector<IGIL_KernelCurbeParams> *curbeParamsForBlocks = new std::vector<IGIL_KernelCurbeParams>[ blockCount ];
std::vector<IGIL_KernelCurbeParams> *curbeParamsForBlocks = new std::vector<IGIL_KernelCurbeParams>[blockCount];
uint64_t *tokenMask = new uint64_t[blockCount];
uint32_t *sshTokenOffsetsFromKernelData = new uint32_t[blockCount];

View File

@@ -78,4 +78,4 @@ void AddressMapper::unmap(void *vm) {
mapping.erase(it);
}
}
}
} // namespace OCLRT

View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -45,4 +45,4 @@ class AddressMapper {
std::vector<MapInfo *> mapping;
std::atomic<uint32_t> nextPage;
};
}
} // namespace OCLRT

View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -30,4 +30,4 @@ class DeferrableDeletion : public IDNode<DeferrableDeletion> {
virtual void apply() = 0;
virtual ~DeferrableDeletion() = default;
};
}
} // namespace OCLRT

View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -43,7 +43,7 @@ static const uintptr_t page64kMask = (pageSize64k - 1);
static const uint64_t max32BitAppAddress = ((1ULL << 31) - 1);
static const uint64_t max64BitAppAddress = ((1ULL << 47) - 1);
static const uint32_t sizeOf4GBinPageEntities = (MemoryConstants::gigaByte * 4 - MemoryConstants::pageSize) / MemoryConstants::pageSize;
}
} // namespace MemoryConstants
const bool is32bit = (sizeof(void *) == 4) ? true : false;
const bool is64bit = (sizeof(void *) == 8) ? true : false;

View File

@@ -146,4 +146,4 @@ PageTable<T, level, bits>::~PageTable() {
template class PageTable<class PDP, 3, 9>;
template class PageTable<class PDE, 2, 2>;
}
} // namespace OCLRT

View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -72,4 +72,4 @@ class PML4 : public PageTable<class PDP, 3> {
};
class PDPE : public PageTable<class PDE, 2, 2> {
};
}
} // namespace OCLRT

View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -36,4 +36,4 @@ class DeviceFactory {
static size_t numDevices;
static HardwareInfo *hwInfos;
};
}
} // namespace OCLRT

View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -54,4 +54,4 @@ std::string EnvironmentVariableReader::getSetting(const char *settingName, const
}
return keyValue;
}
}
} // namespace OCLRT

View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -36,4 +36,4 @@ CommandStreamReceiver *DeviceCommandStreamReceiver<GfxFamily>::create(const Hard
return new DrmCommandStreamReceiver<GfxFamily>(hwInfo, nullptr);
}
};
}
} // namespace OCLRT

View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -49,4 +49,4 @@ class DrmAllocation : public GraphicsAllocation {
protected:
BufferObject *bo;
};
}
} // namespace OCLRT

View File

@@ -117,4 +117,4 @@ void *DrmGemCloseWorker::worker(void *arg) {
self->workerDone.store(true);
return nullptr;
}
}
} // namespace OCLRT

View File

@@ -69,4 +69,4 @@ class DrmGemCloseWorker {
std::condition_variable condition;
std::atomic<bool> workerDone{false};
};
}
} // namespace OCLRT

View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -38,4 +38,4 @@ Drm *Drm::create(int32_t deviceOrdinal) {
void Drm::closeDevice(int32_t deviceOrdinal) {
return;
}
}
} // namespace OCLRT

View File

@@ -59,4 +59,4 @@ class DrmNullDevice : public Drm {
uint64_t gpuTimestamp;
};
}
} // namespace OCLRT

View File

@@ -36,4 +36,4 @@ void Gmm::loadLib() {
Gmm::deleteClientContextFunc = GmmDeleteClientContext;
isLoaded = true;
}
}
} // namespace OCLRT

View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -27,4 +27,4 @@
namespace OCLRT {
class PerfProfiler;
extern thread_local PerfProfiler *gPerfProfiler;
};
}; // namespace OCLRT

View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -63,5 +63,5 @@ void *OsLibrary::getProcAddress(const std::string &procName) {
return dlsym(this->handle, procName.c_str());
}
}
}
} // namespace Linux
} // namespace OCLRT

View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (c) 2017 - 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -37,5 +37,5 @@ class OsLibrary : public OCLRT::OsLibrary {
bool isLoaded() override;
void *getProcAddress(const std::string &procName) override;
};
}
}
} // namespace Linux
} // namespace OCLRT

View File

@@ -34,4 +34,4 @@ std::unique_ptr<Thread> Thread::create(void *(*func)(void *), void *arg) {
void ThreadLinux::join() {
pthread_join(threadId, nullptr);
}
}
} // namespace OCLRT

View File

@@ -32,4 +32,4 @@ class ThreadLinux : public Thread {
protected:
pthread_t threadId;
};
}
} // namespace OCLRT

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