mirror of
https://github.com/intel/compute-runtime.git
synced 2025-12-21 09:14:47 +08:00
Remove code.
Change-Id: I7e578ab0bc7e490520159bfaa4f8f193db40b23e Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
This commit is contained in:
Mrozek, Michal
committed by
sys_ocldev
sys_ocldev
parent
2a2b83f79f
commit
794fba189e
2
Jenkinsfile
vendored
2
Jenkinsfile
vendored
@@ -1,5 +1,5 @@
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#!groovy
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dependenciesRevision='0dea8bf00d710a5d2da5d04eb5ae595d0df4ce47-1217'
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strategy='EQUAL'
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allowedCD=272
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allowedCD=276
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allowedF=4
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@@ -18,7 +18,6 @@
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#include "unit_tests/fixtures/device_fixture.h"
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#include "unit_tests/helpers/debug_manager_state_restore.h"
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#include "unit_tests/helpers/hw_parse.h"
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#include "unit_tests/libult/mock_gfx_family.h"
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#include "unit_tests/mocks/mock_command_queue.h"
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#include "unit_tests/mocks/mock_graphics_allocation.h"
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#include "unit_tests/mocks/mock_kernel.h"
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@@ -1270,18 +1269,6 @@ TEST(DispatchWalker, calculateDispatchDim) {
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}
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}
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HWTEST_F(DispatchWalkerTest, WhenCallingDefaultWaMethodsThenExpectNothing) {
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auto &cmdStream = pCmdQ->getCS(0);
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MockKernel kernel(program.get(), kernelInfo, *pDevice);
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EXPECT_EQ(CL_SUCCESS, kernel.initialize());
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GpgpuWalkerHelper<GENX>::applyWADisableLSQCROPERFforOCL(&cmdStream, kernel, false);
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size_t expectedSize = 0;
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size_t actualSize = GpgpuWalkerHelper<GENX>::getSizeForWADisableLSQCROPERFforOCL(&kernel);
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EXPECT_EQ(expectedSize, actualSize);
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}
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HWTEST_F(DispatchWalkerTest, givenKernelWhenAuxTranslationRequiredThenPipeControlWithStallAndDCFlushAdded) {
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MockKernel kernel(program.get(), kernelInfo, *pDevice);
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kernelInfo.workloadInfo.workDimOffset = 0;
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@@ -14,7 +14,6 @@
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#include "runtime/platform/platform.h"
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#include "unit_tests/helpers/debug_manager_state_restore.h"
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#include "unit_tests/helpers/variable_backup.h"
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#include "unit_tests/libult/mock_gfx_family.h"
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#include "unit_tests/mocks/mock_device.h"
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#include "unit_tests/mocks/mock_gmm.h"
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#include "unit_tests/mocks/mock_graphics_allocation.h"
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@@ -744,39 +743,4 @@ TEST(GmmHelperTest, whenGmmHelperIsInitializedThenClientContextIsSet) {
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EXPECT_NE(nullptr, GmmHelper::getClientContext()->getHandle());
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}
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struct GmmQueryInfoWithoutYTilingTest : public ::testing::Test {
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GmmQueryInfoWithoutYTilingTest() : enabledYTilingBackup(&GENX::enabledYTiling, false),
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renderCoreFamilyBackup(const_cast<GFXCORE_FAMILY *>(&platformDevices[0]->pPlatform->eRenderCoreFamily), IGFX_UNKNOWN_CORE) {}
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VariableBackup<bool> enabledYTilingBackup;
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VariableBackup<GFXCORE_FAMILY> renderCoreFamilyBackup;
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};
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TEST_F(GmmQueryInfoWithoutYTilingTest, givenPlatformThatDoesntSupportYTilingWhenQueryImageParamsForTilableImageThenTilingIsDisabled) {
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cl_image_desc imgDesc{};
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imgDesc.image_type = CL_MEM_OBJECT_IMAGE3D;
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imgDesc.image_width = 17;
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imgDesc.image_height = 17;
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imgDesc.image_depth = 17;
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auto imgInfo = MockGmm::initImgInfo(imgDesc, 0, nullptr);
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auto queryGmm = MockGmm::queryImgParams(imgInfo);
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EXPECT_EQ(queryGmm->resourceParams.Flags.Info.Linear, 0u);
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EXPECT_EQ(queryGmm->resourceParams.Flags.Info.TiledY, 0u);
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}
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TEST_F(GmmQueryInfoWithoutYTilingTest, givenPlatformThatDoesntSupportYTilingWhenQueryImageParamsForUntilableImageThenLinearPropertyRemains) {
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cl_image_desc imgDesc{};
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imgDesc.image_type = CL_MEM_OBJECT_IMAGE1D;
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imgDesc.image_width = 17;
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auto imgInfo = MockGmm::initImgInfo(imgDesc, 0, nullptr);
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auto queryGmm = MockGmm::queryImgParams(imgInfo);
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EXPECT_EQ(queryGmm->resourceParams.Flags.Info.Linear, 1u);
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EXPECT_EQ(queryGmm->resourceParams.Flags.Info.TiledY, 0u);
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}
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} // namespace NEO
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@@ -35,8 +35,6 @@ set(IGDRCL_SRCS_LIB_ULT
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${IGDRCL_SOURCE_DIR}/unit_tests/libult/source_level_debugger_library.h
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${IGDRCL_SOURCE_DIR}/unit_tests/program/evaluate_unhandled_token_ult.cpp
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${IGDRCL_SOURCE_DIR}/unit_tests/utilities/debug_settings_reader_creator.cpp
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${CMAKE_CURRENT_SOURCE_DIR}/mock_gfx_family.h
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${CMAKE_CURRENT_SOURCE_DIR}/mock_gfx_family.cpp
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)
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set(IGDRCL_SRCS_LIB_ULT_WINDOWS
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@@ -1,190 +0,0 @@
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/*
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* Copyright (C) 2017-2019 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#include "unit_tests/libult/mock_gfx_family.h"
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#include "runtime/command_queue/gpgpu_walker.inl"
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#include "runtime/command_queue/gpgpu_walker_base.inl"
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#include "runtime/command_stream/preemption.inl"
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#include "runtime/device_queue/device_queue_hw.h"
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#include "runtime/device_queue/device_queue_hw.inl"
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#include "runtime/gen_common/aub_mapper.h"
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#include "runtime/helpers/hw_helper_common.inl"
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#include "runtime/helpers/kernel_commands.inl"
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#include "runtime/helpers/kernel_commands_base.inl"
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#include "runtime/helpers/preamble.inl"
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namespace NEO {
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static AubMemDump::LrcaHelperRcs rcs(0x000000);
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static AubMemDump::LrcaHelperBcs bcs(0x020000);
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static AubMemDump::LrcaHelperVcs vcs(0x010000);
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static AubMemDump::LrcaHelperVecs vecs(0x018000);
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const AubMemDump::LrcaHelper *AUBFamilyMapper<GENX>::csTraits[aub_stream::NUM_ENGINES] = {
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&rcs,
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&bcs,
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&vcs,
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&vecs};
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const MMIOList AUBFamilyMapper<GENX>::globalMMIO;
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bool (*GENX::isSimulationFcn)(unsigned short) = nullptr;
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GENX::GPGPU_WALKER GENX::cmdInitGpgpuWalker = GENX::GPGPU_WALKER::sInit();
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GENX::INTERFACE_DESCRIPTOR_DATA GENX::cmdInitInterfaceDescriptorData = GENX::INTERFACE_DESCRIPTOR_DATA::sInit();
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GENX::MEDIA_STATE_FLUSH GENX::cmdInitMediaStateFlush = GENX::MEDIA_STATE_FLUSH::sInit();
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GENX::MEDIA_INTERFACE_DESCRIPTOR_LOAD GENX::cmdInitMediaInterfaceDescriptorLoad = GENX::MEDIA_INTERFACE_DESCRIPTOR_LOAD::sInit();
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GENX::MI_SEMAPHORE_WAIT GENX::cmdInitMiSemaphoreWait = GENX::MI_SEMAPHORE_WAIT::sInit();
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GENX::RENDER_SURFACE_STATE GENX::cmdInitRenderSurfaceState = GENX::RENDER_SURFACE_STATE::sInit();
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GENX::MI_LOAD_REGISTER_IMM GENX::cmdInitLoadRegisterImm = GENX::MI_LOAD_REGISTER_IMM::sInit();
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GENX::MI_LOAD_REGISTER_REG GENX::cmdInitLoadRegisterReg = GENX::MI_LOAD_REGISTER_REG::sInit();
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GENX::MI_LOAD_REGISTER_MEM GENX::cmdInitLoadRegisterMem = GENX::MI_LOAD_REGISTER_MEM::sInit();
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GENX::MI_STORE_DATA_IMM GENX::cmdInitStoreDataImm = GENX::MI_STORE_DATA_IMM::sInit();
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GENX::MI_STORE_REGISTER_MEM GENX::cmdInitStoreRegisterMem = GENX::MI_STORE_REGISTER_MEM::sInit();
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GENX::MI_NOOP GENX::cmdInitNoop = GENX::MI_NOOP::sInit();
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GENX::MI_BATCH_BUFFER_START GENX::cmdInitBatchBufferStart = GENX::MI_BATCH_BUFFER_START::sInit();
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GENX::MI_BATCH_BUFFER_END GENX::cmdInitBatchBufferEnd = GENX::MI_BATCH_BUFFER_END::sInit();
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GENX::MI_REPORT_PERF_COUNT GENX::cmdInitReportPerfCount = GENX::MI_REPORT_PERF_COUNT::sInit();
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GENX::MI_ATOMIC GENX::cmdInitAtomic = GENX::MI_ATOMIC::sInit();
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GENX::PIPELINE_SELECT GENX::cmdInitPipelineSelect = GENX::PIPELINE_SELECT::sInit();
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GENX::MI_ARB_CHECK GENX::cmdInitArbCheck = GENX::MI_ARB_CHECK::sInit();
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GENX::MEDIA_VFE_STATE GENX::cmdInitMediaVfeState = GENX::MEDIA_VFE_STATE::sInit();
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GENX::STATE_BASE_ADDRESS GENX::cmdInitStateBaseAddress = GENX::STATE_BASE_ADDRESS::sInit();
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GENX::MEDIA_SURFACE_STATE GENX::cmdInitMediaSurfaceState = GENX::MEDIA_SURFACE_STATE::sInit();
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GENX::SAMPLER_STATE GENX::cmdInitSamplerState = GENX::SAMPLER_STATE::sInit();
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GENX::GPGPU_CSR_BASE_ADDRESS GENX::cmdInitGpgpuCsrBaseAddress = GENX::GPGPU_CSR_BASE_ADDRESS::sInit();
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GENX::STATE_SIP GENX::cmdInitStateSip = GENX::STATE_SIP::sInit();
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GENX::BINDING_TABLE_STATE GENX::cmdInitBindingTableState = GENX::BINDING_TABLE_STATE::sInit();
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GENX::MI_USER_INTERRUPT GENX::cmdInitUserInterrupt = GENX::MI_USER_INTERRUPT::sInit();
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bool GENX::enabledYTiling = true;
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template <>
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size_t HwHelperHw<GENX>::getMaxBarrierRegisterPerSlice() const {
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return 32;
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}
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template <>
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void HwHelperHw<GENX>::setCapabilityCoherencyFlag(const HardwareInfo *pHwInfo, bool &coherencyFlag) {
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coherencyFlag = (pHwInfo->pPlatform->usDeviceID != 20);
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}
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template <>
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bool HwHelperHw<GENX>::setupPreemptionRegisters(HardwareInfo *pHwInfo, bool enable) {
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pHwInfo->capabilityTable.whitelistedRegisters.csChicken1_0x2580 = enable;
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return enable;
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}
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template <>
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const AubMemDump::LrcaHelper &HwHelperHw<GENX>::getCsTraits(aub_stream::EngineType engineType) const {
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return *AUBFamilyMapper<GENX>::csTraits[engineType];
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}
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template <>
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bool HwHelperHw<GENX>::supportsYTiling() const {
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return GENX::enabledYTiling;
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}
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template class HwHelperHw<GENX>;
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struct hw_helper_static_init {
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hw_helper_static_init() {
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hwHelperFactory[IGFX_UNKNOWN_CORE] = &HwHelperHw<GENX>::get();
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}
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};
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hw_helper_static_init si;
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template class GpgpuWalkerHelper<GENX>;
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template <>
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bool KernelCommandsHelper<GENX>::isPipeControlWArequired() {
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return false;
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}
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template struct KernelCommandsHelper<GENX>;
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template <>
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size_t PreemptionHelper::getRequiredCmdStreamSize<GENX>(PreemptionMode newPreemptionMode, PreemptionMode oldPreemptionMode) {
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return 0;
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}
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template <>
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void PreemptionHelper::programCmdStream<GENX>(LinearStream &cmdStream, PreemptionMode newPreemptionMode, PreemptionMode oldPreemptionMode,
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GraphicsAllocation *preemptionCsr, Device &device) {
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}
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template <>
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size_t PreemptionHelper::getRequiredPreambleSize<GENX>(const Device &device) {
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return 0;
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}
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template <>
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size_t PreemptionHelper::getRequiredStateSipCmdSize<GENX>(const Device &device) {
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return 0;
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}
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template <>
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void PreemptionHelper::programStateSip<GENX>(LinearStream &preambleCmdStream, Device &device) {
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}
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template <>
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size_t PreemptionHelper::getPreemptionWaCsSize<GENX>(const Device &device) {
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return 0;
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}
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template void PreemptionHelper::programInterfaceDescriptorDataPreemption<GENX>(INTERFACE_DESCRIPTOR_DATA<GENX> *idd, PreemptionMode preemptionMode);
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template <>
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size_t DeviceQueueHw<GENX>::getWaCommandsSize() {
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return (size_t)0;
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}
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template <>
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void DeviceQueueHw<GENX>::addArbCheckCmdWa() {
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}
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template <>
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void DeviceQueueHw<GENX>::addMiAtomicCmdWa(uint64_t atomicOpPlaceholder) {
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}
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template <>
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void DeviceQueueHw<GENX>::addLriCmdWa(bool setArbCheck) {
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}
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template <>
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void DeviceQueueHw<GENX>::addPipeControlCmdWa(bool isNoopCmd) {
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}
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template <>
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void DeviceQueueHw<GENX>::addProfilingEndCmds(uint64_t timestampAddress) {
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}
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template class DeviceQueueHw<GENX>;
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template <>
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void PreambleHelper<GENX>::addPipeControlBeforeVfeCmd(LinearStream *pCommandStream, const HardwareInfo *hwInfo) {
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}
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template <>
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uint32_t PreambleHelper<GENX>::getL3Config(const HardwareInfo &hwInfo, bool useSLM) {
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uint32_t l3Config = 0;
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return l3Config;
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}
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template <>
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void PreambleHelper<GENX>::programPipelineSelect(LinearStream *pCommandStream, const DispatchFlags &dispatchFlags) {
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}
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template <>
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struct L3CNTLRegisterOffset<GENX> {
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static const uint32_t registerOffset = 0x7034;
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};
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template struct PreambleHelper<GENX>;
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} // namespace NEO
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@@ -1,551 +0,0 @@
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/*
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* Copyright (C) 2018-2019 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#pragma once
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#include "runtime/gen_common/aub_mapper_base.h"
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#include "runtime/helpers/hw_helper.h"
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namespace NEO {
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extern HwHelper *hwHelperFactory[IGFX_MAX_CORE];
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struct GENX {
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static bool (*isSimulationFcn)(unsigned short);
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static bool enabledYTiling;
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typedef struct tagINTERFACE_DESCRIPTOR_DATA {
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typedef enum tagDENORM_MODE {
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DENORM_MODE_FTZ = 0x0,
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DENORM_MODE_SETBYKERNEL = 0x1,
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} DENORM_MODE;
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typedef enum tagSAMPLERSTATEPOINTER {
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SAMPLERSTATEPOINTER_BIT_SHIFT = 0x5,
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SAMPLERSTATEPOINTER_ALIGN_SIZE = 0x20,
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} SAMPLERSTATEPOINTER;
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typedef enum tagSAMPLER_COUNT {
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SAMPLER_COUNT_NO_SAMPLERS_USED = 0x0,
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SAMPLER_COUNT_BETWEEN_1_AND_4_SAMPLERS_USED = 0x1,
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SAMPLER_COUNT_BETWEEN_5_AND_8_SAMPLERS_USED = 0x2,
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SAMPLER_COUNT_BETWEEN_9_AND_12_SAMPLERS_USED = 0x3,
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SAMPLER_COUNT_BETWEEN_13_AND_16_SAMPLERS_USED = 0x4,
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} SAMPLER_COUNT;
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typedef enum tagSHARED_LOCAL_MEMORY_SIZE {
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SHARED_LOCAL_MEMORY_SIZE_ENCODES_0K = 0x0,
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SHARED_LOCAL_MEMORY_SIZE_ENCODES_1K = 0x1,
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SHARED_LOCAL_MEMORY_SIZE_ENCODES_2K = 0x2,
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SHARED_LOCAL_MEMORY_SIZE_ENCODES_4K = 0x3,
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SHARED_LOCAL_MEMORY_SIZE_ENCODES_8K = 0x4,
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SHARED_LOCAL_MEMORY_SIZE_ENCODES_16K = 0x5,
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SHARED_LOCAL_MEMORY_SIZE_ENCODES_32K = 0x6,
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SHARED_LOCAL_MEMORY_SIZE_ENCODES_64K = 0x7,
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} SHARED_LOCAL_MEMORY_SIZE;
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typedef enum tagBINDINGTABLEPOINTER {
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BINDINGTABLEPOINTER_BIT_SHIFT = 0x5,
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BINDINGTABLEPOINTER_ALIGN_SIZE = 0x20,
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} BINDINGTABLEPOINTER;
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static tagINTERFACE_DESCRIPTOR_DATA sInit(void) {
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INTERFACE_DESCRIPTOR_DATA state;
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return state;
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}
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inline void setKernelStartPointerHigh(const uint32_t value) {
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}
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inline void setKernelStartPointer(const uint64_t value) {
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}
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inline void setNumberOfThreadsInGpgpuThreadGroup(const uint32_t value) {
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}
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inline void setCrossThreadConstantDataReadLength(const uint32_t value) {
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}
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inline void setDenormMode(const DENORM_MODE value) {
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}
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inline void setConstantIndirectUrbEntryReadLength(const uint32_t value) {
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}
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inline void setBindingTablePointer(const uint64_t value) {
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}
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inline void setSamplerStatePointer(const uint64_t value) {
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}
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inline void setSamplerCount(const SAMPLER_COUNT value) {
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}
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inline void setSharedLocalMemorySize(const SHARED_LOCAL_MEMORY_SIZE value) {
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}
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inline void setBarrierEnable(const bool value) {
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}
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inline void setBindingTableEntryCount(const uint32_t value) {
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}
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} INTERFACE_DESCRIPTOR_DATA;
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typedef struct tagBINDING_TABLE_STATE {
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static tagBINDING_TABLE_STATE sInit(void) {
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BINDING_TABLE_STATE state;
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return state;
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}
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inline void init(void) {
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}
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inline uint32_t getSurfaceStatePointer(void) const {
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return 0u;
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}
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inline void setSurfaceStatePointer(const uint64_t value) {
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}
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inline uint32_t getRawData(const uint32_t index) {
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return 0;
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}
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typedef enum tagSURFACESTATEPOINTER {
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SURFACESTATEPOINTER_BIT_SHIFT = 0x6,
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SURFACESTATEPOINTER_ALIGN_SIZE = 0x40,
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} SURFACESTATEPOINTER;
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} BINDING_TABLE_STATE;
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typedef struct tagGPGPU_WALKER {
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typedef enum tagSIMD_SIZE {
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SIMD_SIZE_SIMD8 = 0x0,
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SIMD_SIZE_SIMD16 = 0x1,
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SIMD_SIZE_SIMD32 = 0x2,
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} SIMD_SIZE;
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typedef enum tagINDIRECTDATASTARTADDRESS {
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INDIRECTDATASTARTADDRESS_BIT_SHIFT = 0x6,
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INDIRECTDATASTARTADDRESS_ALIGN_SIZE = 0x40,
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} INDIRECTDATASTARTADDRESS;
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static tagGPGPU_WALKER sInit(void) {
|
||||
GPGPU_WALKER state;
|
||||
return state;
|
||||
}
|
||||
inline void setThreadWidthCounterMaximum(const uint32_t value) {
|
||||
}
|
||||
inline void setThreadGroupIdXDimension(const uint32_t value) {
|
||||
}
|
||||
inline void setThreadGroupIdYDimension(const uint32_t value) {
|
||||
}
|
||||
inline void setThreadGroupIdZDimension(const uint32_t value) {
|
||||
}
|
||||
inline void setRightExecutionMask(const uint32_t value) {
|
||||
}
|
||||
inline void setBottomExecutionMask(const uint32_t value) {
|
||||
}
|
||||
inline void setSimdSize(const SIMD_SIZE value) {
|
||||
}
|
||||
inline void setThreadGroupIdStartingX(const uint32_t value) {
|
||||
}
|
||||
inline void setThreadGroupIdStartingY(const uint32_t value) {
|
||||
}
|
||||
inline void setThreadGroupIdStartingResumeZ(const uint32_t value) {
|
||||
}
|
||||
inline void setIndirectDataStartAddress(const uint32_t value) {
|
||||
}
|
||||
inline void setInterfaceDescriptorOffset(const uint32_t value) {
|
||||
}
|
||||
inline void setIndirectDataLength(const uint32_t value) {
|
||||
}
|
||||
} GPGPU_WALKER;
|
||||
|
||||
typedef struct tagPIPE_CONTROL {
|
||||
typedef enum tagPOST_SYNC_OPERATION {
|
||||
POST_SYNC_OPERATION_NO_WRITE = 0x0,
|
||||
POST_SYNC_OPERATION_WRITE_IMMEDIATE_DATA = 0x1,
|
||||
POST_SYNC_OPERATION_WRITE_PS_DEPTH_COUNT = 0x2,
|
||||
POST_SYNC_OPERATION_WRITE_TIMESTAMP = 0x3,
|
||||
} POST_SYNC_OPERATION;
|
||||
static tagPIPE_CONTROL sInit(void) {
|
||||
PIPE_CONTROL state;
|
||||
return state;
|
||||
}
|
||||
inline void setCommandStreamerStallEnable(const uint32_t value) {
|
||||
}
|
||||
inline void setDcFlushEnable(const bool value) {
|
||||
}
|
||||
inline void setStateCacheInvalidationEnable(const bool value) {
|
||||
}
|
||||
inline void setPipeControlFlushEnable(const bool value) {
|
||||
}
|
||||
inline void setTextureCacheInvalidationEnable(const bool value) {
|
||||
}
|
||||
inline void setPostSyncOperation(const POST_SYNC_OPERATION value) {
|
||||
}
|
||||
inline void setAddress(const uint32_t value) {
|
||||
}
|
||||
inline void setAddressHigh(const uint32_t value) {
|
||||
}
|
||||
inline void setImmediateData(const uint64_t value) {
|
||||
}
|
||||
inline void setGenericMediaStateClear(const bool value) {
|
||||
}
|
||||
inline void setRenderTargetCacheFlushEnable(const bool value) {
|
||||
}
|
||||
inline void setInstructionCacheInvalidateEnable(const bool value) {
|
||||
}
|
||||
inline void setVfCacheInvalidationEnable(const bool value) {
|
||||
}
|
||||
inline void setConstantCacheInvalidationEnable(const bool value) {
|
||||
}
|
||||
} PIPE_CONTROL;
|
||||
|
||||
typedef struct tagMI_LOAD_REGISTER_IMM {
|
||||
static tagMI_LOAD_REGISTER_IMM sInit(void) {
|
||||
MI_LOAD_REGISTER_IMM state;
|
||||
return state;
|
||||
}
|
||||
inline void setRegisterOffset(const uint32_t value) {
|
||||
}
|
||||
inline void setDataDword(const uint32_t value) {
|
||||
}
|
||||
} MI_LOAD_REGISTER_IMM;
|
||||
|
||||
typedef struct tagMI_LOAD_REGISTER_REG {
|
||||
static tagMI_LOAD_REGISTER_REG sInit(void) {
|
||||
MI_LOAD_REGISTER_REG state;
|
||||
return state;
|
||||
}
|
||||
inline void setSourceRegisterAddress(const uint32_t value) {
|
||||
}
|
||||
inline void setDestinationRegisterAddress(const uint32_t value) {
|
||||
}
|
||||
} MI_LOAD_REGISTER_REG;
|
||||
|
||||
typedef struct tagMI_MATH {
|
||||
union _DW0 {
|
||||
struct _BitField {
|
||||
uint32_t DwordLength : BITFIELD_RANGE(0, 5);
|
||||
uint32_t Reserved : BITFIELD_RANGE(6, 22);
|
||||
uint32_t InstructionOpcode : BITFIELD_RANGE(23, 28);
|
||||
uint32_t InstructionType : BITFIELD_RANGE(29, 31);
|
||||
} BitField;
|
||||
uint32_t Value;
|
||||
} DW0;
|
||||
typedef enum tagMI_COMMAND_OPCODE {
|
||||
MI_COMMAND_OPCODE_MI_MATH = 0x0,
|
||||
} MI_COMMAND_OPCODE;
|
||||
typedef enum tagCOMMAND_TYPE {
|
||||
COMMAND_TYPE_MI_COMMAND = 0x0,
|
||||
} COMMAND_TYPE;
|
||||
} MI_MATH;
|
||||
|
||||
typedef struct tagMI_MATH_ALU_INST_INLINE {
|
||||
union _DW0 {
|
||||
struct _BitField {
|
||||
uint32_t Operand2 : BITFIELD_RANGE(0, 9);
|
||||
uint32_t Operand1 : BITFIELD_RANGE(10, 19);
|
||||
uint32_t ALUOpcode : BITFIELD_RANGE(20, 31);
|
||||
} BitField;
|
||||
uint32_t Value;
|
||||
} DW0;
|
||||
} MI_MATH_ALU_INST_INLINE;
|
||||
|
||||
typedef struct tagMI_COMMAND_OPCODE_MI_MATH {
|
||||
} MI_COMMAND_OPCODE_MI_MATH;
|
||||
|
||||
typedef struct tagMI_STORE_REGISTER_MEM {
|
||||
static tagMI_STORE_REGISTER_MEM sInit(void) {
|
||||
MI_STORE_REGISTER_MEM state;
|
||||
return state;
|
||||
}
|
||||
inline void setRegisterAddress(const uint32_t value) {
|
||||
}
|
||||
inline void setMemoryAddress(const uint64_t value) {
|
||||
}
|
||||
} MI_STORE_REGISTER_MEM;
|
||||
|
||||
typedef struct tagMI_REPORT_PERF_COUNT {
|
||||
static tagMI_REPORT_PERF_COUNT sInit(void) {
|
||||
MI_REPORT_PERF_COUNT state;
|
||||
return state;
|
||||
}
|
||||
inline void setReportId(const uint32_t value) {
|
||||
}
|
||||
inline void setMemoryAddress(const uint64_t value) {
|
||||
}
|
||||
} MI_REPORT_PERF_COUNT;
|
||||
|
||||
typedef struct tagMI_BATCH_BUFFER_START {
|
||||
typedef enum tagSECOND_LEVEL_BATCH_BUFFER {
|
||||
SECOND_LEVEL_BATCH_BUFFER_FIRST_LEVEL_BATCH = 0x0,
|
||||
SECOND_LEVEL_BATCH_BUFFER_SECOND_LEVEL_BATCH = 0x1,
|
||||
} SECOND_LEVEL_BATCH_BUFFER;
|
||||
static tagMI_BATCH_BUFFER_START sInit(void) {
|
||||
MI_BATCH_BUFFER_START state;
|
||||
return state;
|
||||
}
|
||||
inline void setSecondLevelBatchBuffer(const SECOND_LEVEL_BATCH_BUFFER value) {
|
||||
}
|
||||
inline void setBatchBufferStartAddressGraphicsaddress472(const uint64_t value) {
|
||||
}
|
||||
} MI_BATCH_BUFFER_START;
|
||||
|
||||
typedef struct tagMEDIA_STATE_FLUSH {
|
||||
static tagMEDIA_STATE_FLUSH sInit(void) {
|
||||
MEDIA_STATE_FLUSH state;
|
||||
return state;
|
||||
}
|
||||
inline void setInterfaceDescriptorOffset(const uint32_t value) {
|
||||
}
|
||||
} MEDIA_STATE_FLUSH;
|
||||
|
||||
typedef struct tagMEDIA_INTERFACE_DESCRIPTOR_LOAD {
|
||||
static tagMEDIA_INTERFACE_DESCRIPTOR_LOAD sInit(void) {
|
||||
MEDIA_INTERFACE_DESCRIPTOR_LOAD state;
|
||||
return state;
|
||||
}
|
||||
inline void setInterfaceDescriptorDataStartAddress(const uint32_t value) {
|
||||
}
|
||||
inline void setInterfaceDescriptorTotalLength(const uint32_t value) {
|
||||
}
|
||||
} MEDIA_INTERFACE_DESCRIPTOR_LOAD;
|
||||
|
||||
typedef struct tagMI_BATCH_BUFFER_END {
|
||||
static tagMI_BATCH_BUFFER_END sInit(void) {
|
||||
MI_BATCH_BUFFER_END state;
|
||||
return state;
|
||||
}
|
||||
} MI_BATCH_BUFFER_END;
|
||||
|
||||
typedef struct tagRENDER_SURFACE_STATE {
|
||||
typedef enum tagSURFACE_VERTICAL_ALIGNMENT {
|
||||
SURFACE_VERTICAL_ALIGNMENT_VALIGN_4 = 0x1,
|
||||
} SURFACE_VERTICAL_ALIGNMENT;
|
||||
typedef enum tagSURFACE_HORIZONTAL_ALIGNMENT {
|
||||
SURFACE_HORIZONTAL_ALIGNMENT_HALIGN_4 = 0x1,
|
||||
} SURFACE_HORIZONTAL_ALIGNMENT;
|
||||
typedef enum tagTILE_MODE {
|
||||
TILE_MODE_LINEAR = 0x0,
|
||||
} TILE_MODE;
|
||||
typedef enum tagSURFACE_TYPE {
|
||||
SURFACE_TYPE_SURFTYPE_BUFFER = 0x4,
|
||||
SURFACE_TYPE_SURFTYPE_NULL = 0x7
|
||||
} SURFACE_TYPE;
|
||||
typedef enum tagSURFACE_FORMAT {
|
||||
SURFACE_FORMAT_RAW = 0x1ff,
|
||||
} SURFACE_FORMAT;
|
||||
typedef enum tagAUXILIARY_SURFACE_MODE {
|
||||
AUXILIARY_SURFACE_MODE_AUX_NONE = 0x0,
|
||||
AUXILIARY_SURFACE_MODE_AUX_CCS_E = 0x5,
|
||||
} AUXILIARY_SURFACE_MODE;
|
||||
typedef enum tagCOHERENCY_TYPE {
|
||||
COHERENCY_TYPE_GPU_COHERENT = 0x0,
|
||||
COHERENCY_TYPE_IA_COHERENT = 0x1,
|
||||
} COHERENCY_TYPE;
|
||||
static tagRENDER_SURFACE_STATE sInit(void) {
|
||||
RENDER_SURFACE_STATE state;
|
||||
return state;
|
||||
}
|
||||
inline void setWidth(const uint32_t value) {
|
||||
}
|
||||
inline void setHeight(const uint32_t value) {
|
||||
}
|
||||
inline void setDepth(const uint32_t value) {
|
||||
}
|
||||
inline void setSurfacePitch(const uint32_t value) {
|
||||
}
|
||||
inline void setSurfaceType(const SURFACE_TYPE value) {
|
||||
}
|
||||
inline void setSurfaceFormat(const SURFACE_FORMAT value) {
|
||||
}
|
||||
inline void setSurfaceVerticalAlignment(const SURFACE_VERTICAL_ALIGNMENT value) {
|
||||
}
|
||||
inline void setSurfaceHorizontalAlignment(const SURFACE_HORIZONTAL_ALIGNMENT value) {
|
||||
}
|
||||
inline void setTileMode(const TILE_MODE value) {
|
||||
}
|
||||
inline void setVerticalLineStride(const uint32_t value) {
|
||||
}
|
||||
inline void setVerticalLineStrideOffset(const uint32_t value) {
|
||||
}
|
||||
inline void setMemoryObjectControlState(const uint32_t value) {
|
||||
}
|
||||
inline void setSurfaceBaseAddress(const uint64_t value) {
|
||||
}
|
||||
inline void setCoherencyType(const COHERENCY_TYPE value) {
|
||||
}
|
||||
inline void setAuxiliarySurfaceMode(const AUXILIARY_SURFACE_MODE value) {
|
||||
}
|
||||
} RENDER_SURFACE_STATE;
|
||||
|
||||
typedef struct tagMEDIA_VFE_STATE {
|
||||
static tagMEDIA_VFE_STATE sInit(void) {
|
||||
MEDIA_VFE_STATE state;
|
||||
return state;
|
||||
}
|
||||
inline void setMaximumNumberOfThreads(const uint32_t value) {
|
||||
}
|
||||
inline void setNumberOfUrbEntries(const uint32_t value) {
|
||||
}
|
||||
inline void setUrbEntryAllocationSize(const uint32_t value) {
|
||||
}
|
||||
inline void setPerThreadScratchSpace(const uint32_t value) {
|
||||
}
|
||||
inline void setStackSize(const uint32_t value) {
|
||||
}
|
||||
inline void setScratchSpaceBasePointer(const uint32_t value) {
|
||||
}
|
||||
inline void setScratchSpaceBasePointerHigh(const uint32_t value) {
|
||||
}
|
||||
} MEDIA_VFE_STATE;
|
||||
|
||||
typedef struct tagSAMPLER_STATE {
|
||||
static tagSAMPLER_STATE sInit(void) {
|
||||
SAMPLER_STATE state;
|
||||
return state;
|
||||
}
|
||||
inline void setIndirectStatePointer(const uint32_t indirectStatePointerValue) {
|
||||
}
|
||||
} SAMPLER_STATE;
|
||||
|
||||
typedef struct tagGPGPU_CSR_BASE_ADDRESS {
|
||||
static tagGPGPU_CSR_BASE_ADDRESS sInit(void) {
|
||||
GPGPU_CSR_BASE_ADDRESS state;
|
||||
return state;
|
||||
}
|
||||
inline void init(void) {
|
||||
}
|
||||
inline void setGpgpuCsrBaseAddress(uint64_t value) {
|
||||
}
|
||||
} GPGPU_CSR_BASE_ADDRESS;
|
||||
|
||||
typedef struct tagSTATE_SIP {
|
||||
static tagSTATE_SIP sInit(void) {
|
||||
STATE_SIP state;
|
||||
return state;
|
||||
}
|
||||
inline void init(void) {
|
||||
}
|
||||
inline void setSystemInstructionPointer(uint64_t value) {
|
||||
}
|
||||
} STATE_SIP;
|
||||
|
||||
typedef struct tagMI_SEMAPHORE_WAIT {
|
||||
typedef enum tagCOMPARE_OPERATION {
|
||||
COMPARE_OPERATION_SAD_NOT_EQUAL_SDD = 0x5,
|
||||
} COMPARE_OPERATION;
|
||||
|
||||
typedef enum tagWAIT_MODE {
|
||||
WAIT_MODE_SIGNAL_MODE = 0x0,
|
||||
WAIT_MODE_POLLING_MODE = 0x1,
|
||||
} WAIT_MODE;
|
||||
|
||||
static tagMI_SEMAPHORE_WAIT sInit(void) {
|
||||
MI_SEMAPHORE_WAIT state;
|
||||
return state;
|
||||
}
|
||||
|
||||
inline void setSemaphoreDataDword(uint32_t value) {}
|
||||
inline void setSemaphoreGraphicsAddress(uint64_t value) {}
|
||||
inline void setCompareOperation(COMPARE_OPERATION value) {}
|
||||
inline void setWaitMode(const WAIT_MODE value) {}
|
||||
} MI_SEMAPHORE_WAIT;
|
||||
|
||||
typedef struct tagMI_ATOMIC {
|
||||
typedef enum tagATOMIC_OPCODES {
|
||||
ATOMIC_4B_DECREMENT = 0x6,
|
||||
ATOMIC_8B_INCREMENT = 0x25,
|
||||
ATOMIC_8B_DECREMENT = 0x26,
|
||||
} ATOMIC_OPCODES;
|
||||
typedef enum tagDATA_SIZE {
|
||||
DATA_SIZE_DWORD = 0x0,
|
||||
DATA_SIZE_QWORD = 0x1,
|
||||
DATA_SIZE_OCTWORD = 0x2,
|
||||
} DATA_SIZE;
|
||||
|
||||
static tagMI_ATOMIC sInit(void) {
|
||||
tagMI_ATOMIC state;
|
||||
return state;
|
||||
}
|
||||
inline void setAtomicOpcode(ATOMIC_OPCODES) {}
|
||||
inline void setDataSize(DATA_SIZE) {}
|
||||
inline void setMemoryAddress(uint32_t) {}
|
||||
inline void setMemoryAddressHigh(uint32_t) {}
|
||||
} MI_ATOMIC;
|
||||
|
||||
typedef struct tagMI_LOAD_REGISTER_MEM {
|
||||
static tagMI_LOAD_REGISTER_MEM sInit(void) {
|
||||
MI_LOAD_REGISTER_MEM state;
|
||||
return state;
|
||||
}
|
||||
} MI_LOAD_REGISTER_MEM;
|
||||
|
||||
typedef struct tagMI_STORE_DATA_IMM {
|
||||
static tagMI_STORE_DATA_IMM sInit(void) {
|
||||
MI_STORE_DATA_IMM state;
|
||||
return state;
|
||||
}
|
||||
} MI_STORE_DATA_IMM;
|
||||
|
||||
typedef struct tagMI_NOOP {
|
||||
static tagMI_NOOP sInit(void) {
|
||||
MI_NOOP state;
|
||||
return state;
|
||||
}
|
||||
} MI_NOOP;
|
||||
|
||||
typedef struct tagPIPELINE_SELECT {
|
||||
static tagPIPELINE_SELECT sInit(void) {
|
||||
PIPELINE_SELECT state;
|
||||
return state;
|
||||
}
|
||||
} PIPELINE_SELECT;
|
||||
|
||||
typedef struct tagMI_ARB_CHECK {
|
||||
static tagMI_ARB_CHECK sInit(void) {
|
||||
MI_ARB_CHECK state;
|
||||
return state;
|
||||
}
|
||||
} MI_ARB_CHECK;
|
||||
|
||||
typedef struct tagSTATE_BASE_ADDRESS {
|
||||
static tagSTATE_BASE_ADDRESS sInit(void) {
|
||||
STATE_BASE_ADDRESS state;
|
||||
return state;
|
||||
}
|
||||
} STATE_BASE_ADDRESS;
|
||||
|
||||
typedef struct tagMEDIA_SURFACE_STATE {
|
||||
static tagMEDIA_SURFACE_STATE sInit(void) {
|
||||
MEDIA_SURFACE_STATE state;
|
||||
return state;
|
||||
}
|
||||
} MEDIA_SURFACE_STATE;
|
||||
|
||||
typedef struct tagMI_USER_INTERRUPT {
|
||||
static tagMI_USER_INTERRUPT sInit(void) {
|
||||
MI_USER_INTERRUPT state;
|
||||
return state;
|
||||
}
|
||||
} MI_USER_INTERRUPT;
|
||||
|
||||
using WALKER_TYPE = GPGPU_WALKER;
|
||||
using MI_STORE_REGISTER_MEM_CMD = MI_STORE_REGISTER_MEM;
|
||||
static GPGPU_WALKER cmdInitGpgpuWalker;
|
||||
static INTERFACE_DESCRIPTOR_DATA cmdInitInterfaceDescriptorData;
|
||||
static MEDIA_STATE_FLUSH cmdInitMediaStateFlush;
|
||||
static MEDIA_INTERFACE_DESCRIPTOR_LOAD cmdInitMediaInterfaceDescriptorLoad;
|
||||
static MI_SEMAPHORE_WAIT cmdInitMiSemaphoreWait;
|
||||
static PIPE_CONTROL cmdInitPipeControl;
|
||||
static RENDER_SURFACE_STATE cmdInitRenderSurfaceState;
|
||||
static MI_LOAD_REGISTER_IMM cmdInitLoadRegisterImm;
|
||||
static MI_LOAD_REGISTER_REG cmdInitLoadRegisterReg;
|
||||
static MI_LOAD_REGISTER_MEM cmdInitLoadRegisterMem;
|
||||
static MI_STORE_DATA_IMM cmdInitStoreDataImm;
|
||||
static MI_STORE_REGISTER_MEM cmdInitStoreRegisterMem;
|
||||
static MI_NOOP cmdInitNoop;
|
||||
static MI_BATCH_BUFFER_START cmdInitBatchBufferStart;
|
||||
static MI_BATCH_BUFFER_END cmdInitBatchBufferEnd;
|
||||
static MI_REPORT_PERF_COUNT cmdInitReportPerfCount;
|
||||
static MI_ATOMIC cmdInitAtomic;
|
||||
static PIPELINE_SELECT cmdInitPipelineSelect;
|
||||
static MI_ARB_CHECK cmdInitArbCheck;
|
||||
static MEDIA_VFE_STATE cmdInitMediaVfeState;
|
||||
static STATE_BASE_ADDRESS cmdInitStateBaseAddress;
|
||||
static MEDIA_SURFACE_STATE cmdInitMediaSurfaceState;
|
||||
static SAMPLER_STATE cmdInitSamplerState;
|
||||
static GPGPU_CSR_BASE_ADDRESS cmdInitGpgpuCsrBaseAddress;
|
||||
static STATE_SIP cmdInitStateSip;
|
||||
static BINDING_TABLE_STATE cmdInitBindingTableState;
|
||||
static MI_USER_INTERRUPT cmdInitUserInterrupt;
|
||||
};
|
||||
|
||||
template <>
|
||||
struct AUBFamilyMapper<GENX> {
|
||||
static const AubMemDump::LrcaHelper *csTraits[aub_stream::NUM_ENGINES];
|
||||
static const MMIOList globalMMIO;
|
||||
static const MMIOList *perEngineMMIO[aub_stream::NUM_ENGINES];
|
||||
};
|
||||
|
||||
} // namespace NEO
|
||||
@@ -10,7 +10,6 @@
|
||||
#include "runtime/helpers/hw_helper.h"
|
||||
#include "runtime/helpers/options.h"
|
||||
#include "runtime/os_interface/linux/os_interface.h"
|
||||
#include "unit_tests/libult/mock_gfx_family.h"
|
||||
|
||||
#include <cstring>
|
||||
|
||||
@@ -98,8 +97,7 @@ struct HwInfoConfigTestLinuxDummy : HwInfoConfigTestLinux {
|
||||
|
||||
drm->StoredDeviceID = 1;
|
||||
drm->setGtType(GTTYPE_GT0);
|
||||
|
||||
testPlatform.eRenderCoreFamily = IGFX_UNKNOWN_CORE;
|
||||
testPlatform.eRenderCoreFamily = platformDevices[0]->pPlatform->eRenderCoreFamily;
|
||||
}
|
||||
|
||||
void TearDown() override {
|
||||
|
||||
@@ -10,7 +10,6 @@
|
||||
#include "runtime/os_interface/windows/os_interface.h"
|
||||
#include "runtime/os_interface/windows/wddm/wddm.h"
|
||||
#include "unit_tests/helpers/debug_manager_state_restore.h"
|
||||
#include "unit_tests/libult/mock_gfx_family.h"
|
||||
|
||||
namespace NEO {
|
||||
|
||||
|
||||
@@ -10,7 +10,6 @@
|
||||
#include "runtime/utilities/stackvec.h"
|
||||
#include "test.h"
|
||||
#include "unit_tests/helpers/hw_parse.h"
|
||||
#include "unit_tests/libult/mock_gfx_family.h"
|
||||
#include "unit_tests/mocks/mock_device.h"
|
||||
#include "unit_tests/mocks/mock_graphics_allocation.h"
|
||||
|
||||
@@ -189,17 +188,3 @@ HWTEST_F(PreambleTest, givenDefaultPreambleWhenGetThreadsMaxNumberIsCalledThenMa
|
||||
uint32_t expected = hwInfo.pSysInfo->EUCount * threadsPerEU;
|
||||
EXPECT_EQ(expected, value);
|
||||
}
|
||||
|
||||
TEST(DefaultPreambleHelperTest, givenDefaultPreambleHelperWhenGetAdditionalCommandsSizeThenZeroIsReturned) {
|
||||
auto size = PreambleHelper<GENX>::getAdditionalCommandsSize(MockDevice(**platformDevices));
|
||||
EXPECT_EQ(0u, size);
|
||||
}
|
||||
|
||||
TEST(DefaultPreambleHelperTest, givenDefaultPreambleHelperWhenProgramGenSpecificPreambleWorkAroundsThenDoNothing) {
|
||||
char preambleBuffer[4096];
|
||||
LinearStream preambleStream(preambleBuffer, 4096);
|
||||
size_t size = preambleStream.getUsed();
|
||||
|
||||
PreambleHelper<GENX>::programGenSpecificPreambleWorkArounds(&preambleStream, **platformDevices);
|
||||
EXPECT_EQ(size, preambleStream.getUsed());
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user