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refactor: move GPR15 to separate debugger context

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Signed-off-by: Jemale Lockett <jemale.lockett@intel.com>
This commit is contained in:
Jemale Lockett
2024-04-15 21:30:35 +00:00
committed by Compute-Runtime-Automation
parent da9df9f0e7
commit 79f8993220
7 changed files with 22 additions and 16 deletions
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12
shared/source/helpers/register_offsets.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2019-2023 Intel Corporation
* Copyright (C) 2019-2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -40,7 +40,6 @@ inline constexpr uint32_t csGprR11 = 0x2658;
inline constexpr uint32_t csGprR12 = 0x2660;
inline constexpr uint32_t csGprR13 = 0x2668;
inline constexpr uint32_t csGprR14 = 0x2670;
inline constexpr uint32_t csGprR15 = 0x2678;
inline constexpr uint32_t csPredicateResult = 0x2418;
inline constexpr uint32_t csPredicateResult2 = 0x23BC;
@@ -53,6 +52,10 @@ inline constexpr uint32_t globalTimestampLdw = 0x2358;
inline constexpr uint32_t globalTimestampUn = 0x235c;
} // namespace RegisterOffsets
namespace DebuggerRegisterOffsets {
inline constexpr uint32_t csGprR15 = 0x2678;
} // namespace DebuggerRegisterOffsets
// Alu opcodes
enum class AluRegisters : uint32_t {
opcodeNone = 0x000,
@@ -86,7 +89,6 @@ enum class AluRegisters : uint32_t {
gpr12 = 0xC,
gpr13 = 0xD,
gpr14 = 0xE,
gpr15 = 0xF,
srca = 0x20,
srcb = 0x21,
@@ -94,3 +96,7 @@ enum class AluRegisters : uint32_t {
zf = 0x32,
cf = 0x33
};
enum class DebuggerAluRegisters : uint32_t {
gpr15 = 0xF
};