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Rename core family names to meet naming convention

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Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
This commit is contained in:
Mateusz Jablonski
2022-07-25 15:30:11 +00:00
committed by Compute-Runtime-Automation
parent c200c6e2dd
commit 8424b27754
292 changed files with 673 additions and 673 deletions
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4
opencl/source/gen8/buffer_gen8.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2021 Intel Corporation
* Copyright (C) 2018-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -11,7 +11,7 @@
namespace NEO {
typedef BDWFamily Family;
typedef Gen8Family Family;
static auto gfxCore = IGFX_GEN8_CORE;
#include "opencl/source/mem_obj/buffer_factory_init.inl"

2
opencl/source/gen8/cl_hw_helper_gen8.cpp
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@@ -13,7 +13,7 @@
namespace NEO {
using Family = BDWFamily;
using Family = Gen8Family;
static auto gfxCore = IGFX_GEN8_CORE;
template <>

2
opencl/source/gen8/command_queue_gen8.cpp
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@@ -15,7 +15,7 @@
namespace NEO {
typedef BDWFamily Family;
typedef Gen8Family Family;
static auto gfxCore = IGFX_GEN8_CORE;
template class CommandQueueHw<Family>;

2
opencl/source/gen8/enable_family_full_ocl_gen8.cpp
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@@ -16,7 +16,7 @@
namespace NEO {
using Family = BDWFamily;
using Family = Gen8Family;
struct EnableOCLGen8 {
EnableOCLGen8() {

28
opencl/source/gen8/gpgpu_walker_gen8.cpp
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@@ -14,33 +14,33 @@
namespace NEO {
template <>
void GpgpuWalkerHelper<BDWFamily>::applyWADisableLSQCROPERFforOCL(NEO::LinearStream *pCommandStream, const Kernel &kernel, bool disablePerfMode) {
void GpgpuWalkerHelper<Gen8Family>::applyWADisableLSQCROPERFforOCL(NEO::LinearStream *pCommandStream, const Kernel &kernel, bool disablePerfMode) {
if (disablePerfMode) {
if (kernel.getKernelInfo().kernelDescriptor.kernelAttributes.flags.usesFencesForReadWriteImages) {
// Set bit L3SQC_BIT_LQSC_RO_PERF_DIS in L3SQC_REG4
GpgpuWalkerHelper<BDWFamily>::addAluReadModifyWriteRegister(pCommandStream, L3SQC_REG4, AluRegisters::OPCODE_OR, L3SQC_BIT_LQSC_RO_PERF_DIS);
GpgpuWalkerHelper<Gen8Family>::addAluReadModifyWriteRegister(pCommandStream, L3SQC_REG4, AluRegisters::OPCODE_OR, L3SQC_BIT_LQSC_RO_PERF_DIS);
}
} else {
if (kernel.getKernelInfo().kernelDescriptor.kernelAttributes.flags.usesFencesForReadWriteImages) {
// Add PIPE_CONTROL with CS_Stall to wait till GPU finishes its work
typedef typename BDWFamily::PIPE_CONTROL PIPE_CONTROL;
typedef typename Gen8Family::PIPE_CONTROL PIPE_CONTROL;
auto pipeControlSpace = reinterpret_cast<PIPE_CONTROL *>(pCommandStream->getSpace(sizeof(PIPE_CONTROL)));
auto pipeControl = BDWFamily::cmdInitPipeControl;
auto pipeControl = Gen8Family::cmdInitPipeControl;
pipeControl.setCommandStreamerStallEnable(true);
*pipeControlSpace = pipeControl;
// Clear bit L3SQC_BIT_LQSC_RO_PERF_DIS in L3SQC_REG4
GpgpuWalkerHelper<BDWFamily>::addAluReadModifyWriteRegister(pCommandStream, L3SQC_REG4, AluRegisters::OPCODE_AND, ~L3SQC_BIT_LQSC_RO_PERF_DIS);
GpgpuWalkerHelper<Gen8Family>::addAluReadModifyWriteRegister(pCommandStream, L3SQC_REG4, AluRegisters::OPCODE_AND, ~L3SQC_BIT_LQSC_RO_PERF_DIS);
}
}
}
template <>
size_t GpgpuWalkerHelper<BDWFamily>::getSizeForWADisableLSQCROPERFforOCL(const Kernel *pKernel) {
typedef typename BDWFamily::MI_LOAD_REGISTER_REG MI_LOAD_REGISTER_REG;
typedef typename BDWFamily::MI_LOAD_REGISTER_IMM MI_LOAD_REGISTER_IMM;
typedef typename BDWFamily::PIPE_CONTROL PIPE_CONTROL;
typedef typename BDWFamily::MI_MATH MI_MATH;
typedef typename BDWFamily::MI_MATH_ALU_INST_INLINE MI_MATH_ALU_INST_INLINE;
size_t GpgpuWalkerHelper<Gen8Family>::getSizeForWADisableLSQCROPERFforOCL(const Kernel *pKernel) {
typedef typename Gen8Family::MI_LOAD_REGISTER_REG MI_LOAD_REGISTER_REG;
typedef typename Gen8Family::MI_LOAD_REGISTER_IMM MI_LOAD_REGISTER_IMM;
typedef typename Gen8Family::PIPE_CONTROL PIPE_CONTROL;
typedef typename Gen8Family::MI_MATH MI_MATH;
typedef typename Gen8Family::MI_MATH_ALU_INST_INLINE MI_MATH_ALU_INST_INLINE;
size_t n = 0;
if (pKernel->getKernelInfo().kernelDescriptor.kernelAttributes.flags.usesFencesForReadWriteImages) {
n += sizeof(PIPE_CONTROL) +
@@ -54,10 +54,10 @@ size_t GpgpuWalkerHelper<BDWFamily>::getSizeForWADisableLSQCROPERFforOCL(const K
return n;
}
template class HardwareInterface<BDWFamily>;
template class HardwareInterface<Gen8Family>;
template class GpgpuWalkerHelper<BDWFamily>;
template class GpgpuWalkerHelper<Gen8Family>;
template struct EnqueueOperation<BDWFamily>;
template struct EnqueueOperation<Gen8Family>;
} // namespace NEO

2
opencl/source/gen8/gtpin_setup_gen8.cpp
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@@ -17,7 +17,7 @@ namespace NEO {
extern GTPinHwHelper *gtpinHwHelperFactory[IGFX_MAX_CORE];
typedef BDWFamily Family;
typedef Gen8Family Family;
static const auto gfxFamily = IGFX_GEN8_CORE;
template <>

4
opencl/source/gen8/hardware_commands_helper_gen8.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2019-2021 Intel Corporation
* Copyright (C) 2019-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -12,7 +12,7 @@
#include "opencl/source/helpers/hardware_commands_helper_bdw_and_later.inl"
namespace NEO {
using FamilyType = BDWFamily;
using FamilyType = Gen8Family;
template struct HardwareCommandsHelper<FamilyType>;
} // namespace NEO

4
opencl/source/gen8/image_gen8.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2021 Intel Corporation
* Copyright (C) 2018-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -13,7 +13,7 @@
namespace NEO {
using Family = BDWFamily;
using Family = Gen8Family;
static auto gfxCore = IGFX_GEN8_CORE;
template <>

4
opencl/source/gen8/sampler_gen8.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2021 Intel Corporation
* Copyright (C) 2018-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -12,7 +12,7 @@
namespace NEO {
typedef BDWFamily Family;
typedef Gen8Family Family;
static auto gfxCore = IGFX_GEN8_CORE;
#include "opencl/source/sampler/sampler_factory_init.inl"