Updated BaseSurfaceStateAddressAlignment to PageSize to handle Block R/W in L0

- Block R/W in kernels requires a minimum of 16B alignment/OWORD
alignment to properly work without data corruption.
- Level Zero currently writes Base Surface State addresses alignment to
4B vs OpenCL writes Base Surface State addresses aligned to PageSize for
4KB.
- Added a function in encode buffer to verify that at a minimum the size
being encoded has the minumum alignment of 4B which is supported, but
will not support Block R/W

Change-Id: I6486c2cbbb0008834c779bf54918388d79c193bb
Signed-off-by: Spruit, Neil R <neil.r.spruit@intel.com>

shared/source/command_container/command_encoder.h

@@ -205,7 +205,9 @@ struct EncodeSurfaceState {
         return ~(getSurfaceBaseAddressAlignment() - 1);
     }
 
-    static constexpr uintptr_t getSurfaceBaseAddressAlignment() { return 4; }
+    static constexpr uintptr_t getSurfaceBaseAddressMinimumAlignment() { return 4; }
+
+    static constexpr uintptr_t getSurfaceBaseAddressAlignment() { return MemoryConstants::pageSize; }
 
     static void getSshAlignedPointer(uintptr_t &ptr, size_t &offset);
     static bool doBindingTablePrefetch();

shared/source/command_container/command_encoder.inl

@@ -256,7 +256,7 @@ void EncodeSurfaceState<Family>::encodeBuffer(void *dst, uint64_t address, size_
                                               bool cpuCoherent, bool forceNonAuxMode, bool isReadOnly, uint32_t numAvailableDevices,
                                               GraphicsAllocation *allocation, GmmHelper *gmmHelper) {
     auto surfaceState = reinterpret_cast<R_SURFACE_STATE *>(dst);
-    UNRECOVERABLE_IF(!isAligned<getSurfaceBaseAddressAlignment()>(size));
+    UNRECOVERABLE_IF(!isAligned<getSurfaceBaseAddressMinimumAlignment()>(size));
 
     SURFACE_STATE_BUFFER_LENGTH Length = {0};
     Length.Length = static_cast<uint32_t>(size - 1);