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Debugger L0: expose FC register set

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Signed-off-by: Igor Venevtsev <igor.venevtsev@intel.com>
This commit is contained in:
Igor Venevtsev
2022-06-28 12:16:51 +00:00
committed by Compute-Runtime-Automation
parent bcdeeb22b5
commit 9e0138f5a7
5 changed files with 28 additions and 8 deletions
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1
level_zero/include/zet_intel_gpu_debug.h
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@@ -31,6 +31,7 @@ typedef enum _zet_debug_regset_type_intel_gpu_t {
ZET_DEBUG_REGSET_TYPE_SP_INTEL_GPU = 10, ///< The stack pointer register set
ZET_DEBUG_REGSET_TYPE_SBA_INTEL_GPU = 11, ///< The state base address register set
ZET_DEBUG_REGSET_TYPE_DBG_INTEL_GPU = 12, ///< The debug register set
ZET_DEBUG_REGSET_TYPE_FC_INTEL_GPU = 13, ///< The flow control register set
ZET_DEBUG_REGSET_TYPE_FORCE_UINT32 = 0x7fffffff
} zet_debug_regset_type_intel_gpu_t;

4
level_zero/tools/source/debug/debug_session_imp.cpp
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@@ -761,6 +761,8 @@ const SIP::regset_desc *DebugSessionImp::typeToRegsetDesc(uint32_t type) {
return &pStateSaveAreaHeader->regHeader.sp;
case ZET_DEBUG_REGSET_TYPE_DBG_INTEL_GPU:
return &pStateSaveAreaHeader->regHeader.dbg;
case ZET_DEBUG_REGSET_TYPE_FC_INTEL_GPU:
return &pStateSaveAreaHeader->regHeader.fc;
case ZET_DEBUG_REGSET_TYPE_SBA_INTEL_GPU:
return DebugSessionImp::getSbaRegsetDesc();
default:
@@ -786,6 +788,7 @@ uint32_t DebugSessionImp::typeToRegsetFlags(uint32_t type) {
case ZET_DEBUG_REGSET_TYPE_ACC_INTEL_GPU:
case ZET_DEBUG_REGSET_TYPE_SP_INTEL_GPU:
case ZET_DEBUG_REGSET_TYPE_DBG_INTEL_GPU:
case ZET_DEBUG_REGSET_TYPE_FC_INTEL_GPU:
return ZET_DEBUG_REGSET_FLAG_READABLE | ZET_DEBUG_REGSET_FLAG_WRITEABLE;
case ZET_DEBUG_REGSET_TYPE_CE_INTEL_GPU:
@@ -938,6 +941,7 @@ ze_result_t DebugSession::getRegisterSetProperties(Device *device, uint32_t *pCo
parseRegsetDesc(*DebugSessionImp::getSbaRegsetDesc(), ZET_DEBUG_REGSET_TYPE_SBA_INTEL_GPU);
parseRegsetDesc(pStateSaveArea->regHeader.dbg, ZET_DEBUG_REGSET_TYPE_DBG_INTEL_GPU);
parseRegsetDesc(pStateSaveArea->regHeader.fc, ZET_DEBUG_REGSET_TYPE_FC_INTEL_GPU);
if (!*pCount || (*pCount > totalRegsetNum)) {
*pCount = totalRegsetNum;

15
level_zero/tools/test/unit_tests/sources/debug/debug_session_tests.cpp
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@@ -1716,6 +1716,7 @@ TEST_F(DebugSessionRegistersAccessTest, givenTypeToRegsetDescCalledThenCorrectRe
EXPECT_EQ(session->typeToRegsetDesc(ZET_DEBUG_REGSET_TYPE_MME_INTEL_GPU), &pStateSaveAreaHeader->regHeader.mme);
EXPECT_EQ(session->typeToRegsetDesc(ZET_DEBUG_REGSET_TYPE_SP_INTEL_GPU), &pStateSaveAreaHeader->regHeader.sp);
EXPECT_EQ(session->typeToRegsetDesc(ZET_DEBUG_REGSET_TYPE_DBG_INTEL_GPU), &pStateSaveAreaHeader->regHeader.dbg);
EXPECT_EQ(session->typeToRegsetDesc(ZET_DEBUG_REGSET_TYPE_FC_INTEL_GPU), &pStateSaveAreaHeader->regHeader.fc);
EXPECT_NE(session->typeToRegsetDesc(ZET_DEBUG_REGSET_TYPE_SBA_INTEL_GPU), nullptr);
}
@@ -1756,6 +1757,20 @@ TEST_F(DebugSessionRegistersAccessTest, givenInvalidRegistersIndicesWheniWriteRe
EXPECT_EQ(ZE_RESULT_ERROR_INVALID_ARGUMENT, zetDebugWriteRegisters(session->toHandle(), {0, 0, 0, 0}, ZET_DEBUG_REGSET_TYPE_GRF_INTEL_GPU, 127, 2, nullptr));
}
TEST_F(DebugSessionRegistersAccessTest, givenNotReportedRegisterSetAndValidRegisterIndicesWhenReadRegistersCalledThenErrorInvalidArgumentIsReturned) {
session->areRequestedThreadsStoppedReturnValue = 1;
session->stateSaveAreaHeader = MockSipData::createStateSaveAreaHeader(2);
// MME is not present
EXPECT_EQ(ZE_RESULT_ERROR_INVALID_ARGUMENT, zetDebugReadRegisters(session->toHandle(), {0, 0, 0, 0}, ZET_DEBUG_REGSET_TYPE_MME_INTEL_GPU, 0, 1, nullptr));
}
TEST_F(DebugSessionRegistersAccessTest, givenNotReportedRegisterSetAndValidRegisterIndicesWhenWriteRegistersCalledThenErrorInvalidArgumentIsReturned) {
session->areRequestedThreadsStoppedReturnValue = 1;
session->stateSaveAreaHeader = MockSipData::createStateSaveAreaHeader(2);
// MME is not present
EXPECT_EQ(ZE_RESULT_ERROR_INVALID_ARGUMENT, zetDebugWriteRegisters(session->toHandle(), {0, 0, 0, 0}, ZET_DEBUG_REGSET_TYPE_MME_INTEL_GPU, 0, 1, nullptr));
}
TEST_F(DebugSessionRegistersAccessTest, givenInvalidSbaRegistersIndicesWhenReadSbaRegistersCalledThenErrorInvalidArgumentIsReturned) {
session->areRequestedThreadsStoppedReturnValue = 1;
session->stateSaveAreaHeader = MockSipData::createStateSaveAreaHeader(2);

10
level_zero/tools/test/unit_tests/sources/debug/test_debug_api.cpp
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@@ -206,14 +206,14 @@ TEST_F(DebugApiTest, givenNullCountPointerWhenGetRegisterSetPropertiesCalledThen
TEST_F(DebugApiTest, givenZeroCountWhenGetRegisterSetPropertiesCalledThenCorrectCountIsSet) {
uint32_t count = 0;
EXPECT_EQ(ZE_RESULT_SUCCESS, zetDebugGetRegisterSetProperties(device->toHandle(), &count, nullptr));
EXPECT_EQ(11u, count);
EXPECT_EQ(12u, count);
}
TEST_F(DebugApiTest, givenGetRegisterSetPropertiesCalledAndExtraSpaceIsProvidedThenCorrectPropertiesReturned) {
uint32_t count = 100;
std::vector<zet_debug_regset_properties_t> regsetProps(count);
EXPECT_EQ(ZE_RESULT_SUCCESS, zetDebugGetRegisterSetProperties(device->toHandle(), &count, regsetProps.data()));
EXPECT_EQ(11u, count);
EXPECT_EQ(12u, count);
}
TEST_F(DebugApiTest, givenNoStateSaveHeaderWhenGettingRegSetPropertiesThenZeroCountIsReturned) {
@@ -234,12 +234,12 @@ TEST_F(DebugApiTest, givenNonZeroCountAndNullRegsetPointerWhenGetRegisterSetProp
TEST_F(DebugApiTest, givenGetRegisterSetPropertiesCalledCorrectPropertiesReturned) {
uint32_t count = 0;
EXPECT_EQ(ZE_RESULT_SUCCESS, zetDebugGetRegisterSetProperties(device->toHandle(), &count, nullptr));
EXPECT_EQ(11u, count);
EXPECT_EQ(12u, count);
std::vector<zet_debug_regset_properties_t> regsetProps(count);
EXPECT_EQ(ZE_RESULT_SUCCESS, zetDebugGetRegisterSetProperties(device->toHandle(), &count, regsetProps.data()));
EXPECT_EQ(11u, count);
EXPECT_EQ(12u, count);
auto validateRegsetProps = [](const zet_debug_regset_properties_t &regsetProps,
zet_debug_regset_type_intel_gpu_t type, zet_debug_regset_flags_t flags,
@@ -265,8 +265,8 @@ TEST_F(DebugApiTest, givenGetRegisterSetPropertiesCalledCorrectPropertiesReturne
// MME is not present
validateRegsetProps(regsetProps[8], ZET_DEBUG_REGSET_TYPE_SP_INTEL_GPU, ZET_DEBUG_REGSET_FLAG_READABLE | ZET_DEBUG_REGSET_FLAG_WRITEABLE, 1, 128, 16);
validateRegsetProps(regsetProps[9], ZET_DEBUG_REGSET_TYPE_SBA_INTEL_GPU, ZET_DEBUG_REGSET_FLAG_READABLE, ZET_DEBUG_SBA_COUNT_INTEL_GPU, 64, 8);
// FC is not present
validateRegsetProps(regsetProps[10], ZET_DEBUG_REGSET_TYPE_DBG_INTEL_GPU, ZET_DEBUG_REGSET_FLAG_READABLE | ZET_DEBUG_REGSET_FLAG_WRITEABLE, 1, 32, 4);
validateRegsetProps(regsetProps[11], ZET_DEBUG_REGSET_TYPE_FC_INTEL_GPU, ZET_DEBUG_REGSET_FLAG_READABLE | ZET_DEBUG_REGSET_FLAG_WRITEABLE, 1, 32, 4);
}
TEST(DebugSessionTest, givenDebugSessionWhenConvertingToAndFromHandleCorrectHandleAndPointerIsReturned) {

6
shared/test/common/helpers/sip_init.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021 Intel Corporation
* Copyright (C) 2021-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -66,7 +66,7 @@ std::vector<char> createStateSaveAreaHeader(uint32_t version) {
{4704, 1, 128, 16}, // sp
{0, 0, 0, 0}, // cmd
{4640, 1, 128, 16}, // tm
{0, 0, 0, 0}, // fc
{0, 1, 32, 4}, // fc
{4736, 1, 32, 4}, // dbg
},
};
@@ -109,7 +109,7 @@ std::vector<char> createStateSaveAreaHeader(uint32_t version) {
{4704, 1, 128, 16}, // sp
{4768, 1, 128 * 8, 128}, // cmd
{4640, 1, 128, 16}, // tm
{0, 0, 0, 0}, // fc
{0, 1, 32, 4}, // fc
{4736, 1, 32, 4}, // dbg
},
};