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feature: Prepare hw info to report CXL type

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Related-To: NEO-11362

Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@intel.com>
This commit is contained in:
Aravind Gopalakrishnan
2024-05-24 01:12:14 +00:00
committed by Compute-Runtime-Automation
parent 4489aedf44
commit b39e99a17a
26 changed files with 88 additions and 44 deletions
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5
shared/source/gen11/hw_info_ehl.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2019-2023 Intel Corporation
* Copyright (C) 2019-2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -77,7 +77,8 @@ const RuntimeCapabilityTable EHL::capabilityTable{
false, // p2pAtomicAccessSupported
false, // fusedEuEnabled
false, // l0DebuggerSupported;
false // supportsFloatAtomics
false, // supportsFloatAtomics
0 // cxlType
};
WorkaroundTable EHL::workaroundTable = {};

5
shared/source/gen11/hw_info_icllp.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2019-2023 Intel Corporation
* Copyright (C) 2019-2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -77,7 +77,8 @@ const RuntimeCapabilityTable ICLLP::capabilityTable{
false, // p2pAtomicAccessSupported
false, // fusedEuEnabled
false, // l0DebuggerSupported;
false // supportsFloatAtomics
false, // supportsFloatAtomics
0 // cxlType
};
WorkaroundTable ICLLP::workaroundTable = {};

5
shared/source/gen11/hw_info_lkf.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2019-2023 Intel Corporation
* Copyright (C) 2019-2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -77,7 +77,8 @@ const RuntimeCapabilityTable LKF::capabilityTable{
false, // p2pAtomicAccessSupported
false, // fusedEuEnabled
false, // l0DebuggerSupported;
false // supportsFloatAtomics
false, // supportsFloatAtomics
0 // cxlType
};
WorkaroundTable LKF::workaroundTable = {};

5
shared/source/gen12lp/hw_info_adln.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2022-2023 Intel Corporation
* Copyright (C) 2022-2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -80,7 +80,8 @@ const RuntimeCapabilityTable ADLN::capabilityTable{
false, // p2pAtomicAccessSupported
true, // fusedEuEnabled
false, // l0DebuggerSupported;
true // supportsFloatAtomics
true, // supportsFloatAtomics
0 // cxlType
};
WorkaroundTable ADLN::workaroundTable = {};

5
shared/source/gen12lp/hw_info_adlp.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021-2023 Intel Corporation
* Copyright (C) 2021-2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -80,7 +80,8 @@ const RuntimeCapabilityTable ADLP::capabilityTable{
false, // p2pAtomicAccessSupported
true, // fusedEuEnabled
false, // l0DebuggerSupported;
true // supportsFloatAtomics
true, // supportsFloatAtomics
0 // cxlType
};
WorkaroundTable ADLP::workaroundTable = {};

5
shared/source/gen12lp/hw_info_adls.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2020-2023 Intel Corporation
* Copyright (C) 2020-2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -80,7 +80,8 @@ const RuntimeCapabilityTable ADLS::capabilityTable{
false, // p2pAtomicAccessSupported
true, // fusedEuEnabled
false, // l0DebuggerSupported;
true // supportsFloatAtomics
true, // supportsFloatAtomics
0 // cxlType
};
WorkaroundTable ADLS::workaroundTable = {};

5
shared/source/gen12lp/hw_info_dg1.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2020-2023 Intel Corporation
* Copyright (C) 2020-2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -80,7 +80,8 @@ const RuntimeCapabilityTable DG1::capabilityTable{
false, // p2pAtomicAccessSupported
true, // fusedEuEnabled
true, // l0DebuggerSupported;
true // supportsFloatAtomics
true, // supportsFloatAtomics
0 // cxlType
};
WorkaroundTable DG1::workaroundTable = {};

5
shared/source/gen12lp/hw_info_rkl.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2020-2023 Intel Corporation
* Copyright (C) 2020-2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -80,7 +80,8 @@ const RuntimeCapabilityTable RKL::capabilityTable{
false, // p2pAtomicAccessSupported
true, // fusedEuEnabled
false, // l0DebuggerSupported;
true // supportsFloatAtomics
true, // supportsFloatAtomics
0 // cxlType
};
WorkaroundTable RKL::workaroundTable = {};

5
shared/source/gen12lp/hw_info_tgllp.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2019-2023 Intel Corporation
* Copyright (C) 2019-2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -80,7 +80,8 @@ const RuntimeCapabilityTable TGLLP::capabilityTable{
false, // p2pAtomicAccessSupported
true, // fusedEuEnabled
false, // l0DebuggerSupported;
true // supportsFloatAtomics
true, // supportsFloatAtomics
0 // cxlType
};
WorkaroundTable TGLLP::workaroundTable = {};

5
shared/source/gen8/hw_info_bdw.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2023 Intel Corporation
* Copyright (C) 2018-2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -77,7 +77,8 @@ const RuntimeCapabilityTable BDW::capabilityTable{
false, // p2pAtomicAccessSupported
false, // fusedEuEnabled
false, // l0DebuggerSupported;
false // supportsFloatAtomics
false, // supportsFloatAtomics
0 // cxlType
};
WorkaroundTable BDW::workaroundTable = {};

5
shared/source/gen9/hw_info_bxt.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2023 Intel Corporation
* Copyright (C) 2018-2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -77,7 +77,8 @@ const RuntimeCapabilityTable BXT::capabilityTable{
false, // p2pAtomicAccessSupported
false, // fusedEuEnabled
false, // l0DebuggerSupported;
false // supportsFloatAtomics
false, // supportsFloatAtomics
0 // cxlType
};
WorkaroundTable BXT::workaroundTable = {};

5
shared/source/gen9/hw_info_cfl.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2023 Intel Corporation
* Copyright (C) 2018-2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -78,7 +78,8 @@ const RuntimeCapabilityTable CFL::capabilityTable{
false, // p2pAtomicAccessSupported
false, // fusedEuEnabled
false, // l0DebuggerSupported;
false // supportsFloatAtomics
false, // supportsFloatAtomics
0 // cxlType
};
WorkaroundTable CFL::workaroundTable = {};

5
shared/source/gen9/hw_info_glk.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2023 Intel Corporation
* Copyright (C) 2018-2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -77,7 +77,8 @@ const RuntimeCapabilityTable GLK::capabilityTable{
false, // p2pAtomicAccessSupported
false, // fusedEuEnabled
false, // l0DebuggerSupported;
false // supportsFloatAtomics
false, // supportsFloatAtomics
0 // cxlType
};
WorkaroundTable GLK::workaroundTable = {};

5
shared/source/gen9/hw_info_kbl.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2023 Intel Corporation
* Copyright (C) 2018-2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -78,7 +78,8 @@ const RuntimeCapabilityTable KBL::capabilityTable{
false, // p2pAtomicAccessSupported
false, // fusedEuEnabled
false, // l0DebuggerSupported;
false // supportsFloatAtomics
false, // supportsFloatAtomics
0 // cxlType
};
WorkaroundTable KBL::workaroundTable = {};

5
shared/source/gen9/hw_info_skl.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2023 Intel Corporation
* Copyright (C) 2018-2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -77,7 +77,8 @@ const RuntimeCapabilityTable SKL::capabilityTable{
false, // p2pAtomicAccessSupported
false, // fusedEuEnabled
false, // l0DebuggerSupported;
false // supportsFloatAtomics
false, // supportsFloatAtomics
0 // cxlType
};
WorkaroundTable SKL::workaroundTable = {};

3
shared/source/helpers/hw_info.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2023 Intel Corporation
* Copyright (C) 2018-2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -68,6 +68,7 @@ struct RuntimeCapabilityTable {
bool fusedEuEnabled;
bool l0DebuggerSupported;
bool supportsFloatAtomics;
uint32_t cxlType;
};
inline bool operator==(const RuntimeCapabilityTable &lhs, const RuntimeCapabilityTable &rhs) {

5
shared/source/xe_hpc_core/hw_info_pvc.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021-2023 Intel Corporation
* Copyright (C) 2021-2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -93,7 +93,8 @@ const RuntimeCapabilityTable PVC::capabilityTable{
true, // p2pAtomicAccessSupported
false, // fusedEuEnabled
true, // l0DebuggerSupported;
true // supportsFloatAtomics
true, // supportsFloatAtomics
0 // cxlType
};
void PVC::setupFeatureAndWorkaroundTable(HardwareInfo *hwInfo) {

5
shared/source/xe_hpg_core/hw_info_arl.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2023 Intel Corporation
* Copyright (C) 2023-2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -78,7 +78,8 @@ const RuntimeCapabilityTable ARL::capabilityTable{
false, // p2pAtomicAccessSupported
true, // fusedEuEnabled
false, // l0DebuggerSupported
true // supportsFloatAtomics
true, // supportsFloatAtomics
0 // cxlType
};
WorkaroundTable ARL::workaroundTable = {};

3
shared/source/xe_hpg_core/hw_info_dg2.cpp
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@@ -83,7 +83,8 @@ const RuntimeCapabilityTable DG2::capabilityTable{
false, // p2pAtomicAccessSupported
true, // fusedEuEnabled
true, // l0DebuggerSupported
true // supportsFloatAtomics
true, // supportsFloatAtomics
0 // cxlType
};
WorkaroundTable DG2::workaroundTable = {};

5
shared/source/xe_hpg_core/hw_info_mtl.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2022-2023 Intel Corporation
* Copyright (C) 2022-2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -79,7 +79,8 @@ const RuntimeCapabilityTable MTL::capabilityTable{
false, // p2pAtomicAccessSupported
true, // fusedEuEnabled
true, // l0DebuggerSupported
true // supportsFloatAtomics
true, // supportsFloatAtomics
0 // cxlType
};
WorkaroundTable MTL::workaroundTable = {};