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Program L3 error detection behavior.

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Change-Id: Ifeccb707376f5b267de58ffd6ad009cf000c5047
This commit is contained in:
Zdunowski, Piotr
2019-02-18 13:43:10 +01:00
committed by sys_ocldev
parent 4ac2c079dc
commit d99e833786
6 changed files with 52 additions and 38 deletions
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6
runtime/gen10/reg_configs.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2018 Intel Corporation
* Copyright (C) 2017-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -13,8 +13,8 @@ namespace OCLRT {
struct CNLFamily;
template <>
struct L3CNTLREGConfig<IGFX_CANNONLAKE> {
static const uint32_t valueForSLM = 0xA0000121u;
static const uint32_t valueForNoSLM = 0xc0000140u;
static const uint32_t valueForSLM = 0xA0000321u;
static const uint32_t valueForNoSLM = 0xc0000340u;
};
template <>

6
runtime/gen8/reg_configs.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2018 Intel Corporation
* Copyright (C) 2017-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -13,8 +13,8 @@ namespace OCLRT {
struct BDWFamily;
template <>
struct L3CNTLREGConfig<IGFX_BROADWELL> {
static const uint32_t valueForSLM = 0x60000121u;
static const uint32_t valueForNoSLM = 0x80000140u;
static const uint32_t valueForSLM = 0x60000321u;
static const uint32_t valueForNoSLM = 0x80000340u;
};
template <>

27
runtime/gen9/reg_configs.h
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@@ -1,23 +1,8 @@
/*
* Copyright (c) 2017, Intel Corporation
* Copyright (C) 2018-2019 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
* SPDX-License-Identifier: MIT
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#pragma once
@@ -28,8 +13,8 @@ namespace OCLRT {
struct SKLFamily;
template <>
struct L3CNTLREGConfig<IGFX_SKYLAKE> {
static const uint32_t valueForSLM = 0x60000121u;
static const uint32_t valueForNoSLM = 0x80000140u;
static const uint32_t valueForSLM = 0x60000321u;
static const uint32_t valueForNoSLM = 0x80000340u;
};
template <>
@@ -39,8 +24,8 @@ struct L3CNTLRegisterOffset<SKLFamily> {
template <>
struct L3CNTLREGConfig<IGFX_BROXTON> {
static const uint32_t valueForSLM = 0x60000121u;
static const uint32_t valueForNoSLM = 0x80000140u;
static const uint32_t valueForSLM = 0x60000321u;
static const uint32_t valueForNoSLM = 0x80000340u;
};
namespace DebugControlReg2 {

19
unit_tests/gen10/test_preamble_gen10.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2018 Intel Corporation
* Copyright (C) 2017-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -112,8 +112,8 @@ CNLTEST_F(Gen10PreambleVfeState, WaOn) {
TEST(L3CNTLREGConfig, checkValidValues) {
uint32_t validCNLNoSLMConfigs[] = {0x80000180, 0x00418180, 0x00420160, 0x00030140, 0xc0000140, 0x00428140};
uint32_t validCNLSLMConfigs[] = {0, 0xa0000121, 0x01008121, 0xc0000101};
uint32_t validCNLNoSLMConfigs[] = {0x80000180, 0x00418180, 0x00420160, 0x00030140, 0xc0000340, 0x00428140};
uint32_t validCNLSLMConfigs[] = {0, 0xa0000321, 0x01008121, 0xc0000101};
bool noSLMConfigValid = false;
bool SLMConfigValid = false;
@@ -136,6 +136,19 @@ TEST(L3CNTLREGConfig, checkValidValues) {
EXPECT_TRUE(noSLMConfigValid);
}
typedef PreambleFixture L3ErrorDetectionBit;
GEN10TEST_F(L3ErrorDetectionBit, GivenGen10WhenProgrammingL3ThenErrorDetectionBehaviorControlBitSet) {
uint32_t l3Config = 0;
l3Config = getL3ConfigHelper<IGFX_CANNONLAKE>(true);
uint32_t errorDetectionBehaviorControlBit = 1 << 9;
EXPECT_TRUE((l3Config & errorDetectionBehaviorControlBit) != 0);
l3Config = getL3ConfigHelper<IGFX_CANNONLAKE>(false);
EXPECT_TRUE((l3Config & errorDetectionBehaviorControlBit) != 0);
}
typedef PreambleFixture PreemptionWatermarkGen10;
GEN10TEST_F(PreemptionWatermarkGen10, givenPreambleThenPreambleWorkAroundsIsNotProgrammed) {
typedef CNLFamily::MI_LOAD_REGISTER_IMM MI_LOAD_REGISTER_IMM;

12
unit_tests/gen8/test_preamble_gen8.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018 Intel Corporation
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -40,7 +40,10 @@ BDWTEST_F(Gen8L3Config, checkNoSLM) {
uint32_t l3Config = 0;
l3Config = getL3ConfigHelper<IGFX_BROADWELL>(slmUsed);
EXPECT_EQ(0x80000140u, l3Config);
EXPECT_EQ(0x80000340u, l3Config);
uint32_t errorDetectionBehaviorControlBit = 1 << 9;
EXPECT_TRUE((l3Config & errorDetectionBehaviorControlBit) != 0);
}
BDWTEST_F(Gen8L3Config, checkSLM) {
@@ -48,7 +51,10 @@ BDWTEST_F(Gen8L3Config, checkSLM) {
uint32_t l3Config = 0;
l3Config = getL3ConfigHelper<IGFX_BROADWELL>(slmUsed);
EXPECT_EQ(0x60000121u, l3Config);
EXPECT_EQ(0x60000321u, l3Config);
uint32_t errorDetectionBehaviorControlBit = 1 << 9;
EXPECT_TRUE((l3Config & errorDetectionBehaviorControlBit) != 0);
}
typedef PreambleFixture ThreadArbitrationGen8;

20
unit_tests/gen9/skl/test_preamble_skl.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018 Intel Corporation
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -42,10 +42,15 @@ SKLTEST_F(Gen9L3Config, checkNoSLM) {
uint32_t l3Config = 0;
l3Config = getL3ConfigHelper<IGFX_SKYLAKE>(slmUsed);
EXPECT_EQ(0x80000140u, l3Config);
EXPECT_EQ(0x80000340u, l3Config);
uint32_t errorDetectionBehaviorControlBit = 1 << 9;
EXPECT_TRUE((l3Config & errorDetectionBehaviorControlBit) != 0);
l3Config = getL3ConfigHelper<IGFX_BROXTON>(slmUsed);
EXPECT_EQ(0x80000140u, l3Config);
EXPECT_EQ(0x80000340u, l3Config);
EXPECT_TRUE((l3Config & errorDetectionBehaviorControlBit) != 0);
}
SKLTEST_F(Gen9L3Config, checkSLM) {
@@ -53,10 +58,15 @@ SKLTEST_F(Gen9L3Config, checkSLM) {
uint32_t l3Config = 0;
l3Config = getL3ConfigHelper<IGFX_SKYLAKE>(slmUsed);
EXPECT_EQ(0x60000121u, l3Config);
EXPECT_EQ(0x60000321u, l3Config);
uint32_t errorDetectionBehaviorControlBit = 1 << 9;
EXPECT_TRUE((l3Config & errorDetectionBehaviorControlBit) != 0);
l3Config = getL3ConfigHelper<IGFX_BROXTON>(slmUsed);
EXPECT_EQ(0x60000121u, l3Config);
EXPECT_EQ(0x60000321u, l3Config);
EXPECT_TRUE((l3Config & errorDetectionBehaviorControlBit) != 0);
}
typedef PreambleFixture ThreadArbitration;