Initial PVC support

Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>

Related-To: NEO-5542

level_zero/core/source/hw_helpers/l0_hw_helper_pvc_and_later.inl

@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "shared/source/debug_settings/debug_settings_manager.h"
+#include "shared/source/helpers/engine_node_helper.h"
+
+#include "level_zero/core/source/hw_helpers/l0_hw_helper.h"
+
+#include "engine_group_types.h"
+
+#include <limits>
+
+namespace L0 {
+
+template <typename Family>
+void L0HwHelperHw<Family>::setAdditionalGroupProperty(ze_command_queue_group_properties_t &groupProperty, NEO::EngineGroupType groupType) const {
+    if (groupType == NEO::EngineGroupType::LinkedCopy) {
+        groupProperty.flags = ZE_COMMAND_QUEUE_GROUP_PROPERTY_FLAG_COPY;
+        groupProperty.maxMemoryFillPatternSize = sizeof(uint8_t);
+    }
+
+    if (groupType == NEO::EngineGroupType::Copy && NEO::EngineHelpers::isBcsVirtualEngineEnabled()) {
+        groupProperty.flags = ZE_COMMAND_QUEUE_GROUP_PROPERTY_FLAG_COPY;
+        groupProperty.maxMemoryFillPatternSize = sizeof(uint8_t);
+    }
+}
+
+} // namespace L0

level_zero/core/source/xe_hpc_core/CMakeLists.txt

@@ -0,0 +1,19 @@
+#
+# Copyright (C) 2021 Intel Corporation
+#
+# SPDX-License-Identifier: MIT
+#
+
+if(SUPPORT_XE_HPC_CORE)
+  set(HW_SOURCES_XE_HPC_CORE
+      ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
+      ${CMAKE_CURRENT_SOURCE_DIR}/cmdlist_xe_hpc_core.inl
+      ${CMAKE_CURRENT_SOURCE_DIR}/debugger_xe_hpc_core.cpp
+      ${CMAKE_CURRENT_SOURCE_DIR}/enable_family_full_l0_xe_hpc_core.cpp
+      ${CMAKE_CURRENT_SOURCE_DIR}/l0_hw_helper_xe_hpc_core.cpp
+  )
+
+  add_subdirectories()
+
+  target_sources(${L0_STATIC_LIB_NAME} PRIVATE ${HW_SOURCES_XE_HPC_CORE})
+endif()

level_zero/core/source/xe_hpc_core/cmdlist_xe_hpc_core.inl

@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "level_zero/core/source/cmdlist/cmdlist_hw.h"
+
+namespace L0 {
+
+template <>
+NEO::PipeControlArgs CommandListCoreFamily<IGFX_XE_HPC_CORE>::createBarrierFlags() {
+    NEO::PipeControlArgs args;
+    args.hdcPipelineFlush = true;
+    args.unTypedDataPortCacheFlush = true;
+    return args;
+}
+
+template <>
+ze_result_t CommandListCoreFamily<IGFX_XE_HPC_CORE>::appendMemoryPrefetch(const void *ptr, size_t size) {
+    using MI_BATCH_BUFFER_END = GfxFamily::MI_BATCH_BUFFER_END;
+    auto allocData = device->getDriverHandle()->getSvmAllocsManager()->getSVMAlloc(ptr);
+
+    if (!allocData) {
+        return ZE_RESULT_ERROR_INVALID_ARGUMENT;
+    }
+
+    if (NEO::DebugManager.flags.AddStatePrefetchCmdToMemoryPrefetchAPI.get() != 1) {
+        return ZE_RESULT_SUCCESS;
+    }
+
+    auto gpuAlloc = allocData->gpuAllocations.getGraphicsAllocation(device->getRootDeviceIndex());
+    auto &hwInfo = device->getHwInfo();
+
+    commandContainer.addToResidencyContainer(gpuAlloc);
+
+    size_t offset = ptrDiff(ptr, gpuAlloc->getGpuAddress());
+
+    NEO::LinearStream &cmdStream = *commandContainer.getCommandStream();
+
+    size_t estimatedSizeRequired = NEO::EncodeMemoryPrefetch<GfxFamily>::getSizeForMemoryPrefetch(size);
+    increaseCommandStreamSpace(estimatedSizeRequired);
+
+    NEO::EncodeMemoryPrefetch<GfxFamily>::programMemoryPrefetch(cmdStream, *gpuAlloc, static_cast<uint32_t>(size), offset, hwInfo);
+
+    return ZE_RESULT_SUCCESS;
+}
+} // namespace L0

level_zero/core/source/xe_hpc_core/debugger_xe_hpc_core.cpp

@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "level_zero/core/source/debugger/debugger_l0.inl"
+
+namespace NEO {
+struct XE_HPC_COREFamily;
+using GfxFamily = XE_HPC_COREFamily;
+
+} // namespace NEO
+
+namespace L0 {
+template class DebuggerL0Hw<NEO::GfxFamily>;
+DebuggerL0PopulateFactory<IGFX_XE_HPC_CORE, NEO::GfxFamily> debuggerXeHpcCore;
+} // namespace L0

level_zero/core/source/xe_hpc_core/enable_family_full_l0_xe_hpc_core.cpp

@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "shared/source/command_stream/aub_command_stream_receiver_hw.h"
+#include "shared/source/command_stream/command_stream_receiver_hw.h"
+#include "shared/source/command_stream/tbx_command_stream_receiver_hw.h"
+#include "shared/source/helpers/populate_factory.h"
+
+#include "level_zero/core/source/helpers/l0_populate_factory.h"
+#include "level_zero/core/source/hw_helpers/l0_hw_helper.h"
+
+namespace NEO {
+
+using Family = XE_HPC_COREFamily;
+
+struct EnableL0XeHpcCore {
+    EnableL0XeHpcCore() {
+        populateFactoryTable<AUBCommandStreamReceiverHw<Family>>();
+        populateFactoryTable<TbxCommandStreamReceiverHw<Family>>();
+        populateFactoryTable<CommandStreamReceiverHw<Family>>();
+        L0::populateFactoryTable<L0::L0HwHelperHw<Family>>();
+    }
+};
+
+static EnableL0XeHpcCore enable;
+} // namespace NEO

level_zero/core/source/xe_hpc_core/image_xe_hpc_core.inl

@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "shared/source/xe_hpc_core/hw_cmds.h"
+#include "shared/source/xe_hpc_core/hw_info.h"
+
+#include "level_zero/core/source/image/image_hw.inl"

level_zero/core/source/xe_hpc_core/l0_hw_helper_xe_hpc_core.cpp

@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "level_zero/core/source/helpers/l0_populate_factory.h"
+#include "level_zero/core/source/hw_helpers/l0_hw_helper_base.inl"
+#include "level_zero/core/source/hw_helpers/l0_hw_helper_pvc_and_later.inl"
+
+#include "hw_cmds.h"
+
+namespace L0 {
+
+using Family = NEO::XE_HPC_COREFamily;
+static auto gfxCore = IGFX_XE_HPC_CORE;
+
+template <>
+void populateFactoryTable<L0HwHelperHw<Family>>() {
+    extern L0HwHelper *l0HwHelperFactory[IGFX_MAX_CORE];
+    l0HwHelperFactory[gfxCore] = &L0HwHelperHw<Family>::get();
+}
+
+template class L0HwHelperHw<Family>;
+
+} // namespace L0

level_zero/core/source/xe_hpc_core/pvc/CMakeLists.txt

@@ -0,0 +1,17 @@
+#
+# Copyright (C) 2021 Intel Corporation
+#
+# SPDX-License-Identifier: MIT
+#
+
+if(SUPPORT_PVC)
+  set(HW_SOURCES_XE_HPC_CORE
+      ${HW_SOURCES_XE_HPC_CORE}
+      ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
+      ${CMAKE_CURRENT_SOURCE_DIR}/image_pvc.cpp
+      ${CMAKE_CURRENT_SOURCE_DIR}/cmdlist_pvc.cpp
+      ${CMAKE_CURRENT_SOURCE_DIR}/cmdqueue_pvc.cpp
+      ${CMAKE_CURRENT_SOURCE_DIR}/kernel_pvc.cpp
+      PARENT_SCOPE
+  )
+endif()

level_zero/core/source/xe_hpc_core/pvc/cmdlist_pvc.cpp

@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "level_zero/core/source/cmdlist/cmdlist_hw.inl"
+#include "level_zero/core/source/cmdlist/cmdlist_hw_immediate.inl"
+#include "level_zero/core/source/cmdlist/cmdlist_hw_xehp_and_later.inl"
+#include "level_zero/core/source/xe_hpc_core/cmdlist_xe_hpc_core.inl"
+
+#include "cmdlist_extended.inl"
+
+namespace L0 {
+template <>
+void CommandListCoreFamily<IGFX_XE_HPC_CORE>::applyMemoryRangesBarrier(uint32_t numRanges,
+                                                                       const size_t *pRangeSizes,
+                                                                       const void **pRanges) {
+
+    increaseCommandStreamSpace(NEO::MemorySynchronizationCommands<GfxFamily>::getSizeForSinglePipeControl());
+
+    NEO::PipeControlArgs args = {};
+    args.hdcPipelineFlush = true;
+    args.unTypedDataPortCacheFlush = true;
+    NEO::MemorySynchronizationCommands<GfxFamily>::addPipeControl(*commandContainer.getCommandStream(), args);
+}
+
+template struct CommandListCoreFamily<IGFX_XE_HPC_CORE>;
+
+template <>
+struct CommandListProductFamily<IGFX_PVC> : public CommandListCoreFamily<IGFX_XE_HPC_CORE> {
+    using CommandListCoreFamily::CommandListCoreFamily;
+};
+
+static CommandListPopulateFactory<IGFX_PVC, CommandListProductFamily<IGFX_PVC>>
+    populatePVC;
+
+template <>
+struct CommandListImmediateProductFamily<IGFX_PVC> : public CommandListCoreFamilyImmediate<IGFX_XE_HPC_CORE> {
+    using CommandListCoreFamilyImmediate::CommandListCoreFamilyImmediate;
+};
+
+static CommandListImmediatePopulateFactory<IGFX_PVC, CommandListImmediateProductFamily<IGFX_PVC>>
+    populatePVCImmediate;
+} // namespace L0

level_zero/core/source/xe_hpc_core/pvc/cmdqueue_pvc.cpp

@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "shared/source/xe_hpc_core/hw_cmds.h"
+#include "shared/source/xe_hpc_core/hw_info.h"
+
+#include "level_zero/core/source/cmdqueue/cmdqueue_hw.inl"
+#include "level_zero/core/source/cmdqueue/cmdqueue_xe_hp_core_and_later.inl"
+
+#include "cmdqueue_extended.inl"
+namespace L0 {
+template struct CommandQueueHw<IGFX_XE_HPC_CORE>;
+static CommandQueuePopulateFactory<IGFX_PVC, CommandQueueHw<IGFX_XE_HPC_CORE>>
+    populatePVC;
+
+} // namespace L0

level_zero/core/source/xe_hpc_core/pvc/image_pvc.cpp

@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "level_zero/core/source/xe_hpc_core/image_xe_hpc_core.inl"
+
+namespace L0 {
+
+template <>
+struct ImageProductFamily<IGFX_PVC> : public ImageCoreFamily<IGFX_XE_HPC_CORE> {
+    using ImageCoreFamily::ImageCoreFamily;
+
+    ze_result_t initialize(Device *device, const ze_image_desc_t *desc) override {
+        return ImageCoreFamily<IGFX_XE_HPC_CORE>::initialize(device, desc);
+    };
+};
+
+static ImagePopulateFactory<IGFX_PVC, ImageProductFamily<IGFX_PVC>> populatePVC;
+
+} // namespace L0

level_zero/core/source/xe_hpc_core/pvc/kernel_pvc.cpp

@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "level_zero/core/source/kernel/kernel_hw.h"
+
+namespace L0 {
+
+static KernelPopulateFactory<IGFX_PVC, KernelHw<IGFX_XE_HPC_CORE>> populatePVC;
+
+} // namespace L0