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76 Commits

Author SHA1 Message Date
Katarzyna Cencelewska
dd63f1d2f9 Add new function append3dStateBtd 
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
 2022-02-03 14:42:10 +01:00
Maciej Plewka
9d8ce7aace Command container appends BB_END on cmd buffer allocation end 
When linear stream created for command container has not enough space
for command and BB_END it will program BB_END and allocate new command
buffer allocation. Pointer returned from getSpace in this case will
return storage from new command buffer allocation.

Related-To: NEO-5707

Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2022-01-31 16:15:37 +01:00
Maciej Plewka
f8c104feaa Use fw declaration of IndirectHeap in CommandContainer 
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2022-01-26 13:30:26 +01:00
Mateusz Jablonski
5e238dc7f1 Unify surface state programming logic related to implicit scaling 
OCL image surface state programming for Xe Hp core is now reusing logic
of EncodeSurfaceState helper

Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2022-01-25 09:02:28 +01:00
Mateusz Jablonski
5cd76aef6a Refactor surface state programming, add enum value for default halign value 
Related-To: NEO-6466
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2022-01-19 14:31:28 +01:00
Filip Hazubski
9a450d1b74 Pass hwInfo to appendMiFlushDw 
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2021-12-22 15:22:47 +01:00
Mateusz Jablonski
66bf806018 Remove magic number from set/getBatchBufferStartAddressGraphicsaddress methods 
rename methods to set/getBatchBufferStartAddress

Related-To: NEO-6466
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2021-12-16 19:03:01 +01:00
Zbigniew Zdanowicz
47dbe359bf Add command encoder for store data command 
Related-To: NEO-6262

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2021-12-02 20:56:07 +01:00
Bartosz Dunajski
55959d4d1d Helper method to check if allocation is compressed 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2021-12-02 16:13:53 +01:00
Zbigniew Zdanowicz
76b8f6296f Move noop programming to dedicated encoder 
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2021-11-18 10:28:56 +01:00
Zbigniew Zdanowicz
9d56939980 Refactor creation of buffer surface state 1/n 
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2021-10-21 13:11:31 +02:00
Mateusz Jablonski
5d2d81b2d1 Use uint64_t instead of void * in indirect dispatch programming 
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2021-10-06 18:37:36 +02:00
Mateusz Jablonski
92bf4b978a Implement implicit args for indirect dispatch 
Related-To: NEO-5081
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2021-10-06 16:10:41 +02:00
Mateusz Jablonski
ae340ff6f5 Add L0 aub tests for indirect dispatch 
Related-To: NEO-5081
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2021-10-05 21:05:40 +02:00
Mateusz Jablonski
b891ec2588 Correct cross thread data GPU address in indirect dispatch programming 
Related-To: NEO-5081
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2021-10-04 14:59:41 +02:00
Zbigniew Zdanowicz
6b299a3ab0 Make partitioned post sync operations for partitioned workloads 
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2021-09-03 20:20:29 +02:00
Bartosz Dunajski
856dee2b08 Improve Sampler programming 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2021-08-25 19:47:30 +02:00
Lukasz Jobczyk
dbf9198186 Flush tlb on BCS direct submission 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2021-07-30 16:26:47 +02:00
Dominik Dabek
62f89b174a Add work_dim patching to l0 kernel 
Related-To: NEO-5931

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
 2021-07-05 20:09:20 +02:00
Mateusz Jablonski
72d124e275 add function to append params for image from buffer 
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2021-06-24 13:33:43 +02:00
Zbigniew Zdanowicz
0e5ca243e2 Add notify enable parameter to post sync commands 
Related-To: NEO-5845

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2021-06-17 19:22:51 +02:00
Szymon Morek
3ed0f074af Add method to set compression flag 
Signed-off-by: Szymon Morek <szymon.morek@intel.com>
 2021-06-10 12:27:24 +02:00
Zbigniew Zdanowicz
4fa5041f27 Add inline directive to smallest functions 
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2021-06-10 09:27:07 +02:00
Maciej Plewka
689ceacfe6 Fix set allocation adress in SS when offset is patched 
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2021-06-08 13:05:38 +02:00
Zbigniew Zdanowicz
8f91fcdd73 Add new atomic operation 
Related-To: NEO-5244

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2021-06-04 09:00:11 +02:00
Maciej Plewka
159404f38e Revert "Program border color once per dsh" 
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2021-05-18 12:26:58 +02:00
Maciej Plewka
b943ad078f Program border color once per dsh 
Related-To: NEO-4928

Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2021-04-30 13:31:58 +02:00
Milczarek, Slawomir
e5eba8be53 Add setters and getters for coherency type in render surface state 
Signed-off-by: Milczarek, Slawomir <slawomir.milczarek@intel.com>
 2021-04-13 16:12:46 +02:00
Mateusz Jablonski
8215395401 Simplify Context method 
return if context has multiple sub devices related to a given root device

Related-To: NEO-3691
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2021-03-30 10:22:15 +02:00
Zbigniew Zdanowicz
e36941b171 Change argument type in EncodeMemoryPrefetch class 
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2021-03-25 18:27:07 +01:00
Bartosz Dunajski
f9197d4e0d Improve memoryPrefetch method 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2021-03-24 15:12:05 +01:00
Igor Venevtsev
3df6110a17 Add extra parameters to setArgStateful() 
Signed-off-by: Igor Venevtsev <igor.venevtsev@intel.com>
 2021-02-05 12:24:27 +01:00
Bartosz Dunajski
580fdd757c Improve buffer surface state programming 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2021-02-02 14:42:18 +01:00
Bartosz Dunajski
c2e333fe38 Update compression encoding interface + test traits 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2021-01-29 13:57:15 +01:00
Maciej Plewka
3ca77a6cbe Program sba for global bindless heaps 
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2021-01-04 14:23:47 +01:00
Young Jin Yoon
e09ac446c4 Mask bit 0 of timestamp for event profiling 
Related-to: LOCI-1161
Signed-off-by: Young Jin Yoon <young.jin.yoon@intel.com>
 2020-12-31 23:51:12 +01:00
Young Jin Yoon
da779d067f Support the AND operation in EncodeMathMMIO 
Related-to: LOCI-1161
Signed-off-by: Young Jin Yoon <young.jin.yoon@intel.com>
 2020-12-03 01:56:22 +01:00
Maciej Plewka
7a5c9d39b5 Encode dispatch kernel with global bindless heaps 
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2020-12-02 17:30:15 +01:00
Bartosz Dunajski
93ba4e646b Improve EncodeDispatchKernel 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-11-27 16:39:34 +01:00
Bartosz Dunajski
8a703c082e Add encodeExtraCacheSettings method 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-11-25 12:27:20 +01:00
Bartosz Dunajski
ae3ad3e8bc Add method to adjust TimestampPacket 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-11-24 17:35:22 +01:00
Kamil Kopryk
b59aa2f928 Rename command_encoder_base.inl file 
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
Related-To: NEO-4750
 2020-11-17 13:22:00 +01:00
Bartosz Dunajski
39e6548ef6 Add mi_arb_check between blit commands 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-11-17 13:07:50 +01:00
Mateusz Hoppe
65690ccb21 Fix indirect dispatch programming 
Related-To: NEO-5195

Change-Id: I82975abaa6323d27d3718ce1619748f7d83b55b4
Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
 2020-10-28 01:06:08 +01:00
Pawel Wilma
7f8b0c5b3f Global l3 invaldate for blitter engine 
Related-To: NEO-5175

Change-Id: I88b3c9333398c91a7dd799f5e52cfd9182316960
Signed-off-by: Pawel Wilma <pawel.wilma@intel.com>
 2020-10-19 16:40:03 +02:00
Zbigniew Zdanowicz
ca023fa532 Fix L3 and Math programming 
Change-Id: I4ffd729beeed95b0806dd284665c72fb424b0ffc
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-10-13 11:41:38 +02:00
Spruit, Neil R
976dad2e17 Updated BaseSurfaceStateAddressAlignment to PageSize to handle Block R/W in L0 
- Block R/W in kernels requires a minimum of 16B alignment/OWORD
alignment to properly work without data corruption.
- Level Zero currently writes Base Surface State addresses alignment to
4B vs OpenCL writes Base Surface State addresses aligned to PageSize for
4KB.
- Added a function in encode buffer to verify that at a minimum the size
being encoded has the minumum alignment of 4B which is supported, but
will not support Block R/W

Change-Id: I6486c2cbbb0008834c779bf54918388d79c193bb
Signed-off-by: Spruit, Neil R <neil.r.spruit@intel.com>
 2020-10-12 19:14:25 +02:00
Zbigniew Zdanowicz
bf32740f97 Move BTI programming to shared code 
Change-Id: Ie9d67c1d883f24cfec13ea1618d834d746c0d5be
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-10-09 13:56:44 +02:00
Zbigniew Zdanowicz
47f5867e8f Move common code to shared directory 
Change-Id: I5f604de01e06d35cc1e045fffdd4a26d88ffca8c
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-10-07 10:55:39 +02:00
Zbigniew Zdanowicz
ce1b669cda Use single class to program load register command 
Change-Id: I90fe084409588cb32f0ac43a3db5082047d7a68b
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-10-06 13:45:35 +02:00