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109 Commits

Author SHA1 Message Date
Filip Hazubski
7eb81e9d85 Unify StreamProperties structs 
Introduce functions allowing to copy values from one struct to another,
while correctly setting values of isDirty field.

Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2021-05-27 15:37:14 +02:00
Mateusz Jablonski
1281e858df Disable compression flags when image is not compressed 
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2021-05-27 12:05:52 +02:00
Mateusz Hoppe
0f32231fc8 Use correct INTERNAL heap base address for ISA in system memory 
Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
 2021-05-25 10:22:28 +02:00
Filip Hazubski
d693d24f27 Add StateComputeModeProperties to StreamProperties 
Related-To: NEO-4940, NEO-4574


Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2021-05-21 16:39:39 +02:00
Maciej Plewka
159404f38e Revert "Program border color once per dsh" 
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2021-05-18 12:26:58 +02:00
Maciej Plewka
171a614f18 Fix reset border color offset when replacing heap buffer 
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2021-05-05 13:38:02 +02:00
Maciej Plewka
b943ad078f Program border color once per dsh 
Related-To: NEO-4928

Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2021-04-30 13:31:58 +02:00
Daria Hinz
53104e0830 Add a parameter to the encode function 
Signed-off-by: Daria Hinz <daria.hinz@intel.com>
 2021-04-22 12:07:16 +02:00
Milczarek, Slawomir
e5eba8be53 Add setters and getters for coherency type in render surface state 
Signed-off-by: Milczarek, Slawomir <slawomir.milczarek@intel.com>
 2021-04-13 16:12:46 +02:00
Igor Venevtsev
bd32518d31 Add extra parameters to EncodeComputeMode::adjustComputeMode() method 
Signed-off-by: Igor Venevtsev <igor.venevtsev@intel.com>
 2021-03-31 16:51:55 +02:00
Mateusz Jablonski
8215395401 Simplify Context method 
return if context has multiple sub devices related to a given root device

Related-To: NEO-3691
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2021-03-30 10:22:15 +02:00
Zbigniew Zdanowicz
e36941b171 Change argument type in EncodeMemoryPrefetch class 
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2021-03-25 18:27:07 +01:00
Bartosz Dunajski
f9197d4e0d Improve memoryPrefetch method 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2021-03-24 15:12:05 +01:00
Jim Snow
c97fe4c660 Minor cleanup: rename parameter argument 
Signed-off-by: Jim Snow <jim.m.snow@intel.com>
 2021-03-23 00:54:19 +01:00
Daria Hinz
9ac7f1d370 Adding a parameter to a encode function 
Signed-off-by: Daria Hinz <daria.hinz@intel.com>
 2021-03-19 17:54:46 +01:00
Zbigniew Zdanowicz
d6dde3df33 Add internal argument to encode method 
Related-To: NEO-5244

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2021-03-19 09:37:05 +01:00
Maciej Dziuban
66cff28002 Do not use threadDims for indirect dispatches 
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
 2021-03-10 08:04:34 +01:00
Maciej Dziuban
1350aa52fb Pass DispatchInfo to estimation functions 
Related-To: NEO-5546

Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
 2021-03-05 12:47:55 +01:00
Daria Hinz
13fe8ed7f1 Revert "Correct POST_SYNC for L0 Events" 
This reverts commit 04d1a3255357a7778a530f054700e211d94f3b6d.

Signed-off-by: Daria Hinz <daria.hinz@intel.com>
 2021-02-24 10:16:22 +01:00
Daria Hinz
64d772d366 Fix for adding MI_SEMAPHORE_WAIT & reset L0 Event 
Signed-off-by: Daria Hinz <daria.hinz@intel.com>
 2021-02-18 18:33:21 +01:00
Zbigniew Zdanowicz
c35f560971 Refactor internal interface 
Related-To: NEO-5244

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2021-02-15 13:24:00 +01:00
Igor Venevtsev
3df6110a17 Add extra parameters to setArgStateful() 
Signed-off-by: Igor Venevtsev <igor.venevtsev@intel.com>
 2021-02-05 12:24:27 +01:00
Bartosz Dunajski
580fdd757c Improve buffer surface state programming 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2021-02-02 14:42:18 +01:00
Bartosz Dunajski
c2e333fe38 Update compression encoding interface + test traits 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2021-01-29 13:57:15 +01:00
Bartosz Dunajski
b57c1b9650 Improve Image surface state encoding for compression 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2021-01-28 16:39:42 +01:00
Igor Venevtsev
bb72beac6b Add extra parameters to programStateBaseAddress() 
Signed-off-by: Igor Venevtsev <igor.venevtsev@intel.com>
 2021-01-28 16:03:17 +01:00
Jaime Arteaga
444b9594af Expand adjustPipelineSelect parameters 
Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
 2021-01-07 18:01:07 +01:00
Maciej Plewka
3ca77a6cbe Program sba for global bindless heaps 
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2021-01-04 14:23:47 +01:00
Young Jin Yoon
e09ac446c4 Mask bit 0 of timestamp for event profiling 
Related-to: LOCI-1161
Signed-off-by: Young Jin Yoon <young.jin.yoon@intel.com>
 2020-12-31 23:51:12 +01:00
Maciej Plewka
bb825acfff Mark heap as dirty when base address has changed 
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2020-12-29 17:19:51 +01:00
Slawomir Milczarek
6986d5de0b Add helper functions for memory compression to CSR 
Signed-off-by: Slawomir Milczarek <slawomir.milczarek@intel.com>
 2020-12-21 17:43:03 +01:00
Krystian Chmielewski
4948c39d39 Remove executionEnvironment from KernelInfo 
Related-To: NEO-3739
 2020-12-16 14:56:57 +01:00
Jim Snow
37cd49330c Implement ZE_CACHE_CONFIG_FLAG_LARGE_DATA for zeKernelSetCacheConfig 
Signed-off-by: Jim Snow <jim.m.snow@intel.com>
 2020-12-16 07:00:13 +01:00
Filip Hazubski
edbda8e8b2 Pass HwInfo to computeSlmValues function 
Resolves: NEO-5215, NEO-5216

Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2020-12-07 20:23:28 +01:00
Young Jin Yoon
da779d067f Support the AND operation in EncodeMathMMIO 
Related-to: LOCI-1161
Signed-off-by: Young Jin Yoon <young.jin.yoon@intel.com>
 2020-12-03 01:56:22 +01:00
Maciej Plewka
7a5c9d39b5 Encode dispatch kernel with global bindless heaps 
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2020-12-02 17:30:15 +01:00
Jaime Arteaga
be90b9ff93 Add support for ZE_DEVICE_MEM_ALLOC_FLAG_BIAS_UNCACHED 
Add support for device and shared allocations that use the
ZE_DEVICE_MEM_ALLOC_FLAG_BIAS_UNCACHED flag, whether the
kernel using the memory is stateless or statefull.

Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
 2020-12-02 10:43:45 +01:00
Bartosz Dunajski
93ba4e646b Improve EncodeDispatchKernel 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-11-27 16:39:34 +01:00
Bartosz Dunajski
8a703c082e Add encodeExtraCacheSettings method 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-11-25 12:27:20 +01:00
Bartosz Dunajski
ae3ad3e8bc Add method to adjust TimestampPacket 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-11-24 17:35:22 +01:00
Vinod Tipparaju
240563099c Clean up code for nullptr device check during cmdlist create 
Signed-off-by: Vinod Tipparaju <vinod.tipparaju@intel.com>
 2020-11-19 04:24:34 +01:00
Kamil Kopryk
b59aa2f928 Rename command_encoder_base.inl file 
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
Related-To: NEO-4750
 2020-11-17 13:22:00 +01:00
Bartosz Dunajski
39e6548ef6 Add mi_arb_check between blit commands 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-11-17 13:07:50 +01:00
Vinod Tipparaju
8e6be83fcc Add cmdContainer ULTs - idOffset & numIdd reset, Gfx alloc failure 
ULT required to cover IDOffset and numIdd values during reset.
ULT required to cover OUT_OF_MEM retrun during init.
Fix to check for valid gfx allocation inside heap helper & destructor

Change-Id: Ied9049b33dc0605d5f5f51c96114d5e96b26a4f7
Signed-off-by: Vinod Tipparaju <vinod.tipparaju@intel.com>
 2020-11-03 13:22:44 +01:00
Mateusz Hoppe
65690ccb21 Fix indirect dispatch programming 
Related-To: NEO-5195

Change-Id: I82975abaa6323d27d3718ce1619748f7d83b55b4
Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
 2020-10-28 01:06:08 +01:00
Pawel Wilma
7f8b0c5b3f Global l3 invaldate for blitter engine 
Related-To: NEO-5175

Change-Id: I88b3c9333398c91a7dd799f5e52cfd9182316960
Signed-off-by: Pawel Wilma <pawel.wilma@intel.com>
 2020-10-19 16:40:03 +02:00
Zbigniew Zdanowicz
ca023fa532 Fix L3 and Math programming 
Change-Id: I4ffd729beeed95b0806dd284665c72fb424b0ffc
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-10-13 11:41:38 +02:00
Spruit, Neil R
976dad2e17 Updated BaseSurfaceStateAddressAlignment to PageSize to handle Block R/W in L0 
- Block R/W in kernels requires a minimum of 16B alignment/OWORD
alignment to properly work without data corruption.
- Level Zero currently writes Base Surface State addresses alignment to
4B vs OpenCL writes Base Surface State addresses aligned to PageSize for
4KB.
- Added a function in encode buffer to verify that at a minimum the size
being encoded has the minumum alignment of 4B which is supported, but
will not support Block R/W

Change-Id: I6486c2cbbb0008834c779bf54918388d79c193bb
Signed-off-by: Spruit, Neil R <neil.r.spruit@intel.com>
 2020-10-12 19:14:25 +02:00
Kamil Diedrich
9e463ab45f Track all ssh in cmdList 
Change-Id: Ibffb7b7b406e5e17d4ffb971fd0789557c879367
 2020-10-12 12:12:12 +02:00
Zbigniew Zdanowicz
bf32740f97 Move BTI programming to shared code 
Change-Id: Ie9d67c1d883f24cfec13ea1618d834d746c0d5be
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-10-09 13:56:44 +02:00