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156 Commits

Author SHA1 Message Date
Daria Hinz
9ac7f1d370 Adding a parameter to a encode function 
Signed-off-by: Daria Hinz <daria.hinz@intel.com>
 2021-03-19 17:54:46 +01:00
Zbigniew Zdanowicz
d6dde3df33 Add internal argument to encode method 
Related-To: NEO-5244

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2021-03-19 09:37:05 +01:00
Maciej Dziuban
1350aa52fb Pass DispatchInfo to estimation functions 
Related-To: NEO-5546

Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
 2021-03-05 12:47:55 +01:00
Daria Hinz
13fe8ed7f1 Revert "Correct POST_SYNC for L0 Events" 
This reverts commit 04d1a3255357a7778a530f054700e211d94f3b6d.

Signed-off-by: Daria Hinz <daria.hinz@intel.com>
 2021-02-24 10:16:22 +01:00
Daria Hinz
64d772d366 Fix for adding MI_SEMAPHORE_WAIT & reset L0 Event 
Signed-off-by: Daria Hinz <daria.hinz@intel.com>
 2021-02-18 18:33:21 +01:00
Zbigniew Zdanowicz
c35f560971 Refactor internal interface 
Related-To: NEO-5244

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2021-02-15 13:24:00 +01:00
Igor Venevtsev
3df6110a17 Add extra parameters to setArgStateful() 
Signed-off-by: Igor Venevtsev <igor.venevtsev@intel.com>
 2021-02-05 12:24:27 +01:00
Bartosz Dunajski
580fdd757c Improve buffer surface state programming 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2021-02-02 14:42:18 +01:00
Bartosz Dunajski
c2e333fe38 Update compression encoding interface + test traits 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2021-01-29 13:57:15 +01:00
Bartosz Dunajski
b57c1b9650 Improve Image surface state encoding for compression 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2021-01-28 16:39:42 +01:00
Jaime Arteaga
444b9594af Expand adjustPipelineSelect parameters 
Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
 2021-01-07 18:01:07 +01:00
Young Jin Yoon
e09ac446c4 Mask bit 0 of timestamp for event profiling 
Related-to: LOCI-1161
Signed-off-by: Young Jin Yoon <young.jin.yoon@intel.com>
 2020-12-31 23:51:12 +01:00
Jim Snow
37cd49330c Implement ZE_CACHE_CONFIG_FLAG_LARGE_DATA for zeKernelSetCacheConfig 
Signed-off-by: Jim Snow <jim.m.snow@intel.com>
 2020-12-16 07:00:13 +01:00
Young Jin Yoon
da779d067f Support the AND operation in EncodeMathMMIO 
Related-to: LOCI-1161
Signed-off-by: Young Jin Yoon <young.jin.yoon@intel.com>
 2020-12-03 01:56:22 +01:00
Maciej Plewka
7a5c9d39b5 Encode dispatch kernel with global bindless heaps 
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2020-12-02 17:30:15 +01:00
Jaime Arteaga
be90b9ff93 Add support for ZE_DEVICE_MEM_ALLOC_FLAG_BIAS_UNCACHED 
Add support for device and shared allocations that use the
ZE_DEVICE_MEM_ALLOC_FLAG_BIAS_UNCACHED flag, whether the
kernel using the memory is stateless or statefull.

Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
 2020-12-02 10:43:45 +01:00
Bartosz Dunajski
93ba4e646b Improve EncodeDispatchKernel 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-11-27 16:39:34 +01:00
Bartosz Dunajski
8a703c082e Add encodeExtraCacheSettings method 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-11-25 12:27:20 +01:00
Bartosz Dunajski
ae3ad3e8bc Add method to adjust TimestampPacket 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-11-24 17:35:22 +01:00
Bartosz Dunajski
39e6548ef6 Add mi_arb_check between blit commands 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-11-17 13:07:50 +01:00
Mateusz Hoppe
65690ccb21 Fix indirect dispatch programming 
Related-To: NEO-5195

Change-Id: I82975abaa6323d27d3718ce1619748f7d83b55b4
Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
 2020-10-28 01:06:08 +01:00
Pawel Wilma
7f8b0c5b3f Global l3 invaldate for blitter engine 
Related-To: NEO-5175

Change-Id: I88b3c9333398c91a7dd799f5e52cfd9182316960
Signed-off-by: Pawel Wilma <pawel.wilma@intel.com>
 2020-10-19 16:40:03 +02:00
Spruit, Neil R
976dad2e17 Updated BaseSurfaceStateAddressAlignment to PageSize to handle Block R/W in L0 
- Block R/W in kernels requires a minimum of 16B alignment/OWORD
alignment to properly work without data corruption.
- Level Zero currently writes Base Surface State addresses alignment to
4B vs OpenCL writes Base Surface State addresses aligned to PageSize for
4KB.
- Added a function in encode buffer to verify that at a minimum the size
being encoded has the minumum alignment of 4B which is supported, but
will not support Block R/W

Change-Id: I6486c2cbbb0008834c779bf54918388d79c193bb
Signed-off-by: Spruit, Neil R <neil.r.spruit@intel.com>
 2020-10-12 19:14:25 +02:00
Zbigniew Zdanowicz
bf32740f97 Move BTI programming to shared code 
Change-Id: Ie9d67c1d883f24cfec13ea1618d834d746c0d5be
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-10-09 13:56:44 +02:00
Zbigniew Zdanowicz
47f5867e8f Move common code to shared directory 
Change-Id: I5f604de01e06d35cc1e045fffdd4a26d88ffca8c
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-10-07 10:55:39 +02:00
Zbigniew Zdanowicz
ce1b669cda Use single class to program load register command 
Change-Id: I90fe084409588cb32f0ac43a3db5082047d7a68b
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-10-06 13:45:35 +02:00
Maciej Dziuban
138f04bdcd Enable L1 cache for Tigerlake 
Change-Id: I33513ed084f9d06ceca11315cac03f1b682db535
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
Related-To: NEO-4832
 2020-10-06 13:26:54 +02:00
Zbigniew Zdanowicz
2717fcae54 Unify programming of atomic command 
Change-Id: I13afdb44fb83beaa8673eb6456d2a8edcb6ac047
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-10-05 13:37:52 +02:00
Zbigniew Zdanowicz
394e626db9 Refactor programming of surface states 
Related-To: NEO-5069

Change-Id: Id7442fcdcc8c7df57f00e8dc383c11869bf1a677
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-09-16 11:54:00 +02:00
Mateusz Hoppe
c3a128f9f4 Refactor StateBaseAddressHelper 
Change-Id: I5071a1a4a067b8f0e880a4f7e1d65e79eeb77c47
Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
 2020-08-04 11:09:41 +02:00
Maciej Plewka
a168040f61 Move setAdditionalData to shared 
Releated-To: NEO-4568

Change-Id: If12f64d51b922da76bb163ed7797897416075af7
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2020-08-04 11:08:59 +02:00
Zbigniew Zdanowicz
2fca4e3477 Refactor programming of additional data of interface descriptor 
Related-To: NEO-4570

Change-Id: I3338046f037878085eddaaeb2c8bbdd821fc1515
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-07-24 14:25:39 +02:00
Bartosz Dunajski
f6c893a801 Pass HardwareInfo to programMemoryPrefetch 
Change-Id: I5ed0ae35143ef244e08bc88ba8817ce1cb17369c
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-07-24 12:43:21 +02:00
Zbigniew Zdanowicz
134462919d Move barrier programming to Encode class 
Related-To: NEO-4576

Change-Id: I34b93b3118528b449c4e1b81826f9784633377a9
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-07-17 14:28:46 +02:00
Zbigniew Zdanowicz
bac5506b62 Modify function dispatching cross and per-thread data 
Related-To: NEO-4585

Change-Id: Ia6b54b8d0c868cab5403332411655dc8c9ef4c8d
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-07-08 19:30:23 +02:00
Zbigniew Zdanowicz
c4cb8c1c81 Add thread programming to Encode class 
Related-To: NEO-4585

Change-Id: I45e57038af23a60f52b57eb1888f8220b77f5e56
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-06-29 20:24:26 +02:00
Maciej Plewka
a822503b41 Use encoder to program buffer surface state 
Change-Id: Ibe66bd9906743b021a04f1d9aad1aae4127a4f71
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2020-06-25 12:32:29 +02:00
Zbigniew Zdanowicz
e286ada6b5 Add function to check local id generation required 
Related-To: NEO-4585

Change-Id: I97c6a728dd08cde5e08ffcad1220a1ef007e1bae
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-06-08 17:15:05 +02:00
Maciej Plewka
008af5b6e4 Add event profiling for copy commandLists 
Change-Id: I9f13e48b4139b3ce3c802c2d38b0ce054e64562c
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2020-06-02 19:35:13 +02:00
Lukasz Jobczyk
02f2f22045 Add profiling support for blitter 
Resolves: NEO-4121

Change-Id: I29dfcf07d48100c578cbc432fee4d87dfa18e8f4
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2020-05-29 13:43:14 +02:00
Mateusz Hoppe
77e4ac0a18 Bindless addressing support in EncodeDispatchKernel 
Related-To: NEO-4607

Change-Id: Ib89b07f71f32c3a623f86212b5305b4aa02e1fb7
Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
 2020-05-12 21:02:06 +02:00
Lukasz Jobczyk
536c50234f Pass linear stream to encode MMIO 
Change-Id: I07bafc49676e31fb457a63f4655a98fd0c793389
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2020-05-04 14:48:49 +02:00
Lukasz Jobczyk
9db47c7421 Apply WA for walker command 
Resolves: NEO-4490

Change-Id: I1a6e04ec64578e630dc2238c5d3e036a4a3ef24b
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2020-04-21 19:05:15 +02:00
Maciej Plewka
691a4ea823 Add blit copy implementation for L0 
Change-Id: I327a4cf977e166cb648ee9f3a79374f7cefa7b1b
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2020-04-09 13:36:09 +02:00
Bartosz Dunajski
3ce0450a9c Update interface for memory prefetch 
Change-Id: I1dfbbd93b97dae100de489319dcfd7d19fe1fc65
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-04-09 13:15:56 +02:00
Jaroslaw Chodor
2c25777f3c DispatchKernelEncoder refactor 
Replacing parts of DispatchKernelEncoder with KernelDescriptor

Change-Id: I1c780b04a2d3d1de0fb75d5413a0dde8b41bbe07
 2020-04-08 16:19:21 +02:00
Bartosz Dunajski
32e1b7d1a7 Add helper for encoding memory prefetch 
Change-Id: I481ec11b66ad392ba9748bb5bbb6fd0ad3ce7f12
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-04-03 18:34:39 +02:00
Lukasz Jobczyk
d1bc7199de Switch to 3D pipeline to program selected commands - part 2 
Resolves: NEO-4447

Change-Id: I1dd6a9694cdf3be19aadec1cd139c466baecbcd7
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2020-04-01 10:42:55 +02:00
Maciej Plewka
5de8f3ac3d Unify setting compute mode 
Change-Id: I8fd5a0cf1a121498efbbf1edb332920578d91598
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2020-03-26 16:08:29 +01:00
Bartosz Dunajski
24c6a1ed96 Add MI_FLUSH_DW command estimation 
Change-Id: I71d966209ce1a9996bfe3f48f3d8da00156211a3
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-03-13 14:11:24 +01:00