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1412 Commits

Author SHA1 Message Date
Hoppe, Mateusz
63ebe252eb Aubstream header update 
Change-Id: I68573223715e5cbb6a308b88d9bae35741ef9984
 2019-02-26 19:27:36 +01:00
Piotr Fusik
d79f1afdc2 GraphicsAllocation constructor accepts allocationType and memoryPool. 
Change-Id: I5044ed26ba0cb0fc9ca7077595f5ab56353ab58c
 2019-02-26 13:29:25 +01:00
Jablonski, Mateusz
798137e4bb Add function to create devices bitfield based on allocation properties 
Change-Id: Ic70443b1fb6106186efcff318690e434dc1db625
Signed-off-by: Jablonski, Mateusz <mateusz.jablonski@intel.com>
 2019-02-26 12:07:09 +01:00
Mrozek, Michal
ce77425428 Add support for reserveGpuVirtualAddress. 
Change-Id: I068df0dd3b2064cdb93be1c4408eeb86ff264d2f
 2019-02-26 12:01:17 +01:00
Zdunowski, Piotr
842fb5dadc [4/n] Log allocation placement. 
Change-Id: I300be5f09b6ee77aa89584a6bddf4c7e57aa54f1
 2019-02-26 10:21:42 +01:00
Piotr Fusik
378bd28bab Change the signature of MemoryManager::createGraphicsAllocation. 
Change-Id: Ia82235ff2831fd5b3436d488a5946bb49d63ce91
 2019-02-25 16:08:35 +01:00
Maciej Dziuban
0cf71414e2 Pass command stream to dispatch scheduler 
instead of taking it from CommandQueue

Change-Id: I8e43c3b7ed5cb46f79edf3290a84fc6ad41f3b57
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
 2019-02-25 14:35:19 +01:00
Hoppe, Mateusz
432b8f20a7 Allow cpu copy with debug keys only when ready waitlist events 
Change-Id: If9293787c76b8248a84e25d03cbf9a9b5aaf7cca
 2019-02-22 17:39:57 +01:00
Mrozek, Michal
1ae92e995a Extract some code blocks to dedicated methods. 
Change-Id: I9e47631367b95ce4ff5479c463a3cb5085b66315
 2019-02-22 15:12:45 +01:00
Mrozek, Michal
e4bffaa194 Route all enqueue without kernel calls directly to enqueueHandler. 
Change-Id: I4c4ab013ff9adbe0e32e2661b3091f319d36c9c3
 2019-02-22 14:19:22 +01:00
Katarzyna Cencelewska
edb3e14147 Fix for enum's name 
change lowercase 'b' for uppercase 'B'

Change-Id: I35f973bc7966e9d5b9f38d4e4a370215e80012ac
 2019-02-22 11:59:17 +01:00
dongwonk
b44d434a89 limited GPU range is used for external 32bit allocation 
Change-Id: I494ad97fb1ddfa7b3c6b2e7cef2ae04fba571ba0
Signed-off-by: dongwonk <dongwon.kim@intel.com>
 2019-02-21 16:26:49 -08:00
Milczarek, Slawomir
278bb83c56 Enable AUB sub-capture in AubStream captures (1/n) 
Change-Id: I6bd0605d06cf4dc3937e2dbeba7ed7037ae91476
 2019-02-21 22:40:40 +01:00
dongwonk
56972935ad graphic memory allocation with alignment in limited Range heap 
Change-Id: Iccfb0fdc2f161e30bfdd26154110185277f176f5
Signed-off-by: dongwonk <dongwon.kim@intel.com>
 2019-02-21 10:10:47 -08:00
Piotr Fusik
4ec5be0c99 Simplify code by removing AllocationOrigin. 
Change-Id: Ie73cefc1ae1ee846fb9a5ef1054af01cd1867a4d
 2019-02-21 16:29:05 +01:00
Maciej Dziuban
90e970cee6 Create GraphicsAllocation during dispatch when queue is blocked 
Change-Id: I8a6f9e14ff57e7ed2920260af291317805f4df13
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
 2019-02-21 15:28:17 +01:00
Piotr Fusik
3e2a2ec191 Do not truncate to size_t while aligning. 
Change-Id: If92e3b20c0ba08a6024116a44463c72ff4cfddce
 2019-02-21 14:18:34 +01:00
Hoppe, Mateusz
98db6147d8 Pass full aubfile name to initAubCenter when using TBX with AubDump 
Change-Id: I9184ce38cd9a066259bbf3a5b8a56694d4e309b4
 2019-02-21 12:39:10 +01:00
Jablonski, Mateusz
9e7c30cb06 Choose Standard or Standard64 heap depending on 64KB suitablity of resource 
Change-Id: I633b1bef1cdef2c5149909c997adc85434bcaf73
Signed-off-by: Jablonski, Mateusz <mateusz.jablonski@intel.com>
 2019-02-21 12:18:26 +01:00
Mrozek, Michal
65d706bdc3 Add mm_pause in waiting loop. 
Change-Id: I9b7efd9869d91ff0f2bc289379ea49a7fd1013fa
 2019-02-21 12:09:36 +01:00
Mrozek, Michal
a1d4c07f45 Simplify DRM allocation constructors. 
Change-Id: I2c477ce85f4748f0637451a405f7949aa829ba81
 2019-02-21 12:06:01 +01:00
Mrozek, Michal
45a0ceecfb Clean drm interfaces. 
- all driver allocations are using SoftPin
- remove unneeded methods.
- remove unneeded members.
- remove unneeded code paths.

Change-Id: I3369c0a4d37727210b5a26271d25537ca5218bd4
 2019-02-20 16:11:19 +01:00
Katarzyna Cencelewska
c9a8f9b1be GlSharingFunction tests update 
Add mock of opengl32.dll to check that sharing functions are loaded

Change-Id: I361707ee9a506e84db51d4fa9c98823db2550fae
 2019-02-20 16:05:32 +01:00
Piotr Fusik
75edea81bb Virtual address space partitioning on Linux [2/n] 
Move selectHeap from Wddm to MemoryManager.
Set DrmAllocation::origin.

Change-Id: I5d412e35d524d1f31174893b9ce1d3b1e98eee96
 2019-02-20 14:43:08 +01:00
Mrozek, Michal
4139e88982 Allocate command buffers with proper allocation type. 
Change-Id: I912dd41cf68fa16ab481bb003c4f5ae63f1f04c4
 2019-02-20 12:52:45 +01:00
Mrozek, Michal
65625e22bf Enhance force shared physical memory flag. 
- forces zero copy for all buffers created with this flag.

Change-Id: Ib76b452e286dcbd3481f1c96f3a48db63fb5c4b5
 2019-02-20 12:26:27 +01:00
Dunajski, Bartosz
23fcbb3265 WriteMemory support in HardwareContextController 
Change-Id: Ie63b12fb8fb78a2d68b8ed84c1ebe9d634e9804b
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-02-20 11:29:19 +01:00
Daria Hinz
82613a0750 Return buffer compressed when render buffer compressed is enable 
Change-Id: I62fde1573849139ca16ff9d7e5d5672eab7ccd2b
 2019-02-19 15:02:48 +01:00
Maciej Dziuban
802eb37394 Revert "Pass HardwareInfo to AubHelper::checkPTEAddress()" 
Delete AubHelper::checkPTEAddress()

This reverts commit aa587b3bc5.

Change-Id: I32b90ce7dddfd2347586b2c47b9114b45cced8ab
 2019-02-19 11:51:35 +01:00
Dunajski, Bartosz
64fbfb21bf Improve iterating over existing CommandStreamReceivers 
Change-Id: I12a10852d43c625ec5521ae91918fcb12e1a6aec
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-02-19 11:48:56 +01:00
Zdunowski, Piotr
d99e833786 Program L3 error detection behavior. 
Change-Id: Ifeccb707376f5b267de58ffd6ad009cf000c5047
 2019-02-19 11:23:07 +01:00
Jablonski, Mateusz
ed6381a66a Use HEAP_STANDARD64Kb when cpu access is required 
Change-Id: I3a451b618f1b72836cd640ed510e874cf2d60624
Signed-off-by: Jablonski, Mateusz <mateusz.jablonski@intel.com>
 2019-02-19 10:36:15 +01:00
Maciej Dziuban
aa587b3bc5 Pass HardwareInfo to AubHelper::checkPTEAddress() 
Change-Id: Ie5370b52eb79a8d118bd8033a335dc1319e93be1
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
 2019-02-19 08:37:58 +01:00
Jablonski, Mateusz
05d02a6fe7 Change DevicesBitfield type to struct 
Change-Id: I7a005b07737cdd21efc174a2ee2be0f6b7f9068d
Signed-off-by: Jablonski, Mateusz <mateusz.jablonski@intel.com>
 2019-02-18 13:57:50 +01:00
Dunajski, Bartosz
ba681035f8 Add new CSR to ExecutionEnvironment 
Change-Id: I5d6b58b5c185bf283ae529ebb21a4cbc8e9f198c
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-02-18 11:39:09 +01:00
Hoppe, Mateusz
7f98db617c Move expectMemory/writeMemory methods to CSRSimulatedCommon 
- fix aub tests with --tbx option

Change-Id: I227449dd8614a8aada3eaa4f28ff6dcca7530956
 2019-02-18 10:01:32 +01:00
Jobczyk, Lukasz
2bcecf3e62 Align command buffers to 64KB 
Change-Id: Id1fbd7c6f1aee48c4b69ec305d5332cb0aa86507
Signed-off-by: Jobczyk, Lukasz <lukasz.jobczyk@intel.com>
 2019-02-18 09:58:45 +01:00
Dunajski, Bartosz
af2dc200c5 Improve creating HwContextController 
Change-Id: If81ec18793a5af7fb58d66bb26a3bc476eaf94e0
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-02-18 08:57:35 +01:00
Piotr Fusik
9af011809f Make HeapIndex and GraphicsAllocation::origin not specific to Windows. 
Change-Id: Ie5a26b45c0b5eff0daf047361d8c992bd3c65ba7
 2019-02-18 08:47:49 +01:00
dongwonk
fb993d6107 limited range and internal 32bit allocators with correct base and size 
correct add 1 to the current size, gpuRange as gpuRange
only specifies the end address of the pool, not the actual
size, which causes alignment issue of all the offsets of
allocated objects. Also, a page was added in the beginning
of the limited range memory pool to avoid the base address
of it to be 0x0 that is interpreted as invalid address by
heap allocator (This makes the size reduced by pageSize)

Internal 32bit allocator is also initialized in proper way
with corrected base address.

v2: added 'givenMemoryManagerLimimedRangeAllocator' unit
    test
v3: adjust size to be freed when DrmMemoryManager instance
    is destroyed to 4GB
v4: - defined external 32bit allocator for limited Range
    allocation case.
    - softpinning object on the correct GPU address

Change-Id: Idaa0206d4133a1476cceb5a48ff8c8528742c76a
Signed-off-by: dongwonk <dongwon.kim@intel.com>
 2019-02-17 19:19:52 +01:00
Pawel Wilma
8272b3f3de Add missing numGrfRequired in blocked kernel DispatchFlags 
Change-Id: Ic1ddd532d8420c9a797a561cc5cb8ee74831eeaa
 2019-02-16 11:37:48 +01:00
dongwonk
c2f5fccfd0 DrmAllocation with correct pair of cpu address and gpu address 
correct mapping of cpu and gpu address in memory allocation
in case of NonSVM. Also, used only aligned address since offset
is already calculated and written to "allocationOffset".
gpuBaseAddress is programmed with 0 instead of base address of
heap because it represents GPU's address space.

v2: add allocationOffset to the aligned address in allocation
    data to point to exact starting address of buffer in two
    NonSVM allocation unit tests

Change-Id: I32ef512de64a13459b7c132672f837c5cb210ada
Signed-off-by: dongwonk <dongwon.kim@intel.com>
 2019-02-15 19:03:26 +01:00
dongwonk
0240f239ad check if the whole object region is in 32Bit address space boundary 
checks the address + size of buffer object to determine
whether the object is located within 32bit address space
boundary.

v2: changed end year to 2019 in ther license term
v3: added unit test for checking of flag when size of
    bo is given.
v4: two different unit tests are created to cover two
    different case separately

Change-Id: Ie2df6025fc116aca679dcfe88d858ff240278c39
Signed-off-by: dongwonk <dongwon.kim@intel.com>
 2019-02-15 16:15:06 +01:00
Zdanowicz, Zbigniew
51d34da7ec Add multiEngineQueue field to DispatchFlags and modify interfaces 
Change-Id: Iaa4754a22e9b88201aed7df01c7d6e5fd06c84a9
 2019-02-14 17:12:15 +01:00
Maciej Dziuban
12245bc88d Pass hwInfo to AubHelper::getMemBankSize() 
Change-Id: If77775cb5fb10dc82e0c7bef06a71e4292ceb6f9
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
 2019-02-14 16:52:10 +01:00
Dunajski, Bartosz
958d931cd9 Allow to create HardwareContextController for multiple Devices 
Change-Id: Ib066c937809536196182ca87359c487570cc2e89
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-02-14 16:00:00 +01:00
Zdanowicz, Zbigniew
8e1e874a76 Refactor headers and reorder include order 
Change-Id: I6b341e2b37e569af7d741bfd7a63804c0b25a4c9
 2019-02-14 13:39:01 +01:00
Kamil Diedrich
76276d4c23 Add unit test for events 
Change-Id: I13d74626a244d234a5bbaff369ed09fb59d6e33f
 2019-02-14 12:42:44 +01:00
Jablonski, Mateusz
e74b31691c Remove redundant parameter of createWddmAllocation method 
Change-Id: I1c1014eacbdee4ab6b83ea7d7b5257f25f2b46dd
Signed-off-by: Jablonski, Mateusz <mateusz.jablonski@intel.com>
 2019-02-14 07:33:45 +01:00
Jobczyk, Lukasz
b44c60ddc0 Use GPU addresses when setting up scheduler kernel's SVM args 
Change-Id: Ia2d67d031ffce2413dd8c73d87c9d3d8f3d71ede
Signed-off-by: Jobczyk, Lukasz <lukasz.jobczyk@intel.com>
 2019-02-14 07:21:31 +01:00