Commit Graph

142 Commits

Author SHA1 Message Date
Katarzyna Cencelewska
bbd75959d5 Calculate CS timestamp based on OA timestamp and frequencies ratio
Changes affect cores up to xe_hpg

Resolves: NEO-7346
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
2022-10-28 16:26:53 +02:00
Lukasz Jobczyk
5a2f00d295 Apply basic WA only for multi CCS on DG2
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2022-10-28 11:34:52 +02:00
Dominik Dabek
6cf8b4daca Correct tg dispatch size heuristic
Multiply available thread count by tile count
if implicit scaling is used

Related-To: NEO-6989

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-10-27 17:24:53 +02:00
Dunajski, Bartosz
7ff37cd5fd Ftr/WA flags cleanup
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-10-26 12:11:31 +02:00
Compute-Runtime-Validation
5e36b1fcbf Revert "Calculate CS timestamp based on OA timestamp and frequencies ratio"
This reverts commit 03c528382f.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2022-10-16 11:14:46 +02:00
Katarzyna Cencelewska
03c528382f Calculate CS timestamp based on OA timestamp and frequencies ratio
Resolves: NEO-7346
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
2022-10-13 17:41:49 +02:00
Yates, Brandon
71bef6094d Use max enabled slice in debugger thread mapping
Signed-off-by: Yates, Brandon <brandon.yates@intel.com>
2022-10-03 18:11:50 +02:00
Maciej Bielski
56cb1f757b programStateBaseAddress: improve code reuse
Another step towards cleaner callers of
StateBaseAddressHelper<>::programStateBaseAddress.

Export programming state base address into a separate function to
improve code reuse and reduce copy-pasted fragments, which make code
modifications or maintenance more and more difficult over time. Use
specialization for gen-specific variations.

Related-To: NEO-6774
Signed-off-by: Maciej Bielski <maciej.bielski@intel.com>
2022-09-21 11:54:57 +02:00
Mateusz Jablonski
cfe51ff2ba Remove not used isSimulation functions
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-09-20 11:01:55 +02:00
Zbigniew Zdanowicz
cee520b311 simplify systolic mode code and reduce double implementation
Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-09-15 11:57:54 +02:00
Zbigniew Zdanowicz
647661e701 add pipeline select hw properties support flags
Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-09-14 11:23:44 +02:00
Compute-Runtime-Validation
c2cd1a2698 Revert "Do not expose RCS on DG2"
This reverts commit 69c9a4e86c.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2022-09-12 01:31:19 +02:00
Andrzej Koska
69c9a4e86c Do not expose RCS on DG2
The RCS is no longer exposed under windows and linux on DG2

Related-To: NEO-7224
Signed-off-by: Andrzej Koska <andrzej.koska@intel.com>
2022-09-09 13:20:31 +02:00
Dominik Dabek
a72213943e Change DG2 l1 cache policy to WB
With compiler LSC WAs this gives better performance.

If debugger is active, policy will not be changed ie.
will be WBP.

Related-To: NEO-7003

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-09-08 12:14:52 +02:00
Dominik Dabek
485ba234f3 Revert change DG2 l1 cache policy
This reverts cache policy back to WBP,
due to functional regressions

Related-To: NEO-7003

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-09-02 12:02:14 +02:00
Zbigniew Zdanowicz
c3f7e40a8d Rename special pipeline select mode to systolic
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-08-31 22:16:26 +02:00
Dominik Dabek
8cc0177f1c Change DG2 l1 cache policy to WB
With compiler LSC WAs this gives better performance.

If debugger is active, policy will not be changed ie.
will be WBP.

Related-To: NEO-7003

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-08-31 14:31:23 +02:00
Maciej Plewka
fe73c06b59 Disable overdispatch for specific Arc devices
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2022-08-31 12:09:54 +02:00
Zbigniew Zdanowicz
816e059c66 connect hardware support with front end properties state management
Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-08-31 11:09:10 +02:00
Compute-Runtime-Validation
2621460e80 Revert "Change DG2 l1 cache policy to WB"
This reverts commit a820e73dd7.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2022-08-27 08:04:19 +02:00
Patryk Wrobel
c0342a0ab5 Optimize binaries' size by adjusting linkage of constants in headers
When header is included for the first time in translation unit,
then preprocessor simply copy-pastes its content. If we define a
constant in a header file and this constant has internal linkage
then each and every translation unit, which includes this header
will have its own copy of this constant.

C++17 introduces inline variables, which are meant to allow creation
of variables in header files, which do not cause multiple instances.

The inline variable has a single instance when:
- constexpr is used without static (constexpr implicitly implies inline)
- inline is used without static
- inline const is used without static (const does not imply internal linkage
when used with inline)

Signed-off-by: Patryk Wrobel <patryk.wrobel@intel.com>
2022-08-26 22:52:04 +02:00
Dominik Dabek
a820e73dd7 Change DG2 l1 cache policy to WB
With compiler LSC WAs this gives better performance.

If debugger is active, policy will not be changed ie.
will be WBP.

Related-To: NEO-7003

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-08-26 12:58:45 +02:00
Naklicki, Mateusz
98500ee653 Allow overriding hw config on aub/tbx mode
Signed-off-by: Naklicki, Mateusz <mateusz.naklicki@intel.com>
2022-08-25 10:54:42 +02:00
Zbigniew Zdanowicz
72c3a04bfd connect hardware pipeline properties support flags to stream properties
Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-08-24 14:32:29 +02:00
Compute-Runtime-Validation
54041d0f2f Revert "Add hardware support for each pipeline property"
This reverts commit 02cf62902b.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2022-08-24 04:54:22 +02:00
Zbigniew Zdanowicz
02cf62902b Add hardware support for each pipeline property
This change is a baseline for tight control over
when dispatch pipeline state commands and which
pipeline state properties can be changed for a
given hardware platform

Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-08-23 17:29:14 +02:00
Zbigniew Zdanowicz
6c38b36251 Unify getting state base address command space from command buffer
Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-08-17 11:49:02 +02:00
Rafal Maziejuk
ed0c36117e Apply heuristics when setting TG dispatch size on XE_HPC_CORE
The default TG dispatch size can be changed
to a better value based on number of threads in TG or
currently available amount of threads on GPU.
Decision on what TG dispatch size should be are based on
implemented heuristics.

Signed-off-by: Rafal Maziejuk <rafal.maziejuk@intel.com>
Related-To: NEO-6989
2022-08-08 16:43:10 +02:00
Dunajski, Bartosz
98d776867f Add initial support for KernelArgsBuffer allocation
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-08-03 20:28:21 +02:00
Compute-Runtime-Validation
b3078cfbae Revert "Change DG2 l1 cache policy to WB"
This reverts commit 9a5e619c42.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2022-07-28 07:27:13 +02:00
Dominik Dabek
9a5e619c42 Change DG2 l1 cache policy to WB
With compiler LSC WAs this gives better performance.

Related-To: NEO-7003

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-07-27 10:20:36 +02:00
Mateusz Jablonski
8424b27754 Rename core family names to meet naming convention
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-07-26 16:36:49 +02:00
Kamil Kopryk
aed26ec51d Add DisableForceToStateless debug flag
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
2022-07-19 14:08:28 +02:00
Bartosz Dunajski
52b00a11b0 Remove LSH from CommandQueue
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2022-07-19 08:47:02 +02:00
Szymon Morek
9203f8787b Add template structs for L1 cache policy helper
Related-To: NEO-7003

Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2022-07-15 16:14:49 +02:00
Daria Hinz
01af53b63c Setting default device id for acronym
This PR includes:
- Move product config implementation from
ocloc arg helper to product config helper.
- Add default device id setting for each platform configuration.
- Add & move hw info config tests from opencl to shared

Signed-off-by: Daria Hinz <daria.hinz@intel.com>
Related-To: NEO-7112
2022-07-15 12:28:58 +02:00
Artur Harasimiuk
6cb44ae0d9 includes refactor
use gen specific hw_cmds instead of all-in-one

Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
2022-07-08 17:02:19 +02:00
Artur Harasimiuk
1f9960b305 hw_cmds.h for XE refactor
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
2022-07-07 12:17:53 +02:00
Artur Harasimiuk
e245523730 per gen/per sku TEST_F/TEST_P refactor
In gen/sku specific tests include only required files to reduce
dependency on not related HW scpecific headers and improve build
performance.
This is achieved by reduce in usage of hw_test.h and related collateral,
like shared/source/helpers/definitions/hw_cmds.h which can be replaced
by sku specific hw_cmds_<sku>.h

Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
2022-07-06 23:13:46 +02:00
Lukasz Jobczyk
880464da77 Apply additional synchronization WA to DG2 ULLS
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2022-07-06 13:37:56 +02:00
Szymon Morek
76e023b941 Link build option with L1 cache policy helper
Related-To: NEO-7003

Add L1CachePolicyHelper struct.
This struct is resposible for L1 cache policy
in build option, Surface State and stateless
caching. Currently default option for all
platforms is WBP (write by-pass)


Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2022-07-04 11:49:55 +02:00
Artur Harasimiuk
2b9827ad7d hw_cmds.h for XE refactor
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
2022-06-30 11:52:27 +02:00
Lukasz Jobczyk
e2441e0d75 Leave direct submission only on DG2 within XE_HPG
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2022-06-28 17:01:25 +02:00
Bartosz Dunajski
2c853adac3 Use LogicalStateHelper to program ComputeMode
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2022-06-27 15:25:55 +02:00
Artur Harasimiuk
4dff4e165c includes simplification
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
2022-06-27 15:08:46 +02:00
Szymon Morek
5236b34629 Set L1 policy globally
Related-To: NEO-7003

Add function to control l1 policy for both
stateless and surface state cache.


Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2022-06-27 14:57:31 +02:00
Artur Harasimiuk
4673a98074 includes simplification
use HW specific header instead generic one

Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
2022-06-24 22:07:18 +02:00
Mateusz Hoppe
673bf3b553 Move DebuggerL0 to shared
Related-To: NEO-7075

Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
2022-06-23 10:05:45 +02:00
Szymon Morek
2f46a7da63 Remove not needed function calls
Related-To: NEO-7003

Minor: remove empty function calls

Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2022-06-22 16:58:21 +02:00
Bartosz Dunajski
f4485ec541 Use LogicalStateHelper for SIP programming
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2022-06-22 13:46:57 +02:00