Related-To: GSD-11990
If user releases USM without defer policy, do not check whether
allocation is in use when trying to reuse.
Also, when context is being destroyed, use blocking policy to
make sure that tag is updated and driver will notice that
resource is no longer being used by GPU when cleaning up.
Signed-off-by: Szymon Morek <szymon.morek@intel.com>
-do not wait for event TS under cmdQ's lock
-determine latest enqueue operation in correct order
-do not recognize marker as a barrier in some cases
-fix mutex order in enqueu blit
Related-To: HSD-16027856705
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
Each host function gets its unique ID within a CSR,
uses 1 mi store to write ID - to signal that host function is ready,
and 1 mi semaphore wait will wait for the ID to be cleared,
Use 0th bit from ID as pending/completed flag,
host function ID is incremented by 2, and starts with 1.
So each ID will always have 0bit set.
This is a must have since semaphore wait can wait for 4 bytes only.
Adjust command buffer programming and patching logic to IDs.
Add hostFunction callable class - using invoke method,
which stores required information about callback.
Add host function streamer - stores all host function data
for a given CSR.
All user provided host functions are stored in unordered map,
where key is host function ID.
Add host function scheduler, and a thread pool - under debug flag
Single threaded scheduler loops over all registered host function streamers,
dispatch ready to execute host functions to thread pool.
Allow for out of order host functions execution for OOQ - under debug flag,
each host function has bool isInOrder flag which indicates if it can be
executed Out Of Order - in this mode, ID tag will be cleared immediately,
so semaphore wait will unblock before the host function execution.
Remove Host Function worker CV and atomics based implementation.
Rename classes
Related-To: NEO-14577
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
Temporarily disable offload test case related to additional blit
properties from the test
Related-To: NEO-13003
Signed-off-by: Young Jin Yoon <young.jin.yoon@intel.com>
Signed-off-by: Bellekallu Rajkiran <bellekallu.rajkiran@intel.com>
When is2MBLocalMemAlignmentEnabled returns true,
increase pool size for builtins from 64k to 2MB.
Additionally, set appropriate alignment for kernel ISA heap allocations.
Additionally, configure isaAllocationPageSize based on productHelper.
Related-To: NEO-12287
Signed-off-by: Fabian Zwoliński <fabian.zwolinski@intel.com>
While this code builds on ARM64, it cannot execute properly because
__rdtsc() is only available on x86. clinfo returns no platform which
gives the incorrect impression that KMD or UMD is not available. A
better fix is still needed but at least clinfo runs.
Signed-off-by: Francois Dugast <francois.dugast@intel.com>
Add support for reporting pitchAlign and maxSupportedPitch for 2D linear
pitched allocations. This change addresses missing device properties
required for SYCL bindless image E2E tests. And removed unused
ze_bindless_image_exp.h file.
Resolves: NEO-16433
Signed-off-by: Aleksandra Nizio <aleksandra.nizio@intel.com>
